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This generational list of Intel processors attempts to present all of Intel's processors from the pioneering 4-bit
First microprocessor (single-chip IC processor)
* Introduced November 15, 1971
* Clock rate 740 kHz
* 0.07 MIPS
* Bus width: 4 bits (multiplexed address/data due to limited pins)
* PMOS
* 2,300 transistors at 10 
* Introduced in 1974 by Intel
* Clock speed was 740 kHz (same as the 4004 microprocessor)
* 3,000 transistors
* Interrupt features were available
* Programmable memory size: 8 KB (8192 B)
* 640 bytes of data memory
* 24-pin DIP
* Introduced April 1, 1972
* Clock rate 500 kHz (8008-1: 800 kHz)
* 0.05 MIPS
* Bus width: 8 bits (multiplexed address/data due to limited pins)
* Enhancement load PMOS logic
* 3,500 transistors at 10 ΞΌm
* Addressable memory 16 KB
* Typical in early 8-bit microcomputers, dumb terminals, general calculators, bottling machines
* Developed in tandem with 4004
* Originally intended for use in the Datapoint 2200 microcomputer
* Key volume deployment in Texas Instruments 742 microcomputer in >3,000 Ford dealerships
* Introduced April 1, 1974
* Clock rate 2 MHz (very rare 8080B: 3 MHz)
* 0.29 MIPS
* Data bus width: 8 bits, address bus: 16 bits
* Enhancement load NMOS logic
* 4,500 transistors at 6 ΞΌm
* 
* Introduced March 1976
* Clock rate 3 MHz
* 0.37 MIPS
* Data bus width: 8 bits, address bus: 16 bits
* Depletion load NMOS logic
* 6,500 transistors at 3 ΞΌm
* Binary compatible downward with the 8080
* Used in Toledo scales. Also used as a computer peripheral controller β modems, hard disks, printers, etc.
*
* Single accumulator Harvard architecture
Introduced in the third quarter of 1974, these
* Introduced June 8, 1978
* Clock rates:
** 5 MHz, 0.33 MIPS
** 8 MHz, 0.66 MIPS
** 10 MHz, 0.75 MIPS
* The memory is divided into odd and even banks. It accesses both banks concurrently to read 16 bits of data in one clock cycle
* Data bus width: 16 bits, address bus: 20 bits
* 29,000 transistors at 3 ΞΌm
* Addressable memory 1 megabyte (1024B)
* Up to 10Γ the performance of 8080
* First used in the Compaq Deskpro IBM PC-compatible computers. Later used in portable computing, and in the IBM 
* Introduced June 1, 1979
* Clock rates:
** 4.77 MHz, 0.33 MIPS
** 8 MHz, 0.66 MIPS
* 16-bit internal architecture
* External data bus width: 8 bits, address bus: 20 bits
* 29,000 transistors at 3 ΞΌm
* Addressable memory 1 megabyte
* Identical to 8086 except for its 8-bit external bus (hence an ''8'' instead of a ''6'' at the end); identical Execution Unit (EU), different Bus Interface Unit (BIU)
* Used in 
* Introduced 1982
* Clock rates
** 6 MHz, > 1 MIPS
* 55,000 transistors
* Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor (these were at fixed addresses which differed from the IBM PC, although it was used by several PC compatible vendors such as Australian company Cleveland)
* Added a few opcodes and exceptions to the 8086 design, otherwise identical instruction set to 8086 and 8088
** BOUND, ENTER, LEAVE
** INS, OUTS
** IMUL imm, PUSH imm, PUSHA, POPA
** RCL/RCR/ROL/ROR/SHL/SHR/SAL/SAR reg, imm
* Address calculation and shift operations are faster than 8086
* Used mostly in embedded applications β controllers, point-of-sale systems, terminals, and the like
* Used in several non-PC compatible DOS computers including RM Nimbus, Tandy 2000, and CP/M 86 Televideo PM16 server
* Later renamed to iAPX 186
* Introduced February 2, 1982
* Clock rates:
** 6 MHz, 0.9 MIPS
** 8 MHz, 10 MHz, 1.5 MIPS
** 12.5 MHz, 2.66 MIPS
** 16 MHz, 20 MHz and 25 MHz available.
* Data bus width: 16 bits, address bus: 24 bits
* Included memory protection hardware to support multitasking operating systems with per-process address space.
* 134,000 transistors at 1.5 ΞΌm
* Addressable memory 16 MB
* Added protected-mode features to 8086 with essentially the same instruction set
* 3β6Γ the performance of the 8086
* Widely used in IBM PC AT and AT clones contemporary to it
* Introduced April 5, 1988
*
* Introduced February 26, 1989
*
* Introduced August 23, 2000
*
* Introduced October 17, 1985
* Clock rates:
** 16 MHz, 5 MIPS
** 20 MHz, 6 to 7 MIPS, introduced February 16, 1987
** 25 MHz, 7.5 MIPS, introduced April 4, 1988
** 33 MHz, 9.9 MIPS (9.4 SPECint92 on Compaq/i 16 KB L2), introduced April 10, 1989
* Data bus width: 32 bits, address bus: 32 bits
* 275,000 transistors at 1 ΞΌm
* Addressable memory 4 GB (4 Γ 1024 B)
* Virtual memory 64 TB (64 Γ 1024 B)
* First x86 chip to handle
* Introduced June 16, 1988
* Clock rates:
** 16 MHz, 2.5 MIPS
** 20 MHz, 3.1 MIPS, introduced January 25, 1989
** 25 MHz, 3.9 MIPS, introduced January 25, 1989
** 33 MHz, 5.1 MIPS, introduced October 26, 1992
* 32-bit internal architecture
* External data bus width: 16 bits
* External address bus width: 24 bits
* 275,000 transistors at 1 ΞΌm
* Addressable memory 16 MB
* Virtual memory 64 TB
* Narrower buses enable low-cost 32-bit processing
* Used in entry-level desktop and portable computing
* No math co-processor
* No commercial software used protected mode or virtual storage for many years
* Later renamed Intel386 SX
* Introduced January 16, 1989; discontinued June 15, 2001
* Variant of 386SX intended for embedded systems
* No "real mode", starts up directly in "protected mode"
* Replaced by much more successful 80386EX from 1994
* Introduced October 15, 1990
* Clock rates:
** 20 MHz, 4.21 MIPS
** 25 MHz, 5.3 MIPS, introduced September 30, 1991
* 32-bit internal architecture
* External bus width: 16 bits
* 855,000 transistors at 1 ΞΌm
* Addressable memory 4 GB
* Virtual memory 64 TB
* First chip specifically made for portable computers because of low power consumption of chip
* Highly integrated, includes cache, bus, and memory controllers
* Introduced August 1994
* Variant of 80386SX intended for embedded systems
* Static core (i.e. may run as slowly (and thus, power efficiently) as desired) down to full halt
* On-chip peripherals:
** Clock and power management
** Timers/counters
** Watchdog timer
** Serial I/O units (sync and async) and parallel I/O
**
* Introduced April 10, 1989
* Clock rates:
** 25 MHz, 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
** 33 MHz, 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KB L2), introduced May 7, 1990
** 50 MHz, 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KB L2), introduced June 24, 1991
* Bus width: 32 bits
* 1.2 million transistors at 1 ΞΌm; the 50 MHz was at 0.8 ΞΌm
* Addressable memory 4 GB
* Virtual memory 64 TB
* Level 1 cache of 8 KB on chip
* Math coprocessor on chip
* 50Γ performance of the 8088
* Officially named Intel486 DX
* Used in desktop computing and servers
* Family 4 model 1
* Introduced November 9, 1992
* Clock rates:
** 20 MHz, 15.4 MIPS
** 25 MHz, 19 MIPS
** 33 MHz, 25 MIPS
* Bus width: 32 bits
* 1.4 million transistors at 0.8 ΞΌm
* Addressable memory 4 GB
* Virtual memory 64 TB
* Officially named Intel486 SL
* Used in notebook computers
* Family 4 model 4
* Introduced March 7, 1994
* Clock rates:
** 75 MHz, 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KB L2)
** 100 MHz, 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KB L2)
* 1.6 million transistors at 0.6 ΞΌm
* Bus width: 32 bits
* Addressable memory 4 GB
* Virtual memory 64 TB
* Socket 3 168-pin PGA Package, or 208 sq. ftP package
* Officially named Intel486 DX4
* Used in high performance entry-level desktops and value notebooks
* Family 4 model 8
P54CS β 0.35 ΞΌm process technology
** 3.3 million transistors
** 90 mm2 die size
** Family 5 model 2
** Variants
** Socket 5 296/320-pin PGA package
*** 133 MHz, 218.9 MIPS (4.14 SPECint95, 3.12 SPECfp95 on Xpress 1 MB L2)
**** Introduced June 12, 1995
*** 150, 166 MHz, 230 and 247 MIPS respectively
**** Introduced January 4, 1996
** Socket 7 296/321-pin PGA package
*** 200 MHz, 270 MIPS (5.47 SPECint95, 3.68 SPECfp95)
**** Introduced June 10, 1996
* P55C β 0.35 ΞΌm process technology
** Introduced January 8, 1997
** Intel MMX (instruction set) support
** Socket 7 296/321 pin PGA (pin grid array) package
** 16 KB L1 instruction cache
** 16 KB data cache
** 4.5 million transistors
** System bus clock rate 66 MHz
** Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8
** Variants
*** 166, 200 MHz introduced January 8, 1997
*** 233 MHz introduced June 2, 1997
*** 133 MHz (Mobile)
*** 166, 266 MHz (Mobile) introduced January 12, 1998
*** 200, 233 MHz (Mobile) introduced September 8, 1997
*** 300 MHz (Mobile) introduced January 7, 1999
* Introduced November 1, 1995
* Multichip Module (2 die)
* Precursor to Pentium II and III
* Primarily used in server systems
* Socket 8 processor package (387 pins; Dual SPGA)
* 5.5 million transistors
* Family 6 model 1
* 0.6 ΞΌm process technology
** 16 KB L1 cache
** 256 KB integrated L2 cache
** 60 MHz system bus clock rate
** Variants
*** 150 MHz
* 0.35 ΞΌm process technology, (two die, a 0.35 ΞΌm CPU with 0.6 ΞΌm L2 cache)
** 5.5 million transistors
** 512 KB or 256 KB integrated L2 cache
** 60 or 66 MHz system bus clock rate
** Variants
*** 150 MHz (60 MHz bus clock rate, 256 KB 0.5 ΞΌm cache) introduced November 1, 1995
*** 166 MHz (66 MHz bus clock rate, 512 KB 0.35 ΞΌm cache) introduced November 1, 1995
*** 180 MHz (60 MHz bus clock rate, 256 KB 0.6 ΞΌm cache) introduced November 1, 1995
*** 200 MHz (66 MHz bus clock rate, 256 KB 0.6 ΞΌm cache) introduced November 1, 1995
*** 200 MHz (66 MHz bus clock rate, 512 KB 0.35 ΞΌm cache) introduced November 1, 1995
*** 200 MHz (66 MHz bus clock rate, 1 MB 0.35 ΞΌm cache) introduced August 18, 1997
* Introduced May 7, 1997
* Pentium Pro with MMX and improved
* Katmai β 0.25 ΞΌm process technology
** Introduced February 26, 1999
** Improved PII (i.e. P6-based core) now including
* Banias 0.13 ΞΌm process technology
** Introduced March 2003
** 64 KB L1 cache
** 1 MB L2 cache (integrated)
** Based on Pentium III core, with
* Banias-512 0.13 ΞΌm process technology
** Introduced March 2003
** 64 KB L1 cache
** 512 KB L2 cache (integrated)
**
* Yonah 0.065 ΞΌm ( 65 nm) process technology
** Introduced January 2006
** 533/667 MHz front-side bus
** 2 MB (Shared on Duo) L2 cache
** SSE3 SIMD instructions
** 31W TDP (T versions)
** Family 6, Model 14
** Variants:
*** Intel Core Duo T2700 2.33 GHz
*** Intel Core Duo T2600 2.16 GHz
*** Intel Core Duo T2500 2 GHz
*** Intel Core Duo T2450 2 GHz
*** Intel Core Duo T2400 1.83 GHz
*** Intel Core Duo T2300 1.66 GHz
*** Intel Core Duo T2050 1.6 GHz
*** Intel Core Duo T2300e 1.66 GHz
*** Intel Core Duo T2080 1.73 GHz
*** Intel Core Duo L2500 1.83 GHz (low voltage, 15 W TDP)
*** Intel Core Duo L2400 1.66 GHz (low voltage, 15 W TDP)
*** Intel Core Duo L2300 1.5 GHz (low voltage, 15 W TDP)
*** Intel Core Duo U2500 1.2 GHz (ultra-low voltage, 9 W TDP)
*** Intel Core Solo T1350 1.86 GHz (533 FSB)
*** Intel Core Solo T1300 1.66 GHz
*** Intel Core Solo T1200 1.5 GHz
* 0.18 ΞΌm process technology (1.40 and 1.50 GHz)
** Introduced November 20, 2000
** L2 cache was 256 KB Advanced Transfer cache (integrated)
** Processor package Style was PGA423, PGA478
** System bus clock rate 400 MHz
**
* Introduced September 2003
* "Extreme Edition"
* Built from the Xeon's "Gallatin" core, but with 2 MB cache
* New instruction set, not at all related to x86
* Before the feature was eliminated ( Montecito, July 2006) IA-64 processors supported 32-bit x86 in hardware, but slowly (see its 2001 market reception and 2006 architectural changes)
* Code name Merced
* Family 7
* Released May 29, 2001
* 733 MHz and 800 MHz
* 2 MB cache
* All recalled and replaced by Itanium 2
* Dual-core microprocessor
* No Hyper-Threading
* 800 (4Γ200) MHz front-side bus
* LGA 775 (Socket T)
* Smithfield (Pentium D) β 90 nm process technology (2.66β3.2 GHz)
** Introduced May 26, 2005
** 2.66β3.2 GHz (model numbers 805β840)
** 230 million transistors
** 1 MB Γ 2 (non-shared, 2 MB total) L2 cache
** Cache coherency between cores requires communication over the FSB
** Performance increase of 60% over similarly clocked Prescott
** 2.66 GHz (533 MHz FSB) Pentium D 805 introduced December 2005
** Contains 2Γ Prescott dies in one package
** Family 15 Model 4
*
* Dual-core microprocessor
* Enabled Hyper-Threading
* 800 (4Γ200) MHz front-side bus
* Smithfield (Pentium Extreme Edition) β 90 nm process technology (3.2 GHz)
** Variants
*** Pentium 840 EE β 3.20 GHz (2 Γ 1 MB L2)
* Presler (Pentium Extreme Edition) β 65 nm process technology (3.46, 3.73)
** 2 MB Γ 2 (non-shared, 4 MB total) L2 cache
** Variants
*** Pentium 955 EE β 3.46 GHz, 1066 MHz front-side bus
*** Pentium 965 EE β 3.73 GHz, 1066 MHz front-side bus
*** Pentium 969 EE β 3.73 GHz, 1066 MHz front-side bus
* Conroe β 65 nm process technology
** Desktop CPU (SMP support restricted to 2 CPUs)
** Two cores on one die
** Introduced July 27, 2006
** SSSE3 SIMD instructions
** 291 million transistors
** 64 KB of L1 cache per core (32+32 KB 8-way)
** Intel VT-x, multiple OS support
** TXT, enhanced security hardware extensions
** Execute Disable Bit
** EIST (Enhanced Intel SpeedStep Technology)
** iAMT2 (Intel Active Management Technology), remotely manage computers
** Intel Management Engine introduced
** LGA 775
** Variants
*** Core 2 Duo E6850, 3.00 GHz (4 MB L2, 1333 MHz FSB)
*** Core 2 Duo E6800, 2.93 GHz (4 MB L2, 1066 MHz FSB)
*** Core 2 Duo E6750, 2.67 GHz (4 MB L2, 1333 MHz FSB, 65 W)
*** Core 2 Duo E6700, 2.67 GHz (4 MB L2, 1066 MHz FSB)
*** Core 2 Duo E6600, 2.40 GHz (4 MB L2, 1066 MHz FSB, 65 W)
*** Core 2 Duo E6550, 2.33 GHz (4 MB L2, 1333 MHz FSB)
*** Core 2 Duo E6420, 2.13 GHz (4 MB L2, 1066 MHz FSB)
*** Core 2 Duo E6400, 2.13 GHz (2 MB L2, 1066 MHz FSB)
*** Core 2 Duo E6320, 1.86 GHz (4 MB L2, 1066 MHz FSB) Family 6, Model 15, Stepping 6
*** Core 2 Duo E6300, 1.86 GHz (2 MB L2, 1066 MHz FSB)
* Conroe XE β 65 nm process technology
** Desktop Extreme Edition CPU (SMP support restricted to 2 CPUs)
** Introduced July 27, 2006
** Same features as Conroe
** LGA 775
** Variants
*** Core 2 Extreme X6800 β 2.93 GHz (4 MB L2, 1066 MHz FSB)
* Allendale (Intel Core 2) β 65 nm process technology
** Desktop CPU (SMP support restricted to 2 CPUs)
** Two CPUs on one die
** Introduced January 21, 2007
** SSSE3 SIMD instructions
** 167 million transistors
** TXT, enhanced security hardware extensions
** Execute Disable Bit
** EIST (Enhanced Intel SpeedStep Technology)
** iAMT2 (Intel Active Management Technology), remotely manage computers
** LGA 775
** Variants
*** Core 2 Duo E4700, 2.60 GHz (2 MB L2, 800 MHz FSB)
*** Core 2 Duo E4600, 2.40 GHz (2 MB L2, 800 MHz FSB)
*** Core 2 Duo E4500, 2.20 GHz (2 MB L2, 800 MHz FSB)
*** Core 2 Duo E4400, 2.00 GHz (2 MB L2, 800 MHz FSB)
*** Core 2 Duo E4300, 1.80 GHz (2 MB L2, 800 MHz FSB) Family 6, Model 15, Stepping 2
* Merom β 65 nm process technology
** Mobile CPU (SMP support restricted to 2 CPUs)
** Introduced July 27, 2006
** Family 6, Model 15
** Same features as Conroe
** Socket M / Socket P
** Variants
*** Core 2 Duo T7800, 2.60 GHz (4 MB L2, 800 MHz FSB) ( Santa Rosa platform)
*** Core 2 Duo T7700, 2.40 GHz (4 MB L2, 800 MHz FSB)
*** Core 2 Duo T7600, 2.33 GHz (4 MB L2, 667 MHz FSB)
*** Core 2 Duo T7500, 2.20 GHz (4 MB L2, 800 MHz FSB)
*** Core 2 Duo T7400, 2.16 GHz (4 MB L2, 667 MHz FSB)
*** Core 2 Duo T7300, 2.00 GHz (4 MB L2, 800 MHz FSB)
*** Core 2 Duo T7250, 2.00 GHz (2 MB L2, 800 MHz FSB)
*** Core 2 Duo T7200, 2.00 GHz (4 MB L2, 667 MHz FSB)
*** Core 2 Duo T7100, 1.80 GHz (2 MB L2, 800 MHz FSB)
*** Core 2 Duo T5600, 1.83 GHz (2 MB L2, 667 MHz FSB) Family 6, Model 15, Stepping 6
*** Core 2 Duo T5550, 1.83 GHz (2 MB L2, 667 MHz FSB, no VT)
*** Core 2 Duo T5500, 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)
*** Core 2 Duo T5470, 1.60 GHz (2 MB L2, 800 MHz FSB, no VT) Family 6, Model 15, Stepping 13
*** Core 2 Duo T5450, 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)
*** Core 2 Duo T5300, 1.73 GHz (2 MB L2, 533 MHz FSB, no VT)
*** Core 2 Duo T5270, 1.40 GHz (2 MB L2, 800 MHz FSB, no VT)
*** Core 2 Duo T5250, 1.50 GHz (2 MB L2, 667 MHz FSB, no VT)
*** Core 2 Duo T5200, 1.60 GHz (2 MB L2, 533 MHz FSB, no VT)
*** Core 2 Duo L7500, 1.60 GHz (4 MB L2, 800 MHz FSB) (low voltage)
*** Core 2 Duo L7400, 1.50 GHz (4 MB L2, 667 MHz FSB) (low voltage)
*** Core 2 Duo L7300, 1.40 GHz (4 MB L2, 800 MHz FSB) (low voltage)
*** Core 2 Duo L7200, 1.33 GHz (4 MB L2, 667 MHz FSB) (low voltage)
*** Core 2 Duo U7700, 1.33 GHz (2 MB L2, 533 MHz FSB) (ultra low voltage)
*** Core 2 Duo U7600, 1.20 GHz (2 MB L2, 533 MHz FSB) (ultra low voltage)
*** Core 2 Duo U7500, 1.06 GHz (2 MB L2, 533 MHz FSB) (ultra low voltage)
* Kentsfield β 65 nm process technology
** Two dual-core CPU dies in one package
** Desktop CPU quad-core (SMP support restricted to 4 CPUs)
** Introduced December 13, 2006
** Same features as Conroe but with 4 CPU cores
** 586 million transistors
** LGA 775
** Family 6, Model 15, Stepping 11
** Variants
*** Core 2 Extreme QX6850, 3 GHz (2Γ4 MB L2 cache, 1333 MHz FSB)
*** Core 2 Extreme QX6800, 2.93 GHz (2Γ4 MB L2 cache, 1066 MHz FSB) (April 9, 2007)
*** Core 2 Extreme QX6700, 2.66 GHz (2Γ4 MB L2 cache, 1066 MHz FSB) (November 14, 2006)
*** Core 2 Quad Q6700, 2.66 GHz (2Γ4 MB L2 cache, 1066 MHz FSB) (July 22, 2007)
*** Core 2 Quad Q6600, 2.40 GHz (2Γ4 MB L2 cache, 1066 MHz FSB) (January 7, 2007)
* Wolfdale β
here
* Intel Core2 Quad Mobile processor family β
* Allendale (Pentium Dual-Core) β 65 nm process technology
** Desktop CPU (SMP support restricted to 2 CPUs)
** Two cores on one die
** Introduced January 21, 2007
** SSSE3 SIMD instructions
** 167 million transistors
** TXT, enhanced security hardware extensions
** Execute Disable Bit
** EIST (Enhanced Intel SpeedStep Technology)
** Variants
*** Intel Pentium E2220, 2.40 GHz (1 MB L2, 800 MHz FSB)
*** Intel Pentium E2200, 2.20 GHz (1 MB L2, 800 MHz FSB)
*** Intel Pentium E2180, 2.00 GHz (1 MB L2, 800 MHz FSB)
*** Intel Pentium E2160, 1.80 GHz (1 MB L2, 800 MHz FSB)
*** Intel Pentium E2140, 1.60 GHz (1 MB L2, 800 MHz FSB)
* Wolfdale-3M (Pentium Dual-Core) β
* 2007: Teraflops Research Chip, an 80 cores processor prototype.
* 2009: Single-chip Cloud Computer, a research microprocessor containing the most Intel Architecture cores ever integrated on a silicon CPU chip: 48.
Intel Museum: History of the Microprocessor
Stealey A100 and A110
Intel Product Specifications
{{Intel Intel microprocessors Intel
This generational list of Intel processors attempts to present all of Intel's processors from the pioneering 4-bit 4004
The Intel 4004 is a 4-bit central processing unit (CPU) released by Intel Corporation in 1971. Sold for US$60, it was the first commercially produced microprocessor, and the first in a long line of Intel CPUs.
The 4004 was the first significa ...
(1971) to the present high-end offerings. Concise technical data is given for each product.
Latest
13th generation Core
Desktop (codenamed " Raptor Lake")
12th generation Core
Desktop (codenamed " Alder Lake")
Mobile (codenamed " Alder Lake")
11th generation Core
Desktop (codenamed " Rocket Lake")
Mobile (codenamed " Tiger Lake")
10th generation Core
Desktop (codenamed " Comet Lake")
Mobile (codenamed " Comet Lake", " Ice Lake", and " Amber Lake")
9th generation Core
Desktop (codenamed "
Coffee Lake Refresh
Coffee Lake is Intel's codename for its eighth generation Core microprocessor family, announced on September 25, 2017. It is manufactured using Intel's second 14 nm process node refinement. Desktop Coffee Lake processors introduced i5 and ...
")
8th generation Core
Desktop (codenamed " Coffee Lake")
Mobile (codenamed " Coffee Lake", " Amber Lake" and "
Whiskey Lake
Whiskey Lake is Intel's codename for a family of third 14 nm generation Skylake low-power mobile processors. Intel announced Whiskey Lake on August 28, 2018.
Changes
* 14++ nm process, same as Coffee Lake
* Increased turbo clocks (300β ...
")
7th generation Core
Desktop (codenamed " Kaby Lake" and " Skylake-X")
Mobile (codenamed " Kaby Lake" and "
Apollo Lake
Goldmont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. They allow only one thread per core.
The ''Apollo Lake'' platform with 14 nm Goldmont core was unv ...
")
All processors
All processors are listed in chronological order.The 4-bit processors
ΞΌm
The micrometre ( international spelling as used by the International Bureau of Weights and Measures; SI symbol: ΞΌm) or micrometer (American spelling), also commonly known as a micron, is a unit of length in the International System of Unit ...
* Addressable memory 640 bytes
* Program memory 4 KB (4096 B)
* Originally designed to be used in Busicom
was a Japanese company that manufactured and sold computer-related products headquartered in Taito, Tokyo. It owned the rights to Intel's first microprocessor, the Intel 4004, which they created in partnership with Intel in 1970.
Busicom ask ...
calculator
MCS-4 family:
* 4004 β CPU
A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, and ...
* 4001 β ROM & 4-bit Port
* 4002 β RAM & 4-bit Port
* 4003 β 10-bit Shift Register
* 4008 β Memory+I/O Interface
* 4009 β Memory+I/O Interface
* 4211 β General Purpose Byte I/O Port
* 4265 β Programmable General Purpose I/O Device
* 4269 β Programmable Keyboard Display Device
* 4289 β Standard Memory Interface for MCS-4/40
* 4308 β 8192-bit (1024 Γ 8) ROM w/ 4-bit I/O Ports
* 4316 β 16384-bit (2048 Γ 8) Static ROM
* 4702 β 2048-bit (256 Γ 8) EPROM
* 4801 β 5.185 MHz Clock Generator Crystal for 4004/4201A or 4040/4201A
The
8-bit
In computer architecture, 8-bit Integer (computer science), integers or other Data (computing), data units are those that are 8 bits wide (1 octet (computing), octet). Also, 8-bit central processing unit (CPU) and arithmetic logic unit (ALU) arc ...
processors
Assembly language
In computer programming, assembly language (or assembler language, or symbolic machine code), often referred to simply as Assembly and commonly abbreviated as ASM or asm, is any low-level programming language with a very strong correspondence be ...
downward compatible with 8008
* Addressable memory 64 KB (64 Γ 1024 B)
* Up to 10Γ the performance of the 8008
* Used in e.g. the Altair 8800
The Altair 8800 is a microcomputer designed in 1974 by MITS and based on the Intel 8080 CPU. Interest grew quickly after it was featured on the cover of the January 1975 issue of Popular Electronics and was sold by mail order through advertiseme ...
, traffic light controller, cruise missile
A cruise missile is a guided missile used against terrestrial or naval targets that remains in the atmosphere and flies the major portion of its flight path at approximately constant speed. Cruise missiles are designed to deliver a large warhe ...
* Required six support chips versus 20 for the 8008
CMOS
Complementary metalβoxideβsemiconductor (CMOS, pronounced "sea-moss", ) is a type of metalβoxideβsemiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFE ...
80C85 in Mars Sojourner
''Sojourner'' is a robotic Mars rover that landed in the Ares Vallis channel in the Chryse Planitia region of the Oxia Palus quadrangle on July 4, 1997. ''Sojourner'' was operational on Mars for 92 sols (95 Earth days). It was the first whee ...
, Radio Shack Model 100 portable
Microcontrollers
They are ICs with CPU, RAM, ROM (or PROM or EPROM), I/O Ports, Timers & Interrupts
Intel 8048
The MCS-48 microcontroller series, Intel's first microcontroller, was originally released in 1976. Its first members were 8048, 8035 and 8748. The 8048 is probably the most prominent member of the family. Initially, this family was produced u ...
* Single accumulator Harvard architecture
MCS-48 family:
* Intel 8020 β Single-Component 8-bit Microcontroller, 1 KB ROM, 64 Byte RAM, 13 I/O ports
* Intel 8021 β Single-Component 8-bit Microcontroller, 1 KB ROM, 64 Byte RAM, 21 I/O ports
* Intel 8022 β Single-Component 8-bit Microcontroller, With On-Chip A/D Converter
* Intel 8035 β Single-Component 8-bit Microcontroller, 64 Byte RAM
* Intel 8039 β Single-Component 8-bit Microcontroller, 128 Byte RAM
* Intel 8040 β Single-Component 8-bit Microcontroller, 256 Byte RAM
* Intel 8048 β Single-Component 8-bit Microcontroller, 1 KB ROM, 64 byte RAM, 27 I/O ports, 0.73 MIPS @ 11 MHz
* Intel 8049 β Single-Component 8-bit Microcontroller, 2 KB ROM, 128 byte RAM, 27 I/O ports,
* Intel 8050 β Single-Component 8-bit Microcontroller, 4 KB ROM, 256 byte RAM, 27 I/O ports,
* Intel 8748 β Single-Component 8-bit Microcontroller, 1 KB EPROM, 64 byte RAM, 27 I/O ports,
* Intel 8749 β Single-Component 8-bit Microcontroller, 2 KB EPROM, 128 byte RAM, 27 I/O ports,
* Intel 87P50 β Single-Component 8-bit Microcontroller, ext. ROM socket (2758/2716/2732), 256 byte RAM, 27 I/O ports
* Intel 8648 β Single-Component 8-bit Microcontroller, 1 KB OTP EPROM, 64 byte RAM, 27 I/O ports
* Intel 8041 β Universal Peripheral Interface 8-bit Slave Microcontroller, 1 KB ROM, 64 byte RAM
* Intel 8041AH β Universal Peripheral Interface 8-bit Slave Microcontroller, 1 KB ROM, 128 byte RAM
* Intel 8641 β Universal Peripheral Interface 8-bit Slave Microcontroller ?
* Intel 8741 β Universal Peripheral Interface 8-bit Slave Microcontroller, 1 KB EPROM, 64 byte RAM
* Intel 8741AH β Universal Peripheral Interface 8-bit Slave Microcontroller, 1 KB EPROM, 128 byte RAM
* Intel 8042 β Universal Peripheral Interface 8-bit Slave Microcontroller, 2 KB ROM, 256 byte RAM
* Intel 8742 β Universal Peripheral Interface 8-bit Slave Microcontroller, 2 KB EPROM, 128 byte RAM
* Intel 8742AH β Universal Peripheral Interface 8-bit Slave Microcontroller, 2 KB OTP EPROM, 256 byte RAM
* Intel 8243 β Input/Output Expander. The available 28-pin PLCC version in sampling for first quarter of 1986.
* Intel 8244 β General Purpose Graphics Display Device (ASIC NTSC/SECAM)
* Intel 8245 β General Purpose Graphics Display Device (ASIC PAL)
MCS-51
The Intel MCS-51 (commonly termed 8051) is a single chip microcontroller (MCU) series developed by Intel in 1980 for use in embedded systems. The architect of the Intel MCS-51 instruction set was John H. Wharton. Intel's original versions were p ...
family:
* 8031 β 8-bit Control-Oriented Microcontroller
* 8032 β 8-bit Control-Oriented Microcontroller
* 8044 β High Performance 8-bit Microcontroller
* 8344 β High Performance 8-bit Microcontroller
* 8744 β High Performance 8-bit Microcontroller
* 8051 β 8-bit Control-Oriented Microcontroller
* 8052 β 8-bit Control-Oriented Microcontroller
* 8054 β 8-bit Control-Oriented Microcontroller
* 8058 β 8-bit Control-Oriented Microcontroller
* 8351 β 8-bit Control-Oriented Microcontroller
* 8352 β 8-bit Control-Oriented Microcontroller
* 8354 β 8-bit Control-Oriented Microcontroller
* 8358 β 8-bit Control-Oriented Microcontroller
* 8751 β 8-bit Control-Oriented Microcontroller
* 8752 β 8-bit Control-Oriented Microcontroller
* 8754 β 8-bit Control-Oriented Microcontroller
* 8758 β 8-bit Control-Oriented Microcontroller
Intel 80151
The Intel MCS-51 (commonly termed 8051) is a single chip microcontroller (MCU) series developed by Intel in 1980 for use in embedded systems. The architect of the Intel MCS-51 instruction set was John H. Wharton. Intel's original versions were po ...
* Single accumulator Harvard architecture
MCS-151
The Intel MCS-51 (commonly termed 8051) is a single chip microcontroller (MCU) series developed by Intel in 1980 for use in embedded systems. The architect of the Intel MCS-51 instruction set was John H. Wharton. Intel's original versions were po ...
family:
* 80151 β High Performance 8-bit Control-Oriented Microcontroller
* 83151 β High Performance 8-bit Control-Oriented Microcontroller
* 87151 β High Performance 8-bit Control-Oriented Microcontroller
* 80152 β High Performance 8-bit Control-Oriented Microcontroller
* 83152 β High Performance 8-bit Control-Oriented Microcontroller
Intel 80251
The Intel MCS-51 (commonly termed 8051) is a single chip microcontroller (MCU) series developed by Intel in 1980 for use in embedded systems. The architect of the Intel MCS-51 instruction set was John H. Wharton. Intel's original versions were po ...
* Single accumulator Harvard architecture
MCS-251 family:
* 80251 β 8/16/32-bit
In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculation ...
Microcontroller
* 80252 β 8/16/32-bit Microcontroller
* 80452 β 8/16/32-bit Microcontroller
* 83251 β 8/16/32-bit Microcontroller
* 87251 β 8/16/32-bit Microcontroller
* 87253 β 8/16/32-bit Microcontroller
MCS-96 family
* 8061 β 16-bit Microcontroller (parent of MCS-96 family ROMless With A/D, most sold to Ford) * 8094 β16-bit
16-bit microcomputers are microcomputers that use 16-bit microprocessors.
A 16-bit register can store 216 different values. The range of integer values that can be stored in 16 bits depends on the integer representation used. With the two mos ...
Microcontroller (48-Pin ROMLess Without A/D)
* 8095 β 16-bit Microcontroller (48-Pin ROMLess With A/D)
* 8096 β 16-bit Microcontroller (68-Pin ROMLess Without A/D)
* 8097 β 16-bit Microcontroller (68-Pin ROMLess With A/D)
* 8394 β 16-bit Microcontroller (48-Pin With ROM Without A/D)
* 8395 β 16-bit Microcontroller (48-Pin With ROM With A/D)
* 8396 β 16-bit Microcontroller (68-Pin With ROM Without A/D)
* 8397 β 16-bit Microcontroller (68-Pin With ROM With A/D)
* 8794 β 16-bit Microcontroller (48-Pin With EROM Without A/D)
* 8795 β 16-bit Microcontroller (48-Pin With EROM With A/D)
* 8796 β 16-bit Microcontroller (68-Pin With EROM Without A/D)
* 8797 β 16-bit Microcontroller (68-Pin With EROM With A/D)
* 8098 β 16-bit Microcontroller
* 8398 β 16-bit Microcontroller
* 8798 β 16-bit Microcontroller
* 80196 β 16-bit Microcontroller
* 83196 β 16-bit Microcontroller
* 87196 β 16-bit Microcontroller
* 80296 β 16-bit Microcontroller
The bit-slice processor
3000 family
Introduced in the third quarter of 1974, these bit-slicing
Bit slicing is a technique for constructing a Processor (computing), processor from modules of processors of smaller bit width, for the purpose of increasing the word length; in theory to make an arbitrary ''n''-bit central processing unit ( ...
components used bipolar
Bipolar may refer to:
Astronomy
* Bipolar nebula, a distinctive nebular formation
* Bipolar outflow, two continuous flows of gas from the poles of a star
Mathematics
* Bipolar coordinates, a two-dimensional orthogonal coordinate system
* Bipolar ...
Schottky transistors. Each component implemented two bits of a processor function; packages could be interconnected to build a processor with any desired word length.
Members of the family:
* 3001 β Microcontrol Unit
* 3002 β 2-bit Arithmetic Logic Unit slice
* 3003 β Look-ahead Carry Generator
* 3205 β High-performance 1 of 8 Binary Decoder
* 3207 β Quad Bipolar-to-MOS Level Shifter and Driver
* 3208 β Hex Sense Amp and Latch for MOS Memories
* 3210 β TTL-to-MOS Level Shifter and High Voltage Clock Driver
* 3211 β ECL-to-MOS Level Shifter and High Voltage Clock Driver
* 3212 β Multimode Latch Buffer
* 3214 β Interrupt Control Unit
* 3216 β Parallel, Inverting Bi-Directional Bus Driver
* 3222 β Refresh Controller for 4K (4096 B) NMOS DRAMs
* 3226 β Parallel, Inverting Bi-Directional Bus Driver
* 3232 β Address Multiplexer and Refresh Counter for 4K DRAMs
* 3242 β Address Multiplexer and Refresh Counter for 16K (16 Γ 1024 B) DRAMs
* 3245 β Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K
* 3246 β Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K
* 3404 β High-performance 6-bit Latch
* 3408 β Hex Sense Amp and Latch for MOS Memories
* 3505 β Next generation processor
Bus width 2''n'' bits data/address (depending on number ''n'' of slices used)
The
16-bit
16-bit microcomputers are microcomputers that use 16-bit microprocessors.
A 16-bit register can store 216 different values. The range of integer values that can be stored in 16 bits depends on the integer representation used. With the two mos ...
processors: MCS-86 family
PS/2
The Personal System/2 or PS/2 is IBM's second generation of personal computers. Released in 1987, it officially replaced the IBM PC, XT, AT, and PC Convertible in IBM's lineup. Many of the PS/2's innovations, such as the 16550 UART (serial po ...
Model 25 and Model 30. Also used in the AT&T PC6300 / Olivetti M24, a popular IBM PC-compatible (predating the IBM PS/2 line)
* Used segment register
Memory segmentation is an operating system memory management technique of division of a computer's primary memory into segments or sections. In a computer system using segmentation, a reference to a memory location includes a value that identifie ...
s to access more than 64 KB of data at once, which many programmers complained made their work excessively difficult.
* The first x86 CPU
* Later renamed the iAPX 86Intel IAPX 86,88 User's Manual, August 1981, Intel order number 210201-001
IBM PC
The IBM Personal Computer (model 5150, commonly known as the IBM PC) is the first microcomputer released in the IBM PC model line and the basis for the IBM PC compatible de facto standard. Released on August 12, 1981, it was created by a team ...
and PC-XT and compatibles
* Later renamed the iAPX 88
80188
The Intel 80188 microprocessor was a variant of the Intel 80186. The 80188 had an 8-bit external data bus instead of the 16-bit bus of the 80186; this made it less expensive to connect to peripherals. The 16-bit registers and the one megabyte add ...
* A version of the 80186 with an 8-bit external data bus
* Later renamed the iAPX 188
32-bit
In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculation ...
processors: the non-x86 microprocessors
iAPX 432
The iAPX 432 (''Intel Advanced Performance Architecture'') is a discontinued computer architecture introduced in 1981. It was Intel's first 32-bit processor design. The main processor of the architecture, the ''general data processor'', is impl ...
* Introduced January 1, 1981 as Intel's first 32-bit
In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculation ...
microprocessor
* Multi-chip CPU
* Object/capability architecture
* Microcoded operating system primitives
* One terabyte virtual address space
* Hardware support for fault tolerance
* Two-chip General Data Processor (GDP), consists of 43201 and 43202
* 43203 Interface Processor (IP) interfaces to I/O subsystem
* 43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
* 43205 Memory Control Unit (MCU)
* Architecture and execution unit internal data base paths: 32 bits
* Clock rates:
** 5 MHz
** 7 MHz
** 8 MHz
RISC
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set comput ...
-like 32-bit
In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculation ...
architecture
* Predominantly used in embedded systems
* Evolved from the capability processor developed for the BiiN joint venture with Siemens
Siemens AG ( ) is a German multinational conglomerate corporation and the largest industrial manufacturing company in Europe headquartered in Munich with branch offices abroad.
The principal divisions of the corporation are ''Industry'', '' ...
* Many variants identified by two-letter suffixes
RISC
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set comput ...
32/ 64-bit architecture, with floating point pipeline characteristics very visible to programmer
* Used in the Intel iPSC/860 Hypercube
In geometry, a hypercube is an ''n''-dimensional analogue of a square () and a cube (). It is a closed, compact, convex figure whose 1- skeleton consists of groups of opposite parallel line segments aligned in each of the space's dimensions, ...
parallel supercomputer
* Mid-life kicker in the i870 processor (primarily a speed bump, some refinement/extension of instruction set)
* Used in the Intel Delta
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 series ...
massively parallel supercomputer prototype, emplaced at California Institute of Technology
* Used in the Intel Paragon
The Intel Paragon is a discontinued series of massively parallel supercomputers that was produced by Intel in the 1990s. The Paragon XP/S is a productized version of the experimental ''Touchstone Delta'' system that was built at Caltech, launched ...
massively parallel supercomputer, emplaced at Sandia National Laboratory
32-bit
In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculation ...
RISC
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set comput ...
microprocessor based on the ARM architecture
ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer (RISC) instruction set architectures for computer processors, configured ...
* Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors
32-bit
In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculation ...
processors: the 80386 range
32-bit
In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculation ...
data sets
* Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required at the time by Xenix and Unix. This memory capability spurred the development and availability of OS/2 and is a fundamental requirement for modern operating systems like Linux, Windows, and macOS
* First used by Compaq in the Deskpro 386. Used in desktop computing
* Unlike the DX naming convention of the 486 chips, it had no math co-processor
* Later renamed Intel386 DX
* Introduced January 16, 1989; discontinued June 15, 2001
* Variant of 386SX intended for embedded systems
* No "real mode", starts up directly in "protected mode"
* Replaced by much more successful 80386EX from 1994
DMA
DMA may refer to:
Arts
* ''DMA'' (magazine), a defunct dance music magazine
* Dallas Museum of Art, an art museum in Texas, US
* Danish Music Awards, an award show held in Denmark
* BT Digital Music Awards, an annual event in the UK
* Doctor of M ...
** RAM refresh
** JTAG
JTAG (named after the Joint Test Action Group which codified it) is an Technical standard, industry standard for verifying designs and testing printed circuit boards after manufacture.
JTAG implements standards for on-chip instrumentation in ele ...
test logic
* Significantly more successful than the 80376
* Used aboard several orbiting satellites and microsatellites
* Used in NASA's FlightLinux project
32-bit processors: the 80486 range
80486SX
The Intel 486, officially named i486 and also known as 80486, is a microprocessor. It is a higher-performance follow-up to the Intel 386. The i486 was introduced in 1989. It represents the fourth generation of binary compatible CPUs following the ...
* Introduced April 22, 1991
* Clock rates:
** 16 MHz, 13 MIPS
** 20 MHz, 16.5 MIPS, introduced September 16, 1991
** 25 MHz, 20 MIPS (12 SPECint92), introduced September 16, 1991
** 33 MHz, 27 MIPS (15.86 SPECint92), introduced September 21, 1992
* Bus width: 32 bits
* 1.185 million transistors at 1 ΞΌm and 900,000 at 0.8 ΞΌm
* Addressable memory 4 GB
* Virtual memory 64 TB
* Identical in design to 486DX but without a math coprocessor. The first version was an 80486DX with disabled math coprocessor in the chip and different pin configuration. If the user needed math coprocessor capabilities, he must add 487SX which was actually a 486DX with different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPU's with only 1 effectively turned on
* Officially named Intel486 SX
* Used in low-cost entry to 486 CPU desktop computing, as well as extensively in low cost mobile computing
* Upgradable with the Intel OverDrive processor
* Family 4 model 2
80486DX2
The Intel i486DX2, rumored as 80486DX2 (later renamed IntelDX2) is a CPU produced by Intel that was first introduced in 1992. The i486DX2 was nearly identical to the i486DX, but it had additional clock multiplier circuitry. It was the first chi ...
* Introduced March 3, 1992
* Runs at twice the speed of the external bus (FSB)
* Fits in Socket 3
* Clock rates:
** 40 MHz
** 50 MHz, 41 MIPS
** 66 MHz, 54 MIPS
* Officially named Intel486 DX2
* Family 4 model 3
32-bit processors: P5 microarchitecture
Original Pentium
* Bus width: 64 bits * System bus clock rate 60 or 66 MHz * Address bus: 32 bits * Addressable memory 4 GB * Virtual memory 64 TB *Superscalar
A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single instruction per clock cycle, a sup ...
architecture
* Runs on 3.3 volts (except the very first generation "P5")
* Used in desktops
* 8 KB of instruction cache
* 8 KB of data cache
* P5 β 0.8 ΞΌm process technology
** Introduced March 22, 1993
** 3.1 million transistors
** The only Pentium to run on 5 Volts
** Socket 4 273 pin PGA Package
** Package dimensions 2.16 in Γ 2.16 in
** Family 5 model 1
** Variants
*** 60 MHz, 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256 KB L2)
*** 66 MHz, 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256 KB L2)
* P54 β 0.6 ΞΌm process technology
** Socket 5 296/320-pin PGA package
** 3.2 million transistors
** Variants
*** 75 MHz, 126.5 MIPS (2.31 SPECint95, 2.02 SPECfp95 on Gateway P5 256K L2)
**** Introduced October 10, 1994
*** 90, 100 MHz, 149.8 and 166.3 MIPS respectively (2.74 SPECint95, 2.39 SPECfp95 on Gateway P5 256K L2 and 3.30 SPECint95, 2.59 SPECfp95 on Xpress 1ML2 respectively)
**** Introduced March 7, 1994
* P54CQS β 0.35 ΞΌm process technology
** Socket 5 296/320 pin PGA package
** 3.2 million transistors
** Variants
*** 120 MHz, 203 MIPS (3.72 SPECint95, 2.81 SPECfp95 on Xpress 1 MB L2)
**** Introduced March 27, 1995
*P54CS β 0.35 ΞΌm process technology
** 3.3 million transistors
** 90 mm2 die size
** Family 5 model 2
** Variants
** Socket 5 296/320-pin PGA package
*** 133 MHz, 218.9 MIPS (4.14 SPECint95, 3.12 SPECfp95 on Xpress 1 MB L2)
**** Introduced June 12, 1995
*** 150, 166 MHz, 230 and 247 MIPS respectively
**** Introduced January 4, 1996
** Socket 7 296/321-pin PGA package
*** 200 MHz, 270 MIPS (5.47 SPECint95, 3.68 SPECfp95)
**** Introduced June 10, 1996
32-bit
In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculation ...
processors: P6/ Pentium M microarchitecture
16-bit
16-bit microcomputers are microcomputers that use 16-bit microprocessors.
A 16-bit register can store 216 different values. The range of integer values that can be stored in 16 bits depends on the integer representation used. With the two mos ...
performance
* 242-pin Slot 1 (SEC) processor package
* Voltage identification pins
* 7.5 million transistors
* 32 KB L1 cache
* 512 KB frequency external L2 cache
* The ''Performance Enhanced'' mobile Pentium II (codenamed Dixon) had a full-speed 256 KB L2 cache
* Klamath β 0.35 ΞΌm process technology (233, 266, 300 MHz)
** 66 MHz system bus clock rate
** Family 6 model 3
** Variants
*** 233, 266, 300 MHz introduced May 7, 1997
* Deschutes β 0.25 ΞΌm process technology (333, 350, 400, 450 MHz)
** Introduced January 26, 1998
** 66 MHz system bus clock rate (''333 MHz variant''), 100 MHz system bus clock rate for all subsequent models
** Family 6 model 5
** Variants
*** 333 MHz introduced January 26, 1998
*** 350, 400 MHz introduced April 15, 1998
*** 450 MHz introduced August 24, 1998
*** 233, 266 MHz (Mobile) introduced April 2, 1998
*** 333 MHz Pentium II Overdrive processor for Socket 8 Introduced August 10, 1998
*** 300 MHz (Mobile) introduced September 9, 1998
*** 333 MHz (Mobile) introduced January 25, 1999
Celeron (Pentium II-based)
* Covington β 0.25 ΞΌm process technology ** Introduced April 15, 1998 ** 242-pin Slot 1 SEPP (Single Edge Processor Package) ** 7.5 million transistors ** 66 MHz system bus clock rate ** Slot 1 ** 32 KB L1 cache ** No L2 cache ** Variants *** 266 MHz introduced April 15, 1998 *** 300 MHz introduced June 9, 1998 * Mendocino β 0.25 ΞΌm process technology ** Introduced August 24, 1998 ** 242-pin Slot 1 SEPP (Single Edge Processor Package), Socket 370 PPGA package ** 19 million transistors ** 66 MHz system bus clock rate ** Slot 1, Socket 370 ** 32 KB L1 cache ** 128 KB integrated cache ** Family 6 model 6 ** Variants *** 300, 333 MHz introduced August 24, 1998 *** 366, 400 MHz introduced January 4, 1999 *** 433 MHz introduced March 22, 1999 *** 466 MHz *** 500 MHz introduced August 2, 1999 *** 533 MHz introduced January 4, 2000 *** 266 MHz (Mobile) *** 300 MHz (Mobile) *** 333 MHz (Mobile) introduced April 5, 1999 *** 366 MHz (Mobile) *** 400 MHz (Mobile) *** 433 MHz (Mobile) *** 450 MHz (Mobile) introduced February 14, 2000 *** 466 MHz (Mobile) *** 500 MHz (Mobile) introduced February 14, 2000 Pentium II Xeon ''(chronological entry)'' * Introduced June 29, 1998Streaming SIMD Extensions
In computing, Streaming SIMD Extensions (SSE) is a single instruction, multiple data (SIMD) instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series of Central processing units (CPUs) ...
(SSE)
** 9.5 million transistors
** 512 KB (512 Γ 1024 B) bandwidth L2 External cache
** 242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package
** System bus clock rate 100 MHz, 133 MHz (B-models)
** Slot 1
** Family 6 model 7
** Variants
*** 450, 500 MHz introduced February 26, 1999
*** 550 MHz introduced May 17, 1999
*** 600 MHz introduced August 2, 1999
*** 533, 600 MHz introduced (133 MHz bus clock rate) September 27, 1999
* Coppermine β 0.18 ΞΌm process technology
** Introduced October 25, 1999
** 28.1 million transistors
** 256 KB (512 Γ 1024 B) Advanced Transfer L2 cache (integrated)
** 242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (flip-chip pin grid array) package
** System Bus clock rate 100 MHz (E-models), 133 MHz (EB models)
** Slot 1, Socket 370
** Family 6 model 8
** Variants
*** 500 MHz (100 MHz bus clock rate)
*** 533 MHz
*** 550 MHz (100 MHz bus clock rate)
*** 600 MHz
*** 600 MHz (100 MHz bus clock rate)
*** 650 MHz (100 MHz bus clock rate) introduced October 25, 1999
*** 667 MHz introduced October 25, 1999
*** 700 MHz (100 MHz bus clock rate) introduced October 25, 1999
*** 733 MHz introduced October 25, 1999
*** 750, 800 MHz (100 MHz bus clock rate) introduced December 20, 1999
*** 850 MHz (100 MHz bus clock rate) introduced March 20, 2000
*** 866 MHz introduced March 20, 2000
*** 933 MHz introduced May 24, 2000
*** 1000 MHz introduced March 8, 2000 (not widely available at time of release)
*** 1100 MHz
*** 1133 MHz (first version recalled, later re-released)
*** 400, 450, 500 MHz (Mobile) introduced October 25, 1999
*** 600, 650 MHz (Mobile) introduced January 18, 2000
*** 700 MHz (Mobile) introduced April 24, 2000
*** 750 MHz (Mobile) introduced June 19, 2000
*** 800, 850 MHz (Mobile) introduced September 25, 2000
*** 900, 1000 MHz (Mobile) introduced March 19, 2001
* Tualatin β 0.13 ΞΌm process technology
** Introduced July 2001
** 28.1 million transistors
** 32 KB (32 Γ 1024 B) L1 cache
** 256 KB or 512 KB Advanced Transfer L2 cache (integrated)
** 370-pin FC-PGA2
A pin grid array (PGA) is a type of integrated circuit packaging. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") a ...
(flip-chip pin grid array) package
** 133 MHz system bus clock rate
** Socket 370
** Family 6 model 11
** Variants
*** 1133 MHz (256 KB L2)
*** 1133 MHz (512 KB L2)
*** 1200 MHz
*** 1266 MHz (512 KB L2)
*** 1333 MHz
*** 1400 MHz (512 KB L2)
Pentium II Xeon and Pentium III Xeon
* PII Xeon ** Variants *** 400 MHz introduced June 29, 1998 *** 450 MHz (512 KB L2 cache) introduced October 6, 1998 *** 450 MHz (1 MB and 2 MB L2 cache) introduced January 5, 1999 * PIII Xeon ** Introduced October 25, 1999 ** 9.5 million transistors at 0.25 ΞΌm or 28 million at 0.18 ΞΌm ** L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated) ** Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330 ** System Bus clock rate 133 MHz (256 KB L2 cache) or 100 MHz (1β2 MB L2 cache) ** System Bus width: 64 bits ** Addressable memory: 64 GB ** Used in two-way servers and workstations (256 KB L2) or 4- and 8-way servers (1β2 MB L2) ** Family 6 model 10 ** Variants *** 500 MHz ( 0.25 ΞΌm process) introduced March 17, 1999 *** 550 MHz (0.25 ΞΌm process) introduced August 23, 1999 *** 600 MHz ( 0.18 ΞΌm process, 256 KB L2 cache) introduced October 25, 1999 *** 667 MHz (0.18 ΞΌm process, 256 KB L2 cache) introduced October 25, 1999 *** 733 MHz (0.18 ΞΌm process, 256 KB L2 cache) introduced October 25, 1999 *** 800 MHz (0.18 ΞΌm process, 256 KB L2 cache) introduced January 12, 2000 *** 866 MHz (0.18 ΞΌm process, 256 KB L2 cache) introduced April 10, 2000 *** 933 MHz (0.18 ΞΌm process, 256 KB L2 cache) *** 1000 MHz (0.18 ΞΌm process, 256 KB L2 cache) introduced August 22, 2000 *** 700 MHz (0.18 ΞΌm process, 1β2 MB L2 cache) introduced May 22, 2000Celeron (Pentium III Coppermine-based)
* Coppermine-128, 0.18 ΞΌm process technology ** Introduced March, 2000 **Streaming SIMD Extensions
In computing, Streaming SIMD Extensions (SSE) is a single instruction, multiple data (SIMD) instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series of Central processing units (CPUs) ...
(SSE)
** Socket 370, FC-PGA processor package
** 28.1 million transistors
** 66 MHz system bus clock rate, 100 MHz system bus clock rate from January 3, 2001
** 32 KB L1 cache
** 128 KB Advanced Transfer L2 cache
** Family 6 model 8
** Variants
*** 533 MHz
*** 566 MHz
*** 600 MHz
*** 633, 667, 700 MHz introduced June 26, 2000
*** 733, 766 MHz introduced November 13, 2000
*** 800 MHz introduced January 3, 2001
*** 850 MHz introduced April 9, 2001
*** 900 MHz introduced July 2, 2001
*** 950, 1000, 1100 MHz introduced August 31, 2001
*** 550 MHz (Mobile)
*** 600, 650 MHz (Mobile) introduced June 19, 2000
*** 700 MHz (Mobile) introduced September 25, 2000
*** 750 MHz (Mobile) introduced March 19, 2001
*** 800 MHz (Mobile)
*** 850 MHz (Mobile) introduced July 2, 2001
*** 600 MHz (LV Mobile)
*** 500 MHz (ULV Mobile) introduced January 30, 2001
*** 600 MHz (ULV Mobile)
XScale ''(chronological entry β non-x86 architecture)''
* Introduced August 23, 2000
Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 ''(chronological entries)''
* Introduced April 2000 β July 2002
Pentium III Tualatin-based
* Tualatin β 0.13 ΞΌm process technology ** 32 KB L1 cache ** 512KB Advanced Transfer L2 cache ** 133 MHz system bus clock rate ** Socket 370 ** Variants *** 1.0 GHz *** 1.13 GHz *** 1.26 GHz *** 1.4 GHzCeleron (Pentium III Tualatin-based)
* Tualatin Celeron β 0.13 ΞΌm process technology ** 32 KB L1 cache ** 256 KB Advanced Transfer L2 cache ** 100 MHz system bus clock rate ** Socket 370 ** Family 6 model 11 ** Variants *** 1.0 GHz *** 1.1 GHz *** 1.2 GHz *** 1.3 GHz *** 1.4 GHzSSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
SIMD instructions and deeper pipeline
** 77 million transistors
** Micro-FCPGA, Micro-FCBGA processor package
** Heart of the Intel mobile '' Centrino'' system
** 400 MHz Netburst-style system bus
** Family 6 model 9
** Variants
*** 900 MHz (ultra-low voltage)
*** 1.0 GHz (ultra-low voltage)
*** 1.1 GHz (low voltage)
*** 1.2 GHz (low voltage)
*** 1.3 GHz
*** 1.4 GHz
*** 1.5 GHz
*** 1.6 GHz
*** 1.7 GHz
* Dothan 0.09 ΞΌm ( 90 nm) process technology
** Introduced May 2004
** 2 MB L2 cache
** 140 million transistors
** Revised data prefetch unit
** 400 MHz Netburst-style system bus
** 21 W TDP
** Family 6 model 13
** Variants
*** 1.00 GHz (Pentium M 723) (ultra-low voltage, 5 W TDP)
*** 1.10 GHz (Pentium M 733) (ultra-low voltage, 5 W TDP)
*** 1.20 GHz (Pentium M 753) (ultra-low voltage, 5 W TDP)
*** 1.30 GHz (Pentium M 718) (low voltage, 10 W TDP)
*** 1.40 GHz (Pentium M 738) (low voltage, 10 W TDP)
*** 1.50 GHz (Pentium M 758) (low voltage, 10 W TDP)
*** 1.60 GHz (Pentium M 778) (low voltage, 10 W TDP)
*** 1.40 GHz (Pentium M 710)
*** 1.50 GHz (Pentium M 715)
*** 1.60 GHz (Pentium M 725)
*** 1.70 GHz (Pentium M 735)
*** 1.80 GHz (Pentium M 745)
*** 2.00 GHz (Pentium M 755)
*** 2.10 GHz (Pentium M 765)
* Dothan 533 0.09 ΞΌm ( 90 nm) process technology
** Introduced Q1 2005
** Same as Dothan except with a 533 MHz NetBurst-style system bus and 27 W TDP
** Variants
*** 1.60 GHz (Pentium M 730)
*** 1.73 GHz (Pentium M 740)
*** 1.86 GHz (Pentium M 750)
*** 2.00 GHz (Pentium M 760)
*** 2.13 GHz (Pentium M 770)
*** 2.26 GHz (Pentium M 780)
* Stealey 0.09 ΞΌm ( 90 nm) process technology
** Introduced Q2 2007
** 512 KB L2, 3 W TDP
** Variants
*** 600 MHz (A100)
*** 800 MHz (A110)
SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
SIMD instructions
** No SpeedStep technology, is not part of the ' Centrino' package
** Family 6 model 9
** Variants
*** 310, 1.20 GHz
*** 320, 1.30 GHz
*** 330, 1.40 GHz
*** 340, 1.50 GHz
* Dothan-1024 90 nm process technology
** 64 KB L1 cache
** 1 MB L2 cache (integrated)
** SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
SIMD instructions
** No SpeedStep technology, is not part of the ' Centrino' package
** Variants
*** 350, 1.30 GHz
*** 350J, 1.30 GHz, with Execute Disable bit
*** 360, 1.40 GHz
*** 360J, 1.40 GHz, with Execute Disable bit
*** 370, 1.50 GHz, with Execute Disable bit
**** Family 6, Model 13, Stepping 8
*** 380, 1.60 GHz, with Execute Disable bit
*** 390, 1.70 GHz, with Execute Disable bit
* Yonah-1024 65 nm process technology
** 64 KB L1 cache
** 1 MB L2 cache (integrated)
** SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit
** No SpeedStep technology, is not part of the ' Centrino' package
** Variants
*** 410, 1.46 GHz
*** 420, 1.60 GHz,
*** 423, 1.06 GHz (ultra-low voltage)
*** 430, 1.73 GHz
*** 440, 1.86 GHz
*** 443, 1.20 GHz (ultra-low voltage)
*** 450, 2.00 GHz
Dual-Core Xeon LV
* Sossaman 0.065 ΞΌm ( 65 nm) process technology ** Introduced March 2006 ** Based on Yonah core, with SSE3 SIMD instructions ** 667 MHzfrontside bus
A front-side bus (FSB) is a computer communication interface ( bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between the ...
** 2 MB shared L2 cache
** Variants
*** 2.0 GHz
32-bit processors: NetBurst microarchitecture
SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
SIMD Extensions
** 42 million transistors
** Used in desktops and entry-level workstations
* 0.18 ΞΌm process technology (1.7 GHz)
** Introduced April 23, 2001
** See the 1.4 and 1.5 chips for details
* 0.18 ΞΌm process technology (1.6 and 1.8 GHz)
** Introduced July 2, 2001
** See 1.4 and 1.5 chips for details
** Core voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in battery optimized mode
** Power <1 watt in battery optimized mode
** Used in full-size and then light mobile PCs
* 0.18 ΞΌm process technology Willamette (1.9 and 2.0 GHz)
** Introduced August 27, 2001
** See 1.4 and 1.5 chips for details
* Family 15 model 1
* Pentium 4 (2 GHz, 2.20 GHz)
** Introduced January 7, 2002
* Pentium 4 (2.4 GHz)
** Introduced April 2, 2002
* 0.13 ΞΌm process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6, 2.8 (OEM), 3.0 (OEM) GHz)
** Improved branch prediction and other microcodes tweaks
** 512 KB integrated L2 cache
** 55 million transistors
** 400 MHz system bus
* Family 15 model 2
* 0.13 ΞΌm process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)
** 533 MHz system bus. (3.06 includes Intel's Hyper-Threading technology)
* 0.13 ΞΌm process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)
** 800 MHz system bus (all versions include Hyper-Threading)
** 6500 to 10,000 MIPS
Itanium ''(chronological entry β new non-x86 architecture)''
* Introduced 2001
Xeon (32-bit NetBurst)
* Official designation now Xeon; i.e. not "Pentium 4 Xeon" * Xeon 1.4, 1.5, 1.7 GHz ** Introduced May 21, 2001 ** L2 cache was 256 KB Advanced Transfer cache (integrated) ** Processor packageOrganic Land Grid Array
Organic may refer to:
* Organic, of or relating to an organism, a living entity
* Organic, of or relating to an anatomical organ
Chemistry
* Organic matter, matter that has come from a once-living organism, is capable of decay or is the product o ...
603 (OLGA 603)
** System bus clock rate 400 MHz
** SSE2 SIMD Extensions
** Used in high-performance and mid-range dual processor enabled workstations
* Xeon 2.0 GHz and up to 3.6 GHz
** Introduced September 25, 2001
Itanium 2 ''(chronological entry β new non-x86 architecture)''
* Introduced July 2002
* ''See main entry''
Mobile Pentium 4-M
* 0.13 ΞΌm process technology * 55 million transistors * 512 KB L2 cache * BUS a 400 MHz * Supports up to 1 GB of DDR 266 MHz memory * Supports ACPI 2.0 andAPM APM, apm, or Apm may refer to:
Technology Computer technology
* Active policy management, a discipline within enterprise software
*Advanced Power Management, a legacy technology in personal computers
* Apple Partition Map, computer disk partit ...
1.2 System Power Management
* 1.3β1.2 V ( SpeedStep)
* Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W
* Sleep power 5 W (1.2 V)
* Deeper sleep power 2.9 W (1.0 V)
** 1.40 GHz β 23 April 2002
** 1.50 GHz β 23 April 2002
** 1.60 GHz β 4 March 2002
** 1.70 GHz β 4 March 2002
** 1.80 GHz β 23 April 2002
** 1.90 GHz β 24 June 2002
** 2.00 GHz β 24 June 2002
** 2.20 GHz β 16 September 2002
** 2.40 GHz β 14 January 2003
** 2.50 GHz β 16 April 2003
** 2.60 GHz β 11 June 2003
Pentium 4E
* Introduced February 2004 * Built on 0.09 ΞΌm ( 90 nm) process technology Prescott (2.4 A, 2.8, 2.8 A, 3.0, 3.2, 3.4, 3.6, 3.8 ) 1 MB L2 cache * 533 MHz system bus (2.4A and 2.8A only) * 800 MHz system bus (all other models) * 125 million transistors in 1 MB models * 169 million transistors in 2 MB models * Hyper-Threading support is only available on CPUs using the 800 MHz system bus. * The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater bandwidth * 7500 to 11,000 MIPS * LGA 775 versions are in the 5xx series (32-bit) and 5''x''1 series (with Intel 64) * The 6xx series has 2 MB L2 cache and Intel 64
Itanium 2
Itanium ( ) is a discontinued family of 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). Launched in June 2001, Intel marketed the processors for enterprise servers and high-performance computin ...
* Family 0x1F
* Released July 2002
* 900 MHz β 1.6 GHz
* McKinley 900 MHz 1.5 MB cache, Model 0x0
* McKinley 1 GHz, 3 MB cache, Model 0x0
* Deerfield 1 GHz, 1.5 MB cache, Model 0x1
* Madison 1.3 GHz, 3 MB cache, Model 0x1
* Madison 1.4 GHz, 4 MB cache, Model 0x1
* Madison 1.5 GHz, 6 MB cache, Model 0x1
* Madison 1.67 GHz, 9 MB cache, Model 0x1
* Hondo 1.4 GHz, 4 MB cache, dual-core MCM, Model 0x1
64-bit processors: Intel 64 β NetBurst microarchitecture
* Intel Extended Memory 64 Technology * Mostly compatible with AMD's AMD64 architecture * Introduced Spring 2004, with the Pentium 4F (D0 and later P4 steppings)Pentium 4F
* Prescott-2M built on 0.09 ΞΌm ( 90 nm) process technology * 2.8β3.8 GHz (model numbers 6''x''0) * Introduced February 20, 2005 * Same features as Prescott with the addition of: ** 2 MB cache ** Intel 64-bit ** Enhanced Intel SpeedStep Technology (EIST) * Cedar Mill built on 0.065 ΞΌm ( 65 nm) process technology * 3.0β3.6 GHz (model numbers 6''x''1) * Introduced January 16, 2006 * Die shrink of Prescott-2M * Same features as Prescott-2M * Family 15 Model 4Presler
Pentium D is a range of desktop 64-bit x86-64 processors based on the NetBurst microarchitecture, which is the dual-core variant of the Pentium 4 manufactured by Intel. Each CPU comprised two dies, each containing a single core, residing next to e ...
(Pentium D) β 65 nm process technology (2.8β3.6 GHz)
** Introduced January 16, 2006
** 2.8β3.6 GHz (model numbers 915β960)
** 376 million transistors
** 2Γ 2 MB (non-shared, 4 MB total) L2 cache
** Contains 2Γ Cedar Mill dies in one package
** Variants
*** Pentium D 945
Xeon (64-bit NetBurst)
* Nocona ** Introduced 2004 * Irwindale ** Introduced 2004 * Cranford ** Introduced April 2005 ** MP version of Nocona * Potomac ** Introduced April 2005 ** Cranford with 8 MB of L3 cache * Paxville DP (2.8 GHz) ** Introduced October 10, 2005 ** Dual-core version of Irwindale, with 4 MB of L2 cache (2 MB per core) ** 2.8 GHz ** 800 MT/s front-side bus * Paxville MP β 90 nm process (2.67 β 3.0 GHz) ** Introduced November 1, 2005 ** Dual-core Xeon 7000 series ** MP-capable version of Paxville DP ** 2 MB of L2 cache (1 MB per core) or 4 MB of L2 (2 MB per core) ** 667 MT/s FSB or 800 MT/s FSB * Dempsey β 65 nm process (2.67β3.73 GHz) ** Introduced May 23, 2006 ** Dual-core Xeon 5000 series ** MP version of Presler ** 667 MT/s or 1066 MT/s FSB ** 4 MB of L2 cache (2 MB per core) ** LGA 771 (Socket J). * Tulsa β 65 nm process (2.5β3.4 GHz) ** Introduced August 29, 2006 ** Dual-core Xeon 7100-series ** Improved version of Paxville MP ** 667 MT/s or 800 MT/s FSB64-bit processors: Intel 64 β Core microarchitecture
Xeon (64-bit Core microarchitecture)
* Woodcrest β 65 nm process technology ** Server and Workstation CPU (SMP support for dual CPU system) ** Introduced June 26, 2006 ** Intel VT-x, multiple OS support ** EIST (Enhanced Intel SpeedStep Technology) in 5140, 5148LV, 5150, 5160 ** Execute Disable Bit ** TXT, enhanced security hardware extensions ** SSSE3 SIMD instructions ** iAMT2 (Intel Active Management Technology), remotely manage computers ** Variants *** Xeon 5160, 3.00 GHz (4 MB L2, 1333 MHz FSB, 80 W) *** Xeon 5150, 2.66 GHz (4 MB L2, 1333 MHz FSB, 65 W) *** Xeon 5140, 2.33 GHz (4 MB L2, 1333 MHz FSB, 65 W) *** Xeon 5130, 2.00 GHz (4 MB L2, 1333 MHz FSB, 65 W) *** Xeon 5120, 1.86 GHz (4 MB L2, 1066 MHz FSB, 65 W) *** Xeon 5110, 1.60 GHz (4 MB L2, 1066 MHz FSB, 65 W) *** Xeon 5148LV, 2.33 GHz (4 MB L2, 1333 MHz FSB, 40 W) (low voltage edition) * Clovertown β 65 nm process technology ** Server and Workstation CPU (SMP support for dual CPU system) ** Introduced December 13, 2006 ** Quad-core ** Intel VT-x, multiple OS support ** EIST (Enhanced Intel SpeedStep Technology) in E5365, L5335 ** Execute Disable Bit ** TXT, enhanced security hardware extensions ** SSSE3 SIMD instructions ** iAMT2 (Intel Active Management Technology), remotely manage computers ** Variants *** Xeon X5355, 2.66 GHz (2Γ4 MB L2, 1333 MHz FSB, 105 W) *** Xeon E5345, 2.33 GHz (2Γ4 MB L2, 1333 MHz FSB, 80 W) *** Xeon E5335, 2.00 GHz (2Γ4 MB L2, 1333 MHz FSB, 80 W) *** Xeon E5320, 1.86 GHz (2Γ4 MB L2, 1066 MHz FSB, 65 W) *** Xeon E5310, 1.60 GHz (2Γ4 MB L2, 1066 MHz FSB, 65 W) *** Xeon L5320, 1.86 GHz (2Γ4 MB L2, 1066 MHz FSB, 50 W) (low voltage edition)45 nm
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007β2008 time frame.
Matsushita and Intel started mass ...
process technology
** Die shrink of Conroe
** Same features as Conroe with the addition of:
*** 50% more cache, 6 MB as opposed to 4 MB
*** Intel Trusted Execution Technology
*** SSE4
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
SIMD instructions
** 410 million transistors
** Variants
*** Core 2 Duo E8600, 3.33 GHz (6 MB L2, 1333 MHz FSB)
*** Core 2 Duo E8500, 3.16 GHz (6 MB L2, 1333 MHz FSB)
*** Core 2 Duo E8435, 3.07 GHz (6 MB L2, 1066 MHz FSB)
*** Core 2 Duo E8400, 3.00 GHz (6 MB L2, 1333 MHz FSB)
*** Core 2 Duo E8335, 2.93 GHz (6 MB L2, 1066 MHz FSB)
*** Core 2 Duo E8300, 2.83 GHz (6 MB L2, 1333 MHz FSB)
*** Core 2 Duo E8235, 2.80 GHz (6 MB L2, 1066 MHz FSB)
*** Core 2 Duo E8200, 2.66 GHz (6 MB L2, 1333 MHz FSB)
*** Core 2 Duo E8135, 2.66 GHz (6 MB L2, 1066 MHz FSB)
*** Core 2 Duo E8190, 2.66 GHz (6 MB L2, 1333 MHz FSB, no TXT, no VT)
* Wolfdale-3M (Intel Core 2) β 45 nm
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007β2008 time frame.
Matsushita and Intel started mass ...
process technology
** Intel Trusted Execution Technology
** Variants
*** Core 2 Duo E7600, 3.06 GHz (3 MB L2, 1066 MHz FSB)
*** Core 2 Duo E7500, 2.93 GHz (3 MB L2, 1066 MHz FSB)
*** Core 2 Duo E7400, 2.80 GHz (3 MB L2, 1066 MHz FSB)
*** Core 2 Duo E7300, 2.66 GHz (3 MB L2, 1066 MHz FSB)
*** Core 2 Duo E7200, 2.53 GHz (3 MB L2, 1066 MHz FSB)
* Yorkfield
Yorkfield is the code name for some Intel processors sold as Core 2 Quad and Xeon.
In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was Penryn microarchitecture, the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23, repla ...
, 45 nm
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007β2008 time frame.
Matsushita and Intel started mass ...
process technology
** Quad-core CPU
** Die shrink of Kentsfield
** Contains 2Γ Wolfdale dual-core dies in one package
** Same features as Wolfdale
** 820 million transistors
** Variants
*** Core 2 Extreme QX9770, 3.20 GHz (2Γ6 MB L2, 1600 MHz FSB)
*** Core 2 Extreme QX9650, 3.00 GHz (2Γ6 MB L2, 1333 MHz FSB)
*** Core 2 Quad Q9705, 3.16 GHz (2Γ3 MB L2, 1333 MHz FSB)
*** Core 2 Quad Q9700, 3.16 GHz (2Γ3 MB L2, 1333 MHz FSB)
*** Core 2 Quad Q9650, 3 GHz (2Γ6 MB L2, 1333 MHz FSB)
*** Core 2 Quad Q9550, 2.83 GHz (2Γ6 MB L2, 1333 MHz FSB, 95 W TDP)
*** Core 2 Quad Q9550s, 2.83 GHz (2Γ6 MB L2, 1333 MHz FSB, 65 W TDP)
*** Core 2 Quad Q9450, 2.66 GHz (2Γ6 MB L2, 1333 MHz FSB, 95 W TDP)
*** Core 2 Quad Q9505, 2.83 GHz (2Γ3 MB L2, 1333 MHz FSB, 95 W TDP)
*** Core 2 Quad Q9505s, 2.83 GHz (2Γ3 MB L2, 1333 MHz FSB, 65 W TDP)
*** Core 2 Quad Q9500, 2.83 GHz (2Γ3 MB L2, 1333 MHz FSB, 95 W TDP, no TXT)
*** Core 2 Quad Q9400, 2.66 GHz (2Γ3 MB L2, 1333 MHz FSB, 95 W TDP)
*** Core 2 Quad Q9400s, 2.66 GHz (2Γ3 MB L2, 1333 MHz FSB, 65 W TDP)
*** Core 2 Quad Q9300, 2.50 GHz (2Γ3 MB L2, 1333 MHz FSB, 95 W TDP)
*** Core 2 Quad Q8400, 2.66 GHz (2Γ2 MB L2, 1333 MHz FSB, 95 W TDP)
*** Core 2 Quad Q8400s, 2.66 GHz (2Γ2 MB L2, 1333 MHz FSB, 65 W TDP)
*** Core 2 Quad Q8300, 2.50 GHz (2Γ2 MB L2, 1333 MHz FSB, 95 W TDP)
*** Core 2 Quad Q8300s, 2.50 GHz (2Γ2 MB L2, 1333 MHz FSB, 65 W TDP)
*** Core 2 Quad Q8200, 2.33 GHz (2Γ2 MB L2, 1333 MHz FSB, 95 W TDP)
*** Core 2 Quad Q8200s, 2.33 GHz (2Γ2 MB L2, 1333 MHz FSB, 65 W TDP)
*** Core 2 Quad Q7600, 2.70 GHz (2Γ1 MB L2, 800 MHz FSB, no SSE4) (no Q7600 listehere
* Intel Core2 Quad Mobile processor family β
45 nm
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007β2008 time frame.
Matsushita and Intel started mass ...
process technology
** Quad-core CPU
** Variants
*** Core 2 Quad Q9100, 2.26 GHz (2Γ6 MB L2, 1066 MHz FSB, 45 W TDP)
*** Core 2 Quad Q9000, 2.00 GHz (2Γ3 MB L2, 1066 MHz FSB, 45 W TDP)
45 nm
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007β2008 time frame.
Matsushita and Intel started mass ...
process technology
** Intel Pentium E6800, 3.33 GHz (2 MB L2,1066 MHz FSB)
** Intel Pentium E6700, 3.20 GHz (2 MB L2,1066 MHz FSB)
** Intel Pentium E6600, 3.06 GHz (2 MB L2,1066 MHz FSB)
** Intel Pentium E6500, 2.93 GHz (2 MB L2,1066 MHz FSB)
** Intel Pentium E6300, 2.80 GHz (2 MB L2,1066 MHz FSB)
** Intel Pentium E5800, 3.20 GHz (2 MB L2, 800 MHz FSB)
** Intel Pentium E5700, 3.00 GHz (2 MB L2, 800 MHz FSB)
** Intel Pentium E5500, 2.80 GHz (2 MB L2, 800 MHz FSB)
** Intel Pentium E5400, 2.70 GHz (2 MB L2, 800 MHz FSB)
** Intel Pentium E5300, 2.60 GHz (2 MB L2, 800 MHz FSB)
** Intel Pentium E5200, 2.50 GHz (2 MB L2, 800 MHz FSB)
** Intel Pentium E2210, 2.20 GHz (1 MB L2, 800 MHz FSB)
Celeron (64-bit Core microarchitecture)
* Allendale (Celeron, 64-bit Core microarchitecture) β 65 nm process technology ** Variants *** Intel Celeron E1600, 2.40 GHz (512 KB L2, 800 MHz FSB) *** Intel Celeron E1500, 2.20 GHz (512 KB L2, 800 MHz FSB) *** Intel Celeron E1400, 2.00 GHz (512 KB L2, 800 MHz FSB) *** Intel Celeron E1300, 1.80 GHz (512 KB L2, 800 MHz FSB) (does it exist?) *** Intel Celeron E1200, 1.60 GHz (512 KB L2, 800 MHz FSB) * Wolfdale-3M (Celeron, 64-bit Core microarchitecture) β45 nm
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007β2008 time frame.
Matsushita and Intel started mass ...
process technology
** Variants
*** Intel Celeron E3500, 2.70 GHz (1 MB L2, 800 MHz FSB)
*** Intel Celeron E3400, 2.60 GHz (1 MB L2, 800 MHz FSB)
*** Intel Celeron E3300, 2.50 GHz (1 MB L2, 800 MHz FSB)
*** Intel Celeron E3200, 2.40 GHz (1 MB L2, 800 MHz FSB)
* Conroe-L (Celeron, 64-bit Core microarchitecture) β 65 nm process technology
** Variants
*** Intel Celeron 450, 2.20 GHz (512 KB L2, 800 MHz FSB)
*** Intel Celeron 440, 2.00 GHz (512 KB L2, 800 MHz FSB)
*** Intel Celeron 430, 1.80 GHz (512 KB L2, 800 MHz FSB)
*** Intel Celeron 420, 1.60 GHz (512 KB L2, 800 MHz FSB)
*** Intel Celeron 220, 1.20 GHz (512 KB L2, 533 MHz FSB)
* Conroe-CL (Celeron, 64-bit Core microarchitecture) β 65 nm process technology
** LGA 771 package
** Variants
*** Intel Celeron 445, 1.87 GHz (512 KB L2, 1066 MHz FSB)
Celeron M (64-bit Core microarchitecture)
* Merom-L 65 nm process technology ** 64 KB L1 cache ** 1 MB L2 cache (integrated) ** SSE3 SIMD instructions, 533 MHz/667 MHz front-side bus, execute-disable bit, 64-bit ** No SpeedStep technology, is not part of the ' Centrino' package ** Variants *** 520, 1.60 GHz *** 530, 1.73 GHz *** 540, 1.86 GHz *** 550, 2.00 GHz *** 560, 2.13 GHz *** 570, 2.26 GHz *** 667 MHz FSB **** 575, 2.00 GHz **** 585, 2.16 GHz64-bit processors: Intel 64 β Nehalem microarchitecture
Intel Pentium (Nehalem)
* Clarkdale (Pentium, Nehalem microarchitecture) β 32 nm process technology (manufacturing 7 Jan 2010) ** 2 physical cores/2 threads ** 32+32 KB L1 cache ** 256 KB L2 cache ** 3 MB L3 cache ** Introduced January 2010 ** Socket 1156 LGA ** 2-channel DDR3 ** Integrated HD GPU ** Variants *** G6950, 2.8 GHz (no Hyper-Threading) *** G6960, 2.933 GHz (no Hyper-Threading)Core i3 (1st generation)
* Clarkdale (Core i3 1st generation) β 32 nm process technology ** 2 physical cores/4 threads ** 32+32 KB L1 cache ** 256 KB L2 cache ** 4 MB L3 cache ** Introduced on January 7, 2010 ** Socket 1156 LGA ** 2-channel DDR3 ** Integrated HD GPU ** Variants *** 530, 2.93 GHz Hyper-Threading *** 540, 3.06 GHz Hyper-Threading *** 550, 3.2 GHz Hyper-Threading *** 560, 3.33 GHz Hyper-ThreadingCore i5 (1st generation)
* Lynnfield (Core i5 1st generation) β45 nm
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007β2008 time frame.
Matsushita and Intel started mass ...
process technology
** 4 physical cores/4 threads
** 32+32 KB L1 cache
** 256 KB L2 cache
** 8 MB L3 cache
** Introduced September 8, 2009
** Family 6 Model E (Ext. Model 1E)
** Socket 1156
LGA 1156 (land grid array 1156), also known as Socket H or H1, is an Intel desktop CPU socket. Its incompatible successor is LGA 1155.
The last processors supporting it ceased production in 2011.
LGA 1156, along with LGA 1366, were designed t ...
LGA
** 2-channel DDR3
** Variants
*** 750S, 2.40 GHz/3.20 GHz Turbo Boost
*** 750, 2.66 GHz/3.20 GHz Turbo Boost
*** 760, 2.80 GHz/3.33 GHz Turbo Boost
* Clarkdale (Core i5 1st generation) β 32 nm process technology
** 2 physical cores/4 threads
** 32+32 KB L1 cache
** 256 KB L2 cache
** 4 MB L3 cache
** Introduced January, 2010
** Socket 1156
LGA 1156 (land grid array 1156), also known as Socket H or H1, is an Intel desktop CPU socket. Its incompatible successor is LGA 1155.
The last processors supporting it ceased production in 2011.
LGA 1156, along with LGA 1366, were designed t ...
LGA
** 2-channel DDR3
** Integrated HD GPU
** AES Support
** Variants
*** 650/655K, 3.2 GHz Hyper-Threading Turbo Boost
*** 660/661, 3.33 GHz Hyper-Threading Turbo Boost
*** 670, 3.46 GHz Hyper-Threading Turbo Boost
*** 680, 3.60 GHz Hyper-Threading Turbo Boost
Core i7 (1st generation)
* Bloomfield (Core i7 1st generation) β45 nm
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007β2008 time frame.
Matsushita and Intel started mass ...
process technology
** 4 physical cores/8 threads
** 256 KB L2 cache
** 8 MB L3 cache
** Front-side bus replaced with QuickPath up to 6.4 GT/s
** Hyper-Threading is again included. This had previously been removed at the introduction of Core line
** 781 million transistors
** Intel Turbo Boost Technology
** TDP 130 W
** Introduced November 17, 2008
** Socket 1366 LGA
** 3-channel DDR3
** Variants
*** 975 (extreme edition), 3.33 GHz/3.60 GHz Turbo Boost
*** 965 (extreme edition), 3.20 GHz/3.46 GHz Turbo Boost
*** 960, 3.20 GHz/3.46 GHz Turbo Boost
*** 950, 3.06 GHz/3.33 GHz Turbo Boost
*** 940, 2.93 GHz/3.20 GHz Turbo Boost
*** 930, 2.80 GHz/3.06 GHz Turbo Boost
*** 920, 2.66 GHz/2.93 GHz Turbo Boost
* Lynnfield (Core i7 1st generation) β 45 nm
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007β2008 time frame.
Matsushita and Intel started mass ...
process technology
** 4 physical cores/8 threads
** 32+32 KB L1 cache
** 256 KB L2 cache
** 8 MB L3 cache
** No QuickPath, instead compatible with slower DMI interface
** Hyper-Threading is included
** Introduced September 8, 2009
** Socket 1156 LGA
** 2-channel DDR3
** Variants
*** 880, 3.06 GHz/3.73 GHz Turbo Boost (TDP 95 W)
*** 870/875K, 2.93 GHz/3.60 GHz Turbo Boost (TDP 95 W)
*** 870S, 2.67 GHz/3.60 GHz Turbo Boost (TDP 82 W)
*** 860, 2.80 GHz/3.46 GHz Turbo Boost (TDP 95 W)
*** 860S, 2.53 GHz/3.46 GHz Turbo Boost (TDP 82 W)
Westmere
* Gulftown, 32 nm process technology
** 6 physical cores
** 256 KB L2 cache
** 12 MB L3 cache
** Front-side bus replaced with QuickPath up to 6.4 GT/s
** Hyper-Threading is included
** Intel Turbo Boost Technology
** Socket 1366
LGA 1366 (land grid array 1366), also known as Socket B, is an Intel CPU socket. This socket supersedes Intel's LGA 775 (Socket T) in the high-end and performance desktop segments. It also replaces the server-oriented LGA 771 (Socket J) in the e ...
LGA
** TDP 130 W
** Introduced 16 March 2010
** Variants
*** 990X Extreme Edition, 3.46 GHz/3.73 GHz Turbo Boost
*** 980X Extreme Edition, 3.33 GHz/3.60 GHz Turbo Boost
*** 970, 3.20 GHz/3.46 GHz Turbo Boost
* Clarksfield β Intel Core i7 Mobile processor family β 45 nm
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007β2008 time frame.
Matsushita and Intel started mass ...
process technology
** 4 physical cores
** Hyper-Threading is included
** Intel Turbo Boost Technology
** Variants
*** 940XM Extreme Edition, 2.13 GHz/3.33 GHz Turbo Boost (8 MB L3, TDP 55 W)
*** 920XM Extreme Edition, 2.00 GHz/3.20 GHz Turbo Boost (8 MB L3, TDP 55 W)
*** 840QM, 1.86 GHz/3.20 GHz Turbo Boost (8 MB L3, TDP 45 W)
*** 820QM, 1.73 GHz/3.06 GHz Turbo Boost (8 MB L3, TDP 45 W)
*** 740QM, 1.73 GHz/2.93 GHz Turbo Boost (6 MB L3, TDP 45 W)
*** 720QM, 1.60 GHz/2.80 GHz Turbo Boost (6 MB L3, TDP 45 W)
Xeon (Nehalem microarchitecture)
* Gainestown β45 nm
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007β2008 time frame.
Matsushita and Intel started mass ...
process technology
** Same processor dies as Bloomfield
** 256 KB L2 cache
** 8 MB L3 cache, 4 MB may be disabled
** QuickPath up to 6.4 GT/s
** Hyper-Threading is included in some models
** 781 million transistors
** Introduced March 29, 2009
** Variants
*** W5590, X5570, X5560, X5550, E5540, E5530, L5530, E5520, L5520, L5518, 4 cores, 8 MB L3 cache, HT
*** E5506, L5506, E5504, 4 cores, 4 MB L3 cache, no HT
*** L5508, E5502, E5502, 2 cores, 4 MB L3 cache, no HT
64-bit processors: Intel 64 β Sandy Bridge / Ivy Bridge microarchitecture
Celeron (Sandy Bridge/Ivy Bridge microarchitecture)
* Sandy Bridge (Celeron-branded) β 32 nm process technology ** 2 physical cores/2 threads (500 series), 1 physical core/1 thread (model G440) or 1 physical core/2 threads (models G460 & G465) ** 2 MB L3 cache (500 series), 1 MB (model G440) or 1.5 MB (models G460 & G465) ** Introduced 3rd quarter, 2011 ** Socket 1155 LGA ** 2-channel DDR3-1066 ** 400 series has max TDP of 35 W ** 500-series variants ending in 'T' have a peak TDP of 35 W; others, 65 W ** Integrated GPU *** All variants have peak GPU turbo frequencies of 1 GHz *** Variants in the 400 series have GPUs running at a base frequency of 650 MHz *** Variants in the 500 series ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz *** All variants have 6 GPU execution units ** Variants *** G440, 1.6 GHz *** G460, 1.8 GHz *** G465, 1.9 GHz *** G470, 2.0 GHz *** G530T, 2.0 GHz *** G540T, 2.1 GHz *** G550T, 2.2 GHz *** G530, 2.4 GHz *** G540, 2.5 GHz *** G550, 2.6 GHz *** G555, 2.7 GHzPentium (Sandy Bridge/Ivy Bridge microarchitecture)
* Sandy Bridge (Pentium-branded) β 32 nm process technology ** 2 physical cores/2 threads ** 3 MB L3 cache ** 624 million transistors ** Introduced May, 2011 ** Socket 1155 LGA ** 2-channel DDR3-1333 (800 series) or DDR3-1066 (600 series) ** Variants ending in 'T' have a peak TDP of 35 W, others 65 W ** Integrated GPU ( HD 2000) *** All variants have peak GPU turbo frequencies of 1.1 GHz *** Variants ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz *** All variants have 6 GPU execution units ** Variants *** G620T, 2.2 GHz *** G630T, 2.3 GHz *** G640T, 2.4 GHz *** G645T, 2.5 GHz *** G860T, 2.6 GHz *** G620, 2.6 GHz *** G622, 2.6 GHz *** G630, 2.7 GHz *** G632, 2.7 GHz *** G640, 2.8 GHz *** G840, 2.8 GHz *** G645, 2.9 GHz *** G850, 2.9 GHz *** G860, 3.0 GHz *** G870, 3.1 GHz * Ivy Bridge (Pentium-branded) β 22 nm tri-gate transistor process technology ** 2 physical cores/2 threads ** 32+32 KB (per core) L1 cache ** 256 KB (per core) L2 cache ** 3 MB L3 cache ** Introduced September, 2012 ** Socket 1155 LGA ** 2-channel DDR3-1333 for G2000 series ** 2-channel DDR3-1600 for G2100 series ** All variants have GPU base frequencies of 650 MHz and peak GPU turbo frequencies of 1.05 GHz ** Variants ending in 'T' have a peak TDP of 35 W; others, TDP of 55 W ** Variants *** G2020T, 2.5 GHz *** G2030T, 2.6 GHz *** G2100T, 2.6 GHz *** G2120T, 2.7 GHz *** G2010, 2.8 GHz *** G2020, 2.9 GHz *** G2030, 3.0 GHz *** G2120, 3.1 GHz *** G2130, 3.2 GHz *** G2140, 3.3 GHzCore i3 (2nd and 3rd generation)
* Sandy Bridge (Core i3 2nd generation) β 32 nm process technology ** 2 physical cores/4 threads ** 32+32 KB (per core) L1 cache ** 256 KB (per core) L2 cache ** 3 MB L3 cache ** 624 million transistors ** Introduced January, 2011 ** Socket 1155 LGA ** 2-channel DDR3-1333 ** Variants ending in 'T' have a peak TDP of 35 W, others 65 W ** Integrated GPU *** All variants have peak GPU turbo frequencies of 1.1 GHz *** Variants ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz *** Variants ending in '5' have Intel HD Graphics 3000 (12 execution units); others have Intel HD Graphics 2000 (6 execution units) ** Variants *** i3-2100T, 2.5 GHz *** i3-2120T, 2.6 GHz *** i3-2100, 3.1 GHz *** i3-2102, 3.1 GHz *** i3-2105, 3.1 GHz *** i3-2120, 3.3 GHz *** i3-2125, 3.3 GHz *** i3-2130, 3.4 GHz * Ivy Bridge (Core i3 3rd generation) β 22 nm tri-gate transistor process technology ** 2 physical cores/4 threads ** 32+32 KB (per core) L1 cache ** 256 KB (per core) L2 cache ** 3 MB L3 cache ** Introduced September, 2012 ** Socket 1155 LGA ** 2-channel DDR3-1600 ** Variants ending in '5' have Intel HD Graphics 4000; others have Intel HD Graphics 2500 ** All variants have GPU base frequencies of 650 MHz and peak GPU turbo frequencies of 1.05 GHz ** TDP 55 W ** Variants *** i3-3220T, 2.8 GHz *** i3-3240T, 2.9 GHz *** i3-3210, 3.2 GHz *** i3-3220, 3.3 GHz *** i3-3225, 3.3 GHz *** i3-3240, 3.4 GHz *** i3-3250, 3.5 GHzCore i5 (2nd and 3rd generation)
* Sandy Bridge (Core i5 2nd generation) β 32 nm process technology ** 4 physical cores/4 threads (except for i5-2390T which has 2 physical cores/4 threads) ** 32+32 KB (per core) L1 cache ** 256 KB (per core) L2 cache ** 6 MB L3 cache (except for i5-2390T which has 3 MB) ** 995 million transistors ** Introduced January, 2011 ** Socket 1155 LGA ** 2-channel DDR3-1333 ** Variants ending in 'S' have a peak TDP of 65 W; others, 95 W except where noted ** Variants ending in 'K' have unlocked multipliers; others cannot be overclocked ** Integrated GPU *** i5-2500T has a peak GPU turbo frequency of 1.25 GHz, others 1.1 GHz *** Variants ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz *** Variants ending in '5' or 'K' have Intel HD Graphics 3000 (12 execution units), except i5-2550K which has no GPU; others have Intel HD Graphics 2000 (6 execution units) *** Variants ending in 'P' and the i5-2550K have no GPU ** Variants *** i5-2390T, 2.7 GHz/3.5 GHz Turbo Boost (35 W max. TDP) *** i5-2500T, 2.3 GHz/3.3 GHz Turbo Boost (45 W max. TDP) *** i5-2400S, 2.5 GHz/3.3 GHz Turbo Boost *** i5-2405S, 2.5 GHz/3.3 GHz Turbo Boost *** i5-2500S, 2.7 GHz/3.7 GHz Turbo Boost *** i5-2300, 2.8 GHz/3.1 GHz Turbo Boost *** i5-2310, 2.9 GHz/3.2 GHz Turbo Boost *** i5-2320, 3.0 GHz/3.3 GHz Turbo Boost *** i5-2380P, 3.1 GHz/3.4 GHz Turbo Boost *** i5-2400, 3.1 GHz/3.4 GHz Turbo Boost *** i5-2450P, 3.2 GHz/3.5 GHz Turbo Boost *** i5-2500, 3.3 GHz/3.7 GHz Turbo Boost *** i5-2500K, 3.3 GHz/3.7 GHz Turbo Boost *** i5-2550K, 3.4 GHz/3.8 GHz Turbo Boost * Ivy Bridge (Core i5 3rd generation) β 22 nm Tri-gate transistor process technology ** 4 physical cores/4 threads (except for i5-3470T which has 2 physical cores/4 threads) ** 32+32 KB (per core) L1 cache ** 256 KB (per core) L2 cache ** 6 MB L3 cache (except for i5-3470T which has 3 MB) ** Introduced April, 2012 ** Socket 1155 LGA ** 2-channel DDR3-1600 ** Variants ending in 'S' have a peak TDP of 65 W, Variants ending in 'T' have a peak TDP of 35 or 45 W (see variants); others, 77 W except where noted ** Variants ending in 'K' have unlocked multipliers; others cannot be overclocked ** Variants ending in 'P' have no integrated GPU; others have Intel HD Graphics 2500 or Intel HD Graphics 4000 (i5-3475S and i5-3570K only) ** Variants *** i5-3470T, 2.9 GHz/3.6 GHz max Turbo Boost (35 W TDP) *** i5-3570T, 2.3 GHz/3.3 GHz max Turbo Boost (45 W TDP) *** i5-3330S, 2.7 GHz/3.2 GHz max Turbo Boost *** i5-3450S, 2.8 GHz/3.5 GHz max Turbo Boost *** i5-3470S, 2.9 GHz/3.6 GHz max Turbo Boost *** i5-3475S, 2.9 GHz/3.6 GHz max Turbo Boost *** i5-3550S, 3.0 GHz/3.7 GHz max Turbo Boost *** i5-3570S, 3.1 GHz/3.8 GHz max Turbo Boost *** i5-3330, 3.0 GHz/3.2 GHz max Turbo Boost *** i5-3350P, 3.1 GHz/3.3 GHz max Turbo Boost (69 W TDP) *** i5-3450, 3.1 GHz/3.5 GHz max Turbo Boost *** i5-3470, 3.2 GHz/3.6 GHz max Turbo Boost *** i5-3550, 3.3 GHz/3.7 GHz max Turbo Boost *** i5-3570, 3.4 GHz/3.8 GHz max Turbo Boost *** i5-3570K, 3.4 GHz/3.8 GHz max Turbo BoostCore i7 (2nd and 3rd generation)
* Sandy Bridge (Core i7 2nd generation) β 32 nm process technology ** 4 physical cores/8 threads ** 32+32 KB (per core) L1 cache ** 256 KB (per core) L2 cache ** 8 MB L3 cache ** 995 million transistors ** Introduced January, 2011 ** Socket 1155 LGA ** 2-channel DDR3-1333 ** Variants ending in 'S' have a peak TDP of 65 W, others β 95 W ** Variants ending in 'K' have unlocked multipliers; others cannot be overclocked ** Integrated GPU *** All variants have base GPU frequencies of 850 MHz and peak GPU turbo frequencies of 1.35 GHz *** Variants ending in 'K' have Intel HD Graphics 3000 (12 execution units); others have Intel HD Graphics 2000 (6 execution units) ** Variants *** i7-2600S, 2.8 GHz/3.8 GHz Turbo Boost *** i7-2600, 3.4 GHz/3.8 GHz Turbo Boost *** i7-2600K, 3.4 GHz/3.8 GHz Turbo Boost *** i7-2700K, 3.5 GHz/3.9 GHz Turbo Boost * Sandy Bridge-E (Core i7 3rd generation X-Series) β 32 nm process technology ** Up to 6 physical cores/12 threads depending on model number ** 32+32 KB (per core) L1 cache ** 256 KB (per core) L2 cache ** Up to 20 MB L3 cache depending on model number ** 2.27 billion transistors ** Introduced November, 2011 ** Socket 2011 LGA ** 4-channel DDR3-1600 ** All variants have a peak TDP of 130 W ** No integrated GPU ** Variants (all marketed under "Intel Core X-series processors") *** i7-3820, 3.6 GHz/3.8 GHz Turbo Boost, 4 cores, 10 MB L3 cache *** i7-3930K, 3.2 GHz/3.8 GHz Turbo Boost, 6 cores, 12 MB L3 cache *** i7-3960X, 3.3 GHz/3.9 GHz Turbo Boost, 6 cores, 15 MB L3 cache *** i7-3970X, 3.5 GHz/4.0 GHz Turbo Boost, 6 cores, 15 MB L3 cache * Ivy Bridge (Core i7 3rd generation) β 22 nm Tri-gate transistor process technology ** 4 physical cores/8 threads ** 32+32 KB (per core) L1 cache ** 256 KB (per core) L2 cache ** 8 MB L3 cache ** Introduced April, 2012 ** Socket 1155 LGA ** 2-channel DDR3-1600 ** Variants ending in 'S' have a peak TDP of 65 W, variants ending in 'T' have a peak TDP of 45 W, others β 77 W ** Variants ending in 'K' have unlocked multipliers; others cannot be overclocked ** Integrated GPU Intel HD Graphics 4000 ** Variants *** i7-3770T β 2.5 GHz/3.7 GHz Turbo Boost *** i7-3770S β 3.1 GHz/3.9 GHz Turbo Boost *** i7-3770 β 3.4 GHz/3.9 GHz Turbo Boost *** i7-3770K β 3.5 GHz/3.9 GHz Turbo Boost64-bit processors: Intel 64 β Haswell microarchitecture
Core i3 (4th generation)
* Haswell (Core i3 4th generation) β22nm
The 22 nm node is the process step following 32 nm in CMOS MOSFET semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22 nm. ...
process technology
64-bit processors: Intel 64 β Broadwell microarchitecture
Core i3 (5th generation)
* Broadwell (Core i3 5th generation) β 14nm process technologyCore i5 (5th generation)
* Broadwell (Core i5 5th generation) β 14nm process technology ** 4 physical cores/4 threads ** 4 MB L3 cache ** Introduced Q2'15 ** Socket 1150 LGA ** 2-channel DDR3L-1333/1600 ** Integrated GPU ** Variants *** i5-5575R β 2.80 GHz/3.30 GHz Turbo Boost *** i5-5675C β 3.10 GHz/3.60 GHz Turbo Boost *** i5-5675R β 3.10 GHz/3.60 GHz Turbo BoostCore i7 (5th generation, Including Core-X Series)
* Broadwell (Core i7 5th generation) β 14nm process technology ** 4 physical cores/8 threads ** 6 MB L3 cache ** Introduced Q2'15 ** Socket 1150 LGA ** 2-channel DDR3L-1333/1600 ** Integrated GPU ** Variants *** i7-5775C β 3.30 GHz/3.70 GHz Turbo Boost *** i7-5775R β 3.30 GHz/3.80 GHz Turbo Boost *Broadwell-E
Broadwell is the fifth generation of the Intel Core Processor. It is Intel's codename for the 14 nanometer die shrink of its Haswell microarchitecture. It is a "tick" in Intel's tickβtock principle as the next step in semiconductor fabri ...
β 14nm process technology
** 6β10 physical cores/12β20 threads
** 15β25 MB L3 cache
** Introduced Q2'16
** Socket 2011-v3 LGA
** 4-channel DDR4-2133/2400
** No Integrated GPU
** Variants (all marketed under "Intel Core X-series processors")
*** i7-6800K β 3.40 GHz/3.60 GHz Turbo Boost/3.80 GHz Turbo Boost Max Technology 3.0 Frequency 15 MB L3 cache
*** i7-6850K β 3.60 GHz/3.80 GHz Turbo Boost/4.00 GHz Turbo Boost Max Technology 3.0 Frequency 15 MB L3 cache
*** i7-6900K β 3.20 GHz/3.70 GHz Turbo Boost/4.00 GHz Turbo Boost Max Technology 3.0 Frequency 20 MB L3 cache
*** i7-6950X β 3.00 GHz/3.50 GHz Turbo Boost/4.00 GHz Turbo Boost Max Technology 3.0 Frequency 25 MB L3 cache
Other Broadwell CPUs
Not listed (yet) are several Broadwell-based CPU models: * Server and workstation CPUs ** single-CPU: Pentium D15nn, Xeon D-15nn, Xeon E3-12nn v4, Xeon E5-16nn v4 ** dual-CPU: Xeon E5-26nn v4 ** quad-CPU: Xeon E5-46nn v4, Xeon E7-48nn v4 ** octo-CPU: Xeon E7-88nn v4 * Embedded CPUs ** Core i7-57nnEQ, Core i7-58nnEQ * Mobile CPUs ** Celeron 32nnU, Celeron 37nnU ** Pentium 38nnU ** Core M-5Ynn ** Core i3-50nnU ** Core i5-5nnnU ** Core i7-55nnU, Core i7-56nnU, Core i7-57nnHQ, Core i7-59nnHQ Note: this list does not say that all processors that match these patterns are Broadwell-based or fit into this scheme. The model numbers may have suffixes that are not shown here.64-bit processors: Intel 64 β
Skylake Skylake or Sky Lake may refer to:
* Skylake (microarchitecture), the codename for a processor microarchitecture developed by Intel as the successor to Broadwell
* Skylake (Mysia), a town of ancient Mysia, now in Turkey
* Sky Lake, Florida
Sky La ...
microarchitecture
Core i3 (6th generation)
*Skylake Skylake or Sky Lake may refer to:
* Skylake (microarchitecture), the codename for a processor microarchitecture developed by Intel as the successor to Broadwell
* Skylake (Mysia), a town of ancient Mysia, now in Turkey
* Sky Lake, Florida
Sky La ...
(Core i3 6th generation) β 14 nm
The 14 nm process refers to the MOSFET technology node that is the successor to the 22nm (or 20nm) node. The 14nm was so named by the International Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following 22nm was expe ...
process technology
** 2 physical cores/4 threads
** 3β4 MB L3 cache
** Introduced Q3'15
** Socket 1151 LGA
** 2-channel DDR3L-1333/1600, DDR4-1866/2133
** Integrated GPU Intel HD Graphics 530 (only i3-6098P have HD Graphics 510)
** Variants
*** i3-6098P β 3.60 GHz
*** i3-6100T β 3.20 GHz
*** i3-6100 β 3.70 GHz
*** i3-6300T β 3.30 GHz
*** i3-6300 β 3.80 GHz
*** i3-6320 β 3.90 GHz
Core i5 (6th generation)
*Skylake Skylake or Sky Lake may refer to:
* Skylake (microarchitecture), the codename for a processor microarchitecture developed by Intel as the successor to Broadwell
* Skylake (Mysia), a town of ancient Mysia, now in Turkey
* Sky Lake, Florida
Sky La ...
(Core i5 6th generation) β 14nm process technology
** 4 physical cores/4 threads
** 6 MB L3 cache
** Introduced Q3'15
** Socket 1151 LGA
** 2-channel DDR3L-1333/1600, DDR4-1866/2133
** Integrated GPU Intel HD Graphics 530
** Variants
*** i5-6300HQ β 2.30/3.20 GHz Turbo Boost
***i5-6400T β 2.20 GHz/2.80 GHz Turbo Boost
*** i5-6400 β 2.70 GHz/3.30 GHz Turbo Boost
*** i5-6440hq
*** i5-6500T β 2.50 GHz/3.10 GHz Turbo Boost
*** i5-6500 β 3.20 GHz/3.60 GHz Turbo Boost
*** i5-6600T β 2.70 GHz/3.50 GHz Turbo Boost
*** i5-6600 β 3.30 GHz/3.90 GHz Turbo Boost
*** i5-6600K β 3.50 GHz/3.90 GHz Turbo Boost
Core i7 (6th generation)
*Skylake Skylake or Sky Lake may refer to:
* Skylake (microarchitecture), the codename for a processor microarchitecture developed by Intel as the successor to Broadwell
* Skylake (Mysia), a town of ancient Mysia, now in Turkey
* Sky Lake, Florida
Sky La ...
(Core i7 6th generation) β 14nm process technology
** 4 physical cores/8 threads
** 8 MB L3 cache
** Introduced Q3'15
** Socket 1151 LGA
** 2-channel DDR3L-1333/1600, DDR4-1866/2133
** Integrated GPU Intel HD Graphics 530
** Variants
*** i7-6700T β 2.80 GHz/3.60 GHz Turbo Boost
*** i7-6700 β 3.40 GHz/4.00 GHz Turbo Boost
*** i7-6700K β 4.00 GHz/4.20 GHz Turbo Boost
Other Skylake processors
Many Skylake-based processors are not yet listed in this section: mobile i3/i5/i7 processors (U, H, and M suffixes), embedded i3/i5/i7 processors (E suffix), certain i7-67nn/i7-68nn/i7-69nn. Skylake-based "Core X-series" processors (certain i7-78nn and i9-79nn models) can be found under current models.64-bit processors: Intel 64 (7th generation) β Kaby Lake microarchitecture
64-bit processors: Intel 64 (8th and 9th generation) β Coffee Lake microarchitecture
64-bit processors: Intel 64 β Cannon Lake microarchitecture
64-bit processors: Intel 64 (10th generation) β Ice Lake microarchitecture
64-bit processors: Intel 64 (10th generation) β Comet Lake microarchitecture
64-bit processors: Intel 64 (11th generation) β Tiger Lake microarchitecture
64-bit processors: Intel 64 (12th generation) β Alder Lake microarchitecture
64-bit processors: Intel 64 (13th generation) β Raptor Lake microarchitecture
Intel 805xx product codes
Intel discontinued the use of part numbers such as 80486 in the marketing of mainstream x86-architecture processors with the introduction of the Pentium brand in 1993. However, numerical codes, in the 805xx range, continued to be assigned to these processors for internal and part numbering uses. The following is a list of such product codes in numerical order:Intel 806xx product codes
Intel 807xx Product Codes
See also
* List of AMD processors * List of PowerPC processors * List of Freescale products *List of Intel Atom processors
The Intel Atom is Intel's line of low-power, low-cost and low-performance x86 and x86-64 microprocessors. Atom, with codenames of ''Silverthorne'' and '' Diamondville'', was first announced on March 2, 2008.
For Nettop and Netbook Atom ...
* List of Intel Xeon processors
* List of Intel Itanium processors
* List of Intel Celeron processors
* List of Intel Pentium processors
** List of Intel Pentium Pro processors
** List of Intel Pentium II processors
** List of Intel Pentium III processors
** List of Intel Pentium 4 processors
** List of Intel Pentium D processors
** List of Intel Pentium M processors
This is a list of Intel Pentium M processors. They are all single-core 32-bit CPUs codenamed ''Banias'' and ''Dothan'', and targeted at the consumer market of mobile computers.
Mobile processors Pentium M "Banias" (130 nm)
* All models suppo ...
* List of Intel Core processors
* List of Intel Core 2 processors
* List of Intel Core M processors
Intel Core M is a family of ultra low-voltage microprocessors belonging to the Intel Core series and designed specifically for ultra-thin notebooks, 2-in-1 detachables, and other mobile devices. The thermal design power (TDP) of all Core M micr ...
* List of Intel Core i3 processors
* List of Intel Core i5 processors
* List of Intel Core i7 processors
* List of Intel Core i9 processors
* List of Intel CPU microarchitectures
* List of Intel graphics processing units
* List of quantum processors
* Apple silicon
References
External links
Intel Museum: History of the Microprocessor
Stealey A100 and A110
Intel Product Specifications
{{Intel Intel microprocessors Intel