This is a list of microprocessors designed by AMD, under the

AMD Accelerated Processing Unit AMD Accelerated Processing Unit (APU), formerly known as Fusion, is a series of 64-bit microprocessors from Advanced Micro Devices (AMD), combining a general-purpose AMD64 central processing unit (CPU) and integrated graphics processing un ...

product series.

Features overview

Graphics API overview

Desktop APUs

Lynx: "Llano" (2011)

* Socket FM1 * CPU: K10 (or ''Husky'' or K10.5) with no L3 cache cores with an upgraded architecture known as ''Stars'' ** L1 Cache: 64 KB Data per core and 64 KB Instructions per core * ''

MMX MMX may refer to: * 2010, in Roman numerals Science and technology * MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel * MMX Mineração, a Brazilian mining company * Martian Moons eXploration, a Japane ...

, Enhanced 3DNow!, SSE,

SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier SSE i ...

SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...

, SSE4a, ABM,

NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...

AMD64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...

, Cool'n'Quiet'', ''

AMD-V x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...

'' * GPU: TeraScale 2 (Evergreen); all A and E series models feature ''Redwood''-class integrated graphics on die (''BeaverCreek'' for the dual-core variants and ''WinterPark'' for the quad-core variants). Sempron and Athlon models exclude integrated graphics. * List of embedded GPU's * Support for up to four

DIMM A DIMM () (Dual In-line Memory Module), commonly called a RAM stick, comprises a series of dynamic random-access memory integrated circuits. These memory modules are mounted on a printed circuit board and designed for use in personal computers ...

s of up to

DDR3 Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface, and has been in use since 2007. It is the higher-speed ...

-1866 memory * Fabrication 32 nm on

GlobalFoundries GlobalFoundries Inc. (GF or GloFo) is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, th ...

SOI ''Soi'' ( th, ซอย ) is the term used in Thailand for a side-street branching off a major street (''thanon'', th, ถนน). An alley is called a ''trok'' ( th, ตรอก). Overview Sois are usually numbered, and are referred to by th ...

process;

Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...

size: , with 1.178 billion transistors * 5 GT/s

UMI Umi or UMI may refer to: Geography * Umi, Iran, a village in Razavi Khorasan Province, Iran * Umi, Fukuoka, a town in Japan People * Umi-a-Liloa, king of the island of Hawaii *Umi Dachlan, Indonesian female artist * Umi Garrett, American female pi ...

* Integrated

PCIe 2.0 PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common m ...

controller * Select models support Turbo Core technology for faster CPU operation when the thermal specification permits * Select models support Hybrid Graphics technology to assist a discrete Radeon HD 6450, 6570, or 6670 discrete graphics card. This is similar to the Hybrid CrossFireX technology available in the AMD 700 and 800 chipset series

Virgo: "Trinity" (2012)

* Fabrication 32 nm on GlobalFoundries SOI process * Socket FM2 * CPU: Piledriver ** L1 Cache: 16 KB Data per core and 64 KB Instructions per module * GPU TeraScale 3 (VLIW4) * Die Size: , 1.303 Billion transistors * Support for up to four DIMMs of up to DDR3-1866 memory * 5 GT/s UMI * GPU (based on VLIW4 architecture) instruction support: ''

DirectX Microsoft DirectX is a collection of application programming interfaces (APIs) for handling tasks related to multimedia, especially game programming and video, on Microsoft platforms. Originally, the names of these APIs all began with "Direct", ...

11,

Opengl OpenGL (Open Graphics Library) is a cross-language, cross-platform application programming interface (API) for rendering 2D and 3D vector graphics. The API is typically used to interact with a graphics processing unit (GPU), to achieve hardwa ...

4.2,

DirectCompute Microsoft DirectCompute is an application programming interface (API) that supports running compute kernels on general-purpose computing on graphics processing units on Microsoft's Windows Vista, Windows 7 and later versions. DirectCompute is part ...

Pixel Shader In computer graphics, a shader is a computer program that calculates the appropriate levels of light, darkness, and color during the rendering of a 3D scene - a process known as ''shading''. Shaders have evolved to perform a variety of spec ...

5.0,

Blu-ray 3D The Blu-ray Disc (BD), often known simply as Blu-ray, is a digital optical disc data storage format. It was invented and developed in 2005 and released on June 20, 2006 worldwide. It is designed to supersede the DVD format, and capable of sto ...

OpenCL OpenCL (Open Computing Language) is a framework for writing programs that execute across heterogeneous platforms consisting of central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), field-progra ...

1.2,

AMD Stream AMD FireStream was AMD's brand name for their Radeon-based product line targeting stream processing and/or GPGPU in supercomputers. Originally developed by ATI Technologies around the Radeon X1900 XTX in 2006, the product line was previously b ...

UVD Unified Video Decoder (UVD, previously called Universal Video Decoder) is the name given to AMD's dedicated video decoding ASIC. There are multiple versions implementing a multitude of video codecs, such as H.264 and VC-1. UVD was introduced wit ...

3'' * Integrated

controller, and Turbo Core technology for faster CPU/GPU operation when the thermal specification permits * MMX, SSE,

SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitecture ...

, SSE4a,

SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; mor ...

SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core (microarchitecture), Core microarchitecture and AMD K10, AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vag ...

, AES,

CLMUL Carry-less Multiplication (CLMUL) is an extension to the x86 instruction set used by microprocessors from Intel and AMD which was proposed by Intel in March 2008 and made available in the Intel Westmere processors announced in early 2010. Mathema ...

AVX AVX may refer to: Technology * Advanced Vector Extensions, an instruction set extension in the x86 microprocessor architecture ** AVX2, an expansion of the AVX instruction set ** AVX-512, 512-bit extensions to the 256-bit AVX * AVX Corporation, a m ...

, XOP,

FMA3 The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations."FMA3 and FMA4 are not instruction sets, they are i ...

, FMA4,

F16C The F16C (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats. History T ...

, ABM,

BMI1 Polycomb complex protein BMI-1 also known as polycomb group RING finger protein 4 (PCGF4) or RING finger protein 51 (RNF51) is a protein that in humans is encoded by the ''BMI1'' gene (B cell-specific Moloney murine leukemia virus integration ...

, TBM * Sempron and Athlon models exclude integrated graphics * Select models support Hybrid Graphics technology to assist a Radeon HD 7350, 7450, 7470, 7550, 7570, 7670 discrete graphics card. However, it has been found that this does not always improve 3D accelerated graphics performance.

"Richland" (2013)

* Fabrication 32 nm on GlobalFoundries SOI process * Socket FM2 * Two or four CPU cores based on the Piledriver microarchitecture ** Die Size: , 1.303 Billion transistors ** L1 Cache: 16 KB Data per core and 64 KB Instructions per module ** MMX, SSE,

, SSSE3, SSE4a, SSE4.1, SSE4.2,

, AES,

, AVX1.1, XOP,

, FMA4,

, ABM,

, TBM, Turbo Core 3.0,

PowerNow! __NOTOC__ AMD PowerNow! is AMD's dynamic frequency scaling and power saving technology for laptop processors. The CPU's clock speed and VCore are automatically decreased when the computer is under low load or idle, to save battery power, reduce ...

* GPU ** TeraScale 3 architecture ** HD Media Accelerator,

AMD Hybrid Graphics AMD Hybrid Graphics technology, is a collective brand from AMD for its Radeon line of discrete and integrated GPU, promoting higher performance and productivity while saving energy consumption in GPUs. The technology previously applied to selec ...

"Kabini" (2013, SoC)

* Fabrication 28 nm by

Socket AM1 Socket FS1b (rebranded as Socket AM1 ) is a socket designed by AMD, launched in April 2014 for desktop SoCs in the value segment. Socket AM1 is intended for a class of CPUs that contain both an integrated GPU and a chipset, essentially forming a ...

, aka Socket FS1b (AM1 platform) * 2 to 4 CPU Cores (

Jaguar (microarchitecture) The AMD Jaguar Family 16h is a low-power microarchitecture designed by AMD. It is used in APUs succeeding the Bobcat Family microarchitecture in 2013 and being succeeded by AMD's Puma architecture in 2014. It is two-way superscalar and capable ...

) * L1 Cache: 32 KB Data per core and 32 KB Instructions per core *

, SSE,

, SSE4a,

, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM,

support * SoC with integrated memory, PCIe, 2× USB 3.0, 6× USB 2.0, Gigabit Ethernet, and 2× SATA III (6 Gb/s) controllers * GPU based on

Graphics Core Next Graphics Core Next (GCN) is the codename for a series of microarchitectures and an instruction set architecture that were developed by AMD for its GPUs as the successor to its TeraScale microarchitecture. The first product featuring GCN was lau ...

(GCN)

"Kaveri" (2014) & "Godavari" (2015)

* Fabrication 28 nm by

. *

Socket FM2+ Socket FM2+ (FM2b, FM2r2) is a zero insertion force CPU socket designed by AMD for their desktop "Kaveri" APUs ( Steamroller-based) and Godavari APUs ( Steamroller-based) to connect to the motherboard. The FM2+ has a slightly different pin config ...

, support for

PCIe 3.0 PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common mot ...

. * Two or four CPU cores based on the

Steamroller A steamroller (or steam roller) is a form of road roller – a type of heavy construction machinery used for leveling surfaces, such as roads or airfields – that is powered by a steam engine. The leveling/flattening action is achieved through ...

microarchitecture. **Kaveri refresh models have codename Godavari. * Die Size: , 2.41 Billion transistors. * L1 Cache: 16 KB Data per core and 96 KB Instructions per module. *

, SSE,

, SSE4a,

, AES,

, AVX 1.1, XOP,

, FMA4,

, ABM,

, TBM,

Turbo Core AMD Turbo Core a.k.a. AMD Core Performance Boost (CPB) is a dynamic frequency scaling technology implemented by AMD that allows the processor to dynamically adjust and control the processor operating frequency in certain versions of its processors ...

* Three to eight Compute Units (CUs) based on GCN 2nd gen microarchitecture; 1 Compute Unit (CU) consists of 64 Unified Shader Processors : 4 Texture Mapping Units (TMUs) : 1

Render Output Unit In computer graphics, the render output unit (ROP) or raster operations pipeline is a hardware component in modern graphics processing units (GPUs) and one of the final steps in the rendering process of modern graphics cards. The pixel pipelines ...

(ROPs). *

Heterogeneous System Architecture Heterogeneous System Architecture (HSA) is a cross-vendor set of specifications that allow for the integration of central processing units and graphics processors on the same bus, with shared memory and tasks. The HSA is being developed by the HSA ...

-enabled

zero-copy "Zero-copy" describes computer operations in which the CPU does not perform the task of copying data from one memory area to another or in which unnecessary data copies are avoided. This is frequently used to save CPU cycles and memory bandwid ...

through pointer passing. * SIP blocks:

Unified Video Decoder Unified Video Decoder (UVD, previously called Universal Video Decoder) is the name given to AMD's dedicated video decoding ASIC. There are multiple versions implementing a multitude of video codecs, such as H.264 and VC-1. UVD was introduced with ...

Video Coding Engine Video Code Engine (VCE, was earlier referred to as Video Coding Engine, Video Compression Engine or Video Codec Engine in official AMD documentation) is AMD's video encoding application-specific integrated circuit implementing the video codec H. ...

, TrueAudio. * Dual-channel (2× 64 Bit)

memory controller. * Integrated custom

ARM Cortex-A5 The ARM Cortex-A5 is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture announced in 2009. Overview The Cortex-A5 is intended to replace the ARM9 and ARM11 cores for use in low-end devices. The Cortex-A5 offe ...

co-processor with

TrustZone ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer (RISC) instruction set architectures for computer processors, configure ...

Security Extensions in select APU models, except the Performance APU models. * Select models support Hybrid Graphics technology by using a Radeon R7 240 or R7 250 discrete graphics card. *

Display controller A video display controller or VDC (also called a display engine or display interface) is an integrated circuit which is the main component in a video-signal generator, a device responsible for the production of a TV video signal in a computing ...

AMD Eyefinity AMD Eyefinity is a brand name for AMD video card products that support multi-monitor setups by integrating multiple (up to six) display controllers on one GPU. AMD Eyefinity was introduced with the Radeon HD 5000 Series "Evergreen" in September 2 ...

2, 4K Ultra HD support, DisplayPort 1.2 Support.

"Carrizo" (2016)

* Fabrication: 28 nm by

* Socket FM2+ or AM4, support for

* Two or four CPU cores based on the

Excavator Excavators are heavy construction equipment consisting of a boom, dipper (or stick), bucket and cab on a rotating platform known as the "house". The house sits atop an undercarriage with tracks or wheels. They are a natural progression fro ...

microarchitecture * Die size: , 3.1 billion transistors * L1 cache: 32 KB data per core and 96 KB instructions per module * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

AVX2 Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge ...

, XOP,

, FMA4,

, ABM,

BMI2 Bit manipulation instructions sets (BMI sets) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is to improve the speed of bit manipulation. All the instruction ...

, TBM,

RDRAND RDRAND (for "read random"; known as Intel Secure Key Technology, previously known as Bull Mountain) is an instruction for returning random numbers from an Intel on-chip hardware random number generator which has been seeded by an on-chip entropy s ...

* Single- or dual-channel DDR3 or

DDR4 Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth ("double data rate") interface. Released to the market in 2014, it is a variant of dynamic rando ...

memory controller * Third generation GCN-based GPU ( Radeon M300) * Integrated custom

coprocessor with

security extensions

"Bristol Ridge" (2016)

* Fabrication 28 nm by

Socket AM4 Socket AM4 is a PGA microprocessor socket used by AMD's central processing units (CPUs) built on the Zen (including Zen+, Zen 2 and Zen 3) and Excavator microarchitectures. ''AM4'' was launched in September 2016 and was designed to replace the ...

, support for

* Two or four " Excavator+" CPU cores * L1 Cache: 32 KB Data per core and 96 KB Instructions per module * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, XOP,

, FMA4,

, ABM,

, TBM,

* Dual-channel

memory controller *

PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...

3.0 x8 (No Bifurcation support, requires a PCI-e switch for any configuration other than x8) *

3.0 x4 as link to optional external chipset * 4x

USB 3.1 USB 3.0, released in November 2008, is the third major version of the Universal Serial Bus (USB) standard for interfacing computers and electronic devices. Among other improvements, USB 3.0 adds the new transfer rate referred to as '' ...

Gen 1 * Storage: 2x

SATA SATA (Serial AT Attachment) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) standard to ...

and 2x

NVMe NVM Express (NVMe) or Non-Volatile Memory Host Controller Interface Specification (NVMHCIS) is an open, logical-device interface specification for accessing a computer's non-volatile storage media usually attached via PCI Express (PCIe) bus. The ...

or 2x PCI Express * Third Generation GCN based GPU with hybrid

VP9 VP9 is an open and royalty-free video coding format developed by Google. VP9 is the successor to VP8 and competes mainly with MPEG's High Efficiency Video Coding (HEVC/H.265). At first, VP9 was mainly used on Google's video platform YouTube. ...

decoding

"Raven Ridge" (2018)

* Fabrication 14 nm by

Transistor upright=1.4, gate (G), body (B), source (S) and drain (D) terminals. The gate is separated from the body by an insulating layer (pink). A transistor is a semiconductor device used to Electronic amplifier, amplify or electronic switch, switch e ...

s: 4.94 billion *

size: 210 mm² *

Zen Zen ( zh, t=禪, p=Chán; ja, text= 禅, translit=zen; ko, text=선, translit=Seon; vi, text=Thiền) is a school of Mahayana Buddhism that originated in China during the Tang dynasty, known as the Chan School (''Chánzong'' 禪宗), and ...

CPU cores * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, ABM,

* Dual-channel

memory controller * Fifth generation GCN based GPU *

Video Core Next Video Core Next is AMD's brand for its dedicated video encoding and decoding hardware core. It is a family of hardware accelerator designs for encoding and decoding video, and is built into AMD's GPUs and APUs since AMD Raven Ridge, released Janu ...

(VCN) 1.0

"Picasso" (2019)

* Fabrication 12 nm by

s: 4.94 billion *

size: 210 mm² *

Zen+ Zen+ is the codename for a computer processor microarchitecture by AMD. It is the successor to the first gen Zen microarchitecture, first released in April 2018, powering the second generation of Ryzen processors, known as Ryzen 2000 for mainstre ...

CPU cores * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, ABM,

* Dual-channel

memory controller * Fifth generation GCN based GPU *

(VCN) 1.0

"Renoir" (2020)

* Fabrication 7 nm by

TSMC Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational corporation, multinational semiconductor contract manufacturing and design company. It is the world's most valuable semicon ...

* Up to eight

Zen 2 Zen 2 is a computer processor microarchitecture by AMD. It is the successor of AMD's Zen and Zen+ microarchitectures, and is fabricated on the 7 nanometer MOSFET node from TSMC. The microarchitecture powers the third generation of Ryzen proces ...

CPU cores * Dual-channel

memory controller

"Cezanne" (2021)

* Fabrication 7 nm by

* Up to eight

Zen 3 Zen 3 is the codename for a CPU microarchitecture by AMD, released on November 5, 2020. It is the successor to Zen 2 and uses TSMC's 7 nm process, 7 nm process for the chiplets and GlobalFoundries's 14 nm process, 14 nm process for the I/O die on ...

CPU cores * Dual-channel

memory controller

"Raphael" (2022)

* Fabrication 5 nm by

Socket AM5 Socket AM5 (LGA 1718) is a zero insertion force flip-chip land grid array (LGA) CPU socket designed by Advanced Micro Devices, that is used for AMD Ryzen microprocessors starting with the Zen 4 microarchitecture. AM5 replaces the Socket AM4 and ...

* Up to sixteen

Zen 4 Zen 4 is the codename for a CPU microarchitecture by AMD, released on September 27, 2022. It is the successor to Zen 3 and uses TSMC's N5 process for CCDs. Zen 4 powers Ryzen 7000 mainstream desktop processors (codenamed "Raphael") and will b ...

CPU cores * Dual-channel

DDR5 Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) ...

memory controller

Server APUs

Opteron X2100-series "Kyoto" (2013)

* Fabrication 28 nm * Socket FT3 (BGA) * 4 CPU Cores (

) * L1 Cache: 32 KB Data per core and 32 KB Instructions per core *

, SSE,

, SSE4a,

, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM,

support * Turbo Dock Technology, C6 and CC6 low power states * GPU based on GCN (Graphics Core Next) architecture

Opteron X3000-series "Toronto" (2017)

* Fabrication 28 nm * Socket FP4 * Two or Four CPU cores based on the

microarchitecture * L1 Cache: 32 KB Data per core and 96 KB Instructions per module * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, XOP,

, FMA4,

, ABM,

, TBM,

DDR4 SDRAM Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth (" double data rate") interface. Released to the market in 2014, it is a variant of dynamic rand ...

* GPU based on 3rd Generation GCN (Graphics Core Next) architecture

Mobile APUs

Sabine: "Llano" (2011)

* Fabrication 32 nm on

process * Socket

FS1 Fox Sports 1 (FS1) is an American pay television television channel, channel owned by the Fox Sports (United States), Fox Sports Media Group, a unit of Fox Corporation. FS1 replaced the motorsports network Speed (TV network), Speed on August 1 ...

* Upgraded ''Stars'' (AMD 10h architecture) codenamed ''Husky'' CPU cores (K10.5) with no L3 cache, and with ''Redwood''-class integrated graphics on die * L1 Cache: 64 KB Data per core and 64 KB Instructions per core(''BeaverCreek'' for the dual-core variants and ''WinterPark'' for the quad-core variants) * Integrated

controller * GPU:

TeraScale 2 TeraScale is the codename for a family of graphics processing unit microarchitectures developed by ATI Technologies/AMD and their second microarchitecture implementing the unified shader model following '' Xenos''. TeraScale replaced the old f ...

* Select models support Turbo Core technology for faster CPU operation when the thermal specification permits * Support for 1.35 V

DDR3L Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface, and has been in use since 2007. It is the higher-speed ...

-1333 memory, in addition to regular 1.5 V DDR3 memory specified * 2.5 GT/s UMI *

, Enhanced 3DNow!, SSE,

, SSE4a, ABM,

Comal: "Trinity" (2012)

* Fabrication 32 nm on GlobalFoundries SOI process * Socket FS1r2, FP2 * Based on the Piledriver architecture * L1 Cache: 16 KB Data per core and 64 KB Instructions per module * GPU: TeraScale 3 (VLIW4) * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1, XOP,

, FMA4,

, ABM,

, TBM,

* Memory support: 1.35 V

-1600 memory, in addition to regular 1.5 V DDR3 memory specified (Dual-channel) * 2.5 GT/s UMI * Transistors: 1.303 billion * Die size: 246 mm²

"Richland" (2013)

* Fabrication 32 nm on GlobalFoundries SOI process * Socket FS1r2, FP2 * ''Elite Performance APU''. * CPU: Piledriver architecture ** L1 Cache: 16 KB Data per core and 64 KB Instructions per module * GPU: TeraScale 3 (VLIW4) * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1, XOP,

, FMA4,

, ABM,

, TBM,

"Kaveri" (2014)

* Fabrication 28 nm * Socket FP3 * Up to 4

x86 CPU cores with 4 MB of L2 cache. * L1 Cache: 16 KB Data per core and 96 KB Instructions per module * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1, XOP,

, FMA4,

, ABM,

, TBM,

* Three to eight Compute Units (CUs) based on

(GCN) microarchitecture; 1 Compute Unit (CU) consists of 64 Unified Shader Processors : 4 Texture Mapping Units (TMUs) : 1

(ROPs) * AMD Heterogeneous System Architecture (HSA) 2.0 * SIP blocks:

, TrueAudio * Dual-channel (2x64-bit)

memory controller * Integrated custom

co-processor with

Security Extensions

"Carrizo" (2015)

* Fabrication 28 nm * Socket FP4 * Up to 4

x86 CPU cores * L1 Cache: 32 KB Data per core and 96 KB Instructions per module * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, XOP,

, FMA4,

, ABM,

, TBM,

* GPU based on

1.2

"Bristol Ridge" (2016)

* Fabrication 28 nm * Socket FP4 * Two or four " Excavator+" x86 CPU cores * L1 Cache: 32 KB Data per core and 96 KB Instructions per module * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, XOP,

, FMA4,

, ABM,

, TBM,

* GPU based on

1.2 with

decoding

"Raven Ridge" (2017)

* Fabrication 14 nm by

s: 4.94 billion * Socket FP5 *

size: 210 mm² *

CPU cores * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, ABM,

* Fifth generation GCN-based GPU

"Picasso" (2019)

* Fabrication 12 nm by

* Socket FP5 *

size: 210 mm² * Up to four

CPU cores * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, ABM,

* Dual-channel

memory controller * Fifth generation GCN-based GPU

"Renoir" (2020)

* Fabrication 7 nm by TSMC * Socket FP6 *

size: 156 mm² * 9.8 billion transistors on one single 7 nm monolithic die * Up to eight

CPU cores * L1

cache Cache, caching, or caché may refer to: Places United States * Cache, Idaho, an unincorporated community * Cache, Illinois, an unincorporated community * Cache, Oklahoma, a city in Comanche County * Cache, Utah, Cache County, Utah * Cache Count ...

: 64 KB (32 KB data + 32 KB instruction) per core. * L2 cache: 512 KB per core. * Fifth generation GCN-based GPU * Memory support:

-3200 or

LPDDR4 Low-Power Double Data Rate (LPDDR), also known as LPDDR SDRAM, is a type of synchronous dynamic random-access memory that consumes less power and is targeted for mobile computers and devices such as mobile phones. Older variants are also known as ...

-4266 in

dual-channel In the fields of digital electronics and computer hardware, multi-channel memory architecture is a technology that increases the data transfer rate between the DRAM memory and the memory controller by adding more channels of communication between ...

mode. * All the CPUs support 16

lanes.

U

H

"Lucienne" (2021)

* Fabrication 7 nm by TSMC * Socket FP6 *

size: 156 mm² * 9.8 billion transistors on one single 7 nm monolithic die * Up to eight

CPU cores * Fifth generation GCN-based GPU (7 nm Vega)

"Cezanne" (2021)

* Fabrication 7 nm by TSMC * Socket FP6 *

size: 180 mm² * Up to eight

CPU cores * L1

: 64 KB (32 KB data + 32 KB instruction) per core. * L2 cache: 512 KB per core. * Fifth generation GCN-based GPU * Memory support:

-3200 or

-4266 in

mode. * All the CPUs support 16

lanes.

U

H

"Barceló" (2022)

* Fabrication 7 nm by TSMC * Socket FP6 *

size: 180 mm² * Up to eight

CPU cores * L1

: 64 KB (32 KB data + 32 KB instruction) per core. * L2 cache: 512 KB per core. * Fifth generation GCN-based GPU * Memory support:

-3200 or

-4266 in

mode. * All the CPUs support 16

lanes.

"Rembrandt" (2022)

* Fabrication 6 nm by TSMC * Socket FP7 *

size: 210 mm² * Up to eight Zen 3+ CPU cores * Second generation RDNA-based GPU

Ultra-mobile APUs

Brazos: "Desna", "Ontario", "Zacate" (2011)

* Fabrication 40 nm by

* Socket FT1 (BGA-413) * Based on the Bobcat microarchitecture * L1 Cache: 32 KB Data per core and 32 KB Instructions per core *

, SSE,

, SSE4a, ABM,

DirectX 11 Microsoft DirectX is a collection of application programming interfaces (APIs) for handling tasks related to multimedia, especially game programming and video, on Microsoft platforms. Originally, the names of these APIs all began with "Direct", ...

integrated graphics with UVD 3.0 * Z-series denote ''Desna''; C-series denote ''Ontario''; and the E-series denotes ''Zacate'' * 2.50 GT/s UMI (PCIe 1.0 ×4)

Brazos 2.0: "Ontario", "Zacate" (2012)

* Fabrication 40 nm by

* Socket FT1 (BGA-413) * Based on the Bobcat microarchitecture * L1 Cache: 32 KB Data per core and 32 KB Instructions per core *

, SSE,

, SSE4a, ABM,

* PowerNow! * DirectX 11 integrated graphics * C-series denote ''Ontario''; and the E-series denotes ''Zacate'' * 2.50 GT/s UMI (PCIe 1.0 ×4)

Brazos-T: "Hondo" (2012)

* Fabrication 40 nm by

* Socket FT1 (BGA-413) * Based on the Bobcat microarchitecture * L1 Cache: 32 KB Data per core and 32 KB Instructions per core * Found in tablet computers *

, SSE,

, SSE4a, ABM,

* PowerNow! * DirectX 11 integrated graphics * 2.50 GT/s UMI (PCIe 1.0 ×4)

"Kabini", "Temash" (2013)

* Fabrication 28 nm by

* Socket FT3 (BGA) * 2 to 4 CPU Cores (

) * L1 Cache: 32 KB Data per core and 32 KB Instructions per core *

, SSE,

, SSE4a,

, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM,

support * Turbo Dock Technology, C6 and CC6 low power states * GPU based on

(GCN) *

multi-monitor for up to two displays

Temash, Elite Mobility APU

Kabini, Mainstream APU

"Beema", "Mullins" (2014)

* Fabrication 28 nm by

* Socket FT3b (BGA) * CPU: 2 to 4 ( Puma cores) ** L1 Cache: 32 KB Data per core and 32 KB Instructions per core * GPU based on

(GCN) *

, SSE,

, SSE4a,

, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM,

support * Intelligent Turbo Boost * Platform Security Processor, with an integrated

for

execution

Mullins, Tablet/2-in-1 APU

Beema, Notebook APU

"Carrizo-L" (2015)

* Fabrication 28 nm by

* Socket FT3b (BGA), FP4 (µBGA) * CPU: 2 to 4 ( Puma+ cores) ** L1 Cache: 32 KB Data per core and 32 KB Instructions per core * GPU based on

(GCN) *

, SSE,

, SSE4a,

, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM,

support * Intelligent Turbo Boost * Platform Security Processor, with an integrated

for

execution * All models except A8-7410 available in both laptop and all-in-one desktop versions

"Stoney Ridge" (2016)

* Fabrication 28 nm by

* Socket FP4 / FT4 * 2 " Excavator+" x86 CPU cores * L1 Cache: 32 KB Data per core and 96 KB Instructions per module * Single-channel DDR4 memory controller * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, XOP,

, FMA4,

, ABM,

, TBM,

* GPU based on

3rd Generation with

decoding

"Dalí" (2020)

* Fabrication 14 nm by

* Socket FP5 * Two

CPU cores * Over 30% die size reduction over predecessor (Raven Ridge) * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, ABM,

*Dual-channel RAM

"Pollock" (2020)

* Fabrication 14 nm by

* Socket FT5 * Two

CPU cores * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, ABM,

*Single-channel RAM

"Mendocino" (2022)

* Fabrication 7 nm by TSMC * Socket FT6 * Up to four

CPU cores * RDNA2-based GPU

Embedded APUs

G-Series

Brazos: "Ontario" and "Zacate" (2011)

* Fabrication 40 nm * Socket FT1 (BGA-413) * CPU microarchitecture:

Bobcat The bobcat (''Lynx rufus''), also known as the red lynx, is a medium-sized cat native to North America. It ranges from southern Canada through most of the contiguous United States to Oaxaca in Mexico. It is listed as Least Concern on the IUC ...

* L1 Cache: 32 KB Data per core and 32 KB Instructions per core *

, SSE,

, SSE4a, ABM,

* GPU microarchitecture: TeraScale 2 (VLIW5) "Evergreen" * Memory support: single-channel, support up to two DIMMs of DDR3-1333 or DDR3L-1066 * 5 GT/s UMI

"Kabini" (2013, SoC)

* Fabrication 28 nm *

Socket FT3 AMD's Socket FT3 or BGA-769 targets mobile devices and was designed for APUs codenamed ''Kabini'' and ''Temash'', ''Beema'' and ''Mullins'' (Socket FT3b). ''"Kabini"''- and ''"Temash"''-branded products combine Jaguar with Islands (GCN), UVD 3 ...

(769-BGA) * CPU microarchitecture:

Jaguar The jaguar (''Panthera onca'') is a large cat species and the only living member of the genus '' Panthera'' native to the Americas. With a body length of up to and a weight of up to , it is the largest cat species in the Americas and the th ...

* L1 Cache: 32 KB Data per core and 32 KB Instructions per core *

, SSE,

, SSE4a,

, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM,

support. No support for FMA (Fused Multiply-Accumulate).

Trusted Platform Module Trusted Platform Module (TPM, also known as ISO/IEC 11889) is an international standard for a secure cryptoprocessor, a dedicated microcontroller designed to secure hardware through integrated cryptographic keys. The term can also refer to a ch ...

(TPM) 1.2 support * GPU microarchitecture:

(GCN) with

3 (H.264, VC-1, MPEG2, etc.) * Single channel DDR3-1600, 1.25 and 1.35 V voltage level support, support for ECC memory * Integrates A85X, Controller Hub functional block, HD audio, 2 SATA channels, USB 2.0 and USB 3.0 (except GX-210JA)

"Steppe Eagle" (2014, SoC)

* Fabrication 28 nm *

b (769-BGA) * CPU microarchitecture: Puma (microarchitecture), Puma * L1 Cache: 32 KB Data per core and 32 KB Instructions per core *

, SSE,

, SSE4a,

, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM,

support

"Crowned Eagle" (2014, SoC)

* Fabrication 28 nm * Socket FT3b (769-BGA) * CPU microarchitecture: Puma (microarchitecture), Puma * L1 Cache: 32 KB Data per core and 32 KB Instructions per core *

, SSE,

, SSE4a,

, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM,

support * no GPU

LX-Family (2016, SoC)

* Fabrication 28 nm * Socket FT3b (769-BGA) * 2 Puma (microarchitecture), Puma x86 cores with 1MB shared L2 cache * L1 Cache: 32 KB Data per core and 32 KB Instructions per core *

, SSE,

, SSE4a,

, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM,

support * GPU microarchitecture:

(GCN) (1CU) with support for DirectX 11.2 * Single channel 64-bit DDR3 memory with ECC memory, ECC * Integrated Controller Hub supports: PCIe® 2.0 4×1, 2 USB3 + 4 USB2 ports, 2 SATA 2.0/3.0 ports

I-Family: "Brown Falcon" (2016, SoC)

* Fabrication 28 nm * Socket FP4 * 2 or 4

x86 cores with 1MB shared L2 cache * L1 Cache: 32 KB Data per core and 96 KB Instructions per module * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, XOP,

, FMA4,

, ABM,

, TBM,

* GPU microarchitecture:

(GCN) (up to 4 CUs) with support for DirectX 12 * Dual channel 64-bit DDR4 or DDR3 memory with ECC memory, ECC * 4K × 2K H.265 decode capability and multi format encode and decode * Integrated Controller Hub supports: PCIe 3.0 1×4, PCIe 2/3 4×1, 2 USB3 + 2 USB2 ports, 2 SATA 2.0/3.0 ports

J-Family: "Prairie Falcon" (2016, SoC)

* Fabrication 28 nm * Socket FP4 * 2 " Excavator+" x86 cores with 1MB shared L2 cache * L1 Cache: 32 KB Data per core and 96 KB Instructions per module * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, XOP,

, FMA4,

, ABM,

, TBM,

* GPU microarchitecture: Radeon R5E

(GCN) (up to 3 CUs) with support for DirectX 12 * Single channel 64-bit DDR4 or DDR3 memory * 4K × 2K H.265 decode capability with 10-bit compatibility and multi format encode and decode * Integrated Controller Hub supports: PCIe 3.0 1×4, PCIe 2/3 4×1, 2 USB3 + 2 USB2 ports, 2 SATA 2.0/3.0 ports

R-Series

Comal: "Trinity" (2012)

* Fabrication 32 nm * Socket FP2 (BGA-827), FS1r2 * CPU microarchitecture: Piledriver * L1 Cache: 16 KB Data per core and 64 KB Instructions per module * MMX, SSE,

, SSE4a,

, AES,

1.1, XOP,

, FMA4,

, ABM,

, TBM * GPU microarchitecture: TeraScale 3, TeraScale 3 (VLIW4) "Northern Islands" * Memory support: dual-channel 1.35 V

-1600 memory, in addition to regular 1.5 V DDR3 * 2.5 GT/s UMI * Die size: 246 mm²; Transistors: 1.303 billion * OpenCL 1.1 and OpenGL 4.2 support

"Bald Eagle" (2014)

* Fabrication 28 nm * Socket FP3 * Up to 4

x86 cores * L1 Cache: 16 KB Data per core and 96 KB Instructions per module * MMX, SSE,

, SSE4a,

, AES,

1.1, XOP,

, FMA4,

, ABM,

, TBM * GPU microarchitecture:

(GCN) (up to 8 CUs) with support for DirectX 11.1 and OpenGL 4.2 * Dual channel DDR3 memory with ECC memory, ECC * Unified Video Decode (UVD) 4.2 and Video Coding Engine (VCE) 2.0

"Merlin Falcon" (2015, SoC)

* Fabrication 28 nm * Socket FP4 * Up to 4

x86 cores * L1 Cache: 32 KB Data per core and 96 KB Instructions per module * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, XOP,

, FMA4,

, ABM,

, TBM,

* GPU microarchitecture:

(GCN) (up to 8 CUs) with support for DirectX 12 * Dual channel 64-bit DDR4 or DDR3 memory with ECC memory, ECC * Unified Video Decode (UVD) 6 (4K H.265 and H.264 decode) and Video Coding Engine (VCE) 3.1 (4K H.264 encode) * Dedicated AMD Secure Processor supports secure boot with AMD Hardware Validated Boot (HVB) * Integrated FCH featuring PCIe 3.0 USB3.0, SATA3, SD, GPIO, SPI, I2S, I2C, UART

1000-Series

V1000-Family: "Great Horned Owl" (2018, SoC)

* Fabrication 14 nm by

* Up to 4

cores * Socket FP5 * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, ABM,

* Dual channel DDR4 memory with ECC memory, ECC * Fifth generation GCN based GPU

R1000-Family: "Banded Kestrel" (2019, SoC)

* Fabrication 14 nm by

* Up to 2

cores * Socket FP5 * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, ABM,

* Dual channel DDR4 memory with ECC memory, ECC * Fifth generation GCN based GPU

2000-Series

V2000-Family: "Grey Hawk" (2020, SoC)

* Fabrication 7 nm by

* Up to 8

cores * Fifth generation GCN based GPU

R2000-Family: "River Hawk" (2022, SoC)

* Fabrication 12 nm by

* Up to 4

cores * MMX, SSE,

, SSE4a,

, AES,

, AVX 1.1,

, ABM,

Custom APUs

As of May 1, 2013, AMD opened the doors of their "semi-custom" business unit. Since these chips are custom-made for specific customer needs, they vary widely from both consumer-grade APUs and even the other custom-built ones. Some notable examples of semi-custom chips that have come from this sector include the chips from the PlayStation 4 and Xbox One. So far the size of the integrated GPU in these semi-custom APUs exceed by far the GPU size in the consumer-grade APUs.

Notes

References

External links

*
Technical specification AMD products

AMD products and technologies
{{DEFAULTSORT:AMD accelerated processing unit microprocessors AMD x86 microprocessors, *Fusion Lists of microprocessors

Features overview

Graphics API overview

Desktop APUs

Lynx: "Llano" (2011)

Virgo: "Trinity" (2012)

"Richland" (2013)

"Kabini" (2013, SoC)

"Kaveri" (2014) & "Godavari" (2015)

"Carrizo" (2016)

"Bristol Ridge" (2016)

"Raven Ridge" (2018)

"Picasso" (2019)

"Renoir" (2020)

"Cezanne" (2021)

"Raphael" (2022)

Server APUs

Opteron X2100-series "Kyoto" (2013)

Opteron X3000-series "Toronto" (2017)

Mobile APUs

Sabine: "Llano" (2011)

Comal: "Trinity" (2012)

"Richland" (2013)

"Kaveri" (2014)

"Carrizo" (2015)

"Bristol Ridge" (2016)

"Raven Ridge" (2017)

"Picasso" (2019)

"Renoir" (2020)

U

H

"Lucienne" (2021)

"Cezanne" (2021)

U

H

"Barceló" (2022)

"Rembrandt" (2022)

Ultra-mobile APUs

Brazos: "Desna", "Ontario", "Zacate" (2011)

Brazos 2.0: "Ontario", "Zacate" (2012)

Brazos-T: "Hondo" (2012)

"Kabini", "Temash" (2013)

Temash, Elite Mobility APU

Kabini, Mainstream APU

"Beema", "Mullins" (2014)

Mullins, Tablet/2-in-1 APU

Beema, Notebook APU

"Carrizo-L" (2015)

"Stoney Ridge" (2016)

"Dalí" (2020)

"Pollock" (2020)

"Mendocino" (2022)

Embedded APUs

G-Series

Brazos: "Ontario" and "Zacate" (2011)

"Kabini" (2013, SoC)

"Steppe Eagle" (2014, SoC)

"Crowned Eagle" (2014, SoC)

LX-Family (2016, SoC)

I-Family: "Brown Falcon" (2016, SoC)

J-Family: "Prairie Falcon" (2016, SoC)

R-Series

Comal: "Trinity" (2012)

"Bald Eagle" (2014)

"Merlin Falcon" (2015, SoC)

1000-Series

V1000-Family: "Great Horned Owl" (2018, SoC)

R1000-Family: "Banded Kestrel" (2019, SoC)

2000-Series

V2000-Family: "Grey Hawk" (2020, SoC)

R2000-Family: "River Hawk" (2022, SoC)

Custom APUs

See also

Notes

References

External links