|
Steamroller (microarchitecture)
AMD Steamroller Family 15h is a microarchitecture developed by AMD for AMD APUs, which succeeded Piledriver in the beginning of 2014 as the third-generation Bulldozer-based microarchitecture. Steamroller APUs continue to use two-core modules as their predecessors, while aiming at achieving greater levels of parallelism. Microarchitecture ''Steamroller'' still features two-core modules found in ''Bulldozer'' and ''Piledriver'' designs called clustered multi-thread (CMT), meaning that one module is marketed as a dual-core processor. The focus of ''Steamroller'' is for greater parallelism. Improvements center on independent instruction decoders for each core within a module, 25% more of the maximum width dispatches per thread, better instruction schedulers, improved perceptron branch predictor, larger and smarter caches, up to 30% fewer instruction cache misses, branch misprediction rate reduced by 20%, dynamically resizable L2 cache, micro-operations queue, more internal regist ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Advanced Micro Devices
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactured its own processors, the company later outsourced its manufacturing, a practice known as going fabless, after GlobalFoundries was spun off in 2009. AMD's main products include microprocessors, motherboard chipsets, embedded processors, graphics processors, and FPGAs for servers, workstations, personal computers, and embedded system applications. History First twelve years Advanced Micro Devices was formally incorporated by Jerry Sanders, along with seven of his colleagues from Fairchild Semiconductor, on May 1, 1969. Sanders, an electrical engineer who was the director of marketing at Fairchild, had, like many Fairchild executives, grown frustrated with the increasing lack of support, opportunity, and flexibility within th ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Processing Power
In computing, computer performance is the amount of useful work accomplished by a computer system. Outside of specific contexts, computer performance is estimated in terms of accuracy, efficiency and speed of executing computer program instructions. When it comes to high computer performance, one or more of the following factors might be involved: * Short response time for a given piece of work. * High throughput (rate of processing work). * Low utilization of computing resource(s). ** Fast (or highly compact) data compression and decompression. * High availability of the computing system or application. * High bandwidth. * Short data transmission time. Technical and non-technical definitions The performance of any computer system can be evaluated in measurable, technical terms, using one or more of the metrics listed above. This way the performance can be * Compared relative to other systems or the same system before/after changes * In absolute terms, e.g. for fulfilling a cont ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
YouTube
YouTube is a global online video platform, online video sharing and social media, social media platform headquartered in San Bruno, California. It was launched on February 14, 2005, by Steve Chen, Chad Hurley, and Jawed Karim. It is owned by Google, and is the List of most visited websites, second most visited website, after Google Search. YouTube has more than 2.5 billion monthly users who collectively watch more than one billion hours of videos each day. , videos were being uploaded at a rate of more than 500 hours of content per minute. In October 2006, YouTube was bought by Google for $1.65 billion. Google's ownership of YouTube expanded the site's business model, expanding from generating revenue from advertisements alone, to offering paid content such as movies and exclusive content produced by YouTube. It also offers YouTube Premium, a paid subscription option for watching content without ads. YouTube also approved creators to participate in Google's Google AdSens ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
AMD Eyefinity
AMD Eyefinity is a brand name for AMD video card products that support multi-monitor setups by integrating multiple (up to six) display controllers on one GPU. AMD Eyefinity was introduced with the Radeon HD 5000 Series "Evergreen" in September 2009 and has been available on APUs and professional-grade graphics cards branded AMD FirePro as well. AMD Eyefinity supports a maximum of 2 non-DisplayPort displays (e.g., HDMI, DVI, VGA, DMS-59, VHDCI) (which AMD calls "legacy output") and up to 6 DisplayPort displays simultaneously using a single graphics card or APU. To feed more than two displays, the additional panels must have native DisplayPort support. Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed. The setup of large video walls by connecting multiple computers over Gigabit Ethernet or Ethernet is also supported. The version of AMD Eyefinity (aka DCE, display controller engine) introduced with Excavator-based Carrizo APUs features a Video underlay pi ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Render Output Unit
In computer graphics, the render output unit (ROP) or raster operations pipeline is a hardware component in modern graphics processing units (GPUs) and one of the final steps in the rendering process of modern graphics cards. The pixel pipelines take pixel (each pixel is a dimensionless point) and texel information and process it, via specific matrix and vector operations, into a final pixel or depth value; this process is called rasterization. Thus, ROPs control antialiasing, when more than one sample is merged into one pixel. The ROPs perform the transactions between the relevant buffers in the local memory – this includes writing or reading values, as well as blending them together. Dedicated antialiasing hardware used to perform hardware-based antialiasing methods like MSAA is contained in ROPs. All data rendered has to travel through the ROP in order to be written to the framebuffer, from there it can be transmitted to the display. Therefore, the ROP is where the GPU's ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Texture Mapping Unit
In computer graphics, a texture mapping unit (TMU) is a component in modern graphics processing units (GPUs). They are able to rotate, resize, and distort a bitmap image to be placed onto an arbitrary plane of a given 3D model as a texture, in a process called texture mapping. In modern graphics cards it is implemented as a discrete stage in a graphics pipeline, whereas when first introduced it was implemented as a separate processor, e.g. as seen on the Voodoo2 graphics card. Background and history The TMU came about due to the compute demands of sampling and transforming a flat image (as the texture map) to the correct angle and perspective it would need to be in 3D space. The compute operation is a large matrix multiply, which CPUs of the time (early Pentiums) could not cope with at acceptable performance. In 2013, TMUs are part of the shader pipeline and decoupled from the Render Output Pipelines (ROPs). For example, in AMD's Cypress GPU, each shader pipeline (of which th ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Unified Shader Model
In the field of 3D computer graphics, the unified shader model (known in Direct3D 10 as "Shader Model 4.0") refers to a form of shader hardware in a graphical processing unit (GPU) where all of the shader stages in the rendering pipeline (geometry, vertex, pixel, etc.) have the same capabilities. They can all read textures and buffers, and they use instruction sets that are almost identical. History Earlier GPUs generally included two types of shader hardware, with the ''vertex shaders'' having considerably more instructions than the simpler ''pixel shaders''. This lowered the cost of implementation of the GPU as a whole, and allowed more shaders in total on a single unit. This was at the cost of making the system less flexible, and sometimes leaving one set of shaders idle if the workload used one more than the other. As improvements in fabrication continued, this distinction became less useful. ATI Technologies introduced a unified architecture on the hardware they developed f ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SemiAccurate
''SemiAccurate'' (S, A in short) is a U.S.-based technology-news and -opinion web site, founded in 2009 by Charlie Demerjian after his departure from ''The Inquirer''. The site lists as its contributors: Charlie Demerjian (the site's founder), Thomas Ryan and Leo Yim. the site operates under a partial paywall model, making the majority of its content publicly available at no cost to readers - but subscribers to the "Student-" and "Professional-"level tiers receive access to special analysis articles and reports on industry trends similar to white papers. Notable Stories In February 2010, SemiAccurate ran a story on the yet to be released, "Fermi", microprocessor from Nvidia, which called the chip, "Hot, Slow, Late and Unmanufacturable." In August 2010, a tip off from a reader helped SemiAccurate to cover Sony admitting to defective graphics chips in some of its laptops. News organization IDG credited SemiAccurate for first reporting the story. In May 2011, SemiAccurate pub ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
AMD TrueAudio
TrueAudio is the name given to AMD's ASIC intended to serve as dedicated co-processor for the calculations of computationally expensive advanced audio signal processing, like e.g. convolution reverberation effects and 3D audio effects. TrueAudio is integrated into some of the AMD GPUs and APUs available since 2013. Overview TrueAudio is a DSP for audio based on Cadence Tensilica HiFi EP DSP with Tensilica Xtensa SP float support. AMD claimed that a few simple audio effects can use up to 14% of the CPU. Audiokinetic claimed that it is up to 10%. Independent software vendors (ISV), such as game developers, can use what is called a Wwise audio plugin to offload such computations to the TrueAudio DSPs. The on-die TrueAudio DSPs provide a better "silicon area to computing power" ratio and "power consumption to computing power" ratio for audio processing than the CPU, effectively making it an audio acceleration unit. Any additional benefits of the TrueAudio DSPs, such as "better ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Video Coding Engine
Video Code Engine (VCE, was earlier referred to as Video Coding Engine, Video Compression Engine or Video Codec Engine in official AMD documentation) is AMD's video encoding application-specific integrated circuit implementing the video codec H.264/MPEG-4 AVC. Since 2012 it was integrated into all of their GPUs and APUs except Oland. VCE was introduced with the Radeon HD 7000 Series on 22 December 2011. VCE occupies a considerable amount of the die surface at the time of its introduction and is not to be confused with AMD's Unified Video Decoder (UVD). As of AMD Raven Ridge (released January 2018), UVD and VCE were succeeded by Video Core Next (VCN). Overview The handling of video data involves computation of data compression algorithms and possibly of video processing algorithms. As the template compression methods shows, lossy video compression algorithms involve the steps: motion estimation (ME), discrete cosine transform (DCT), and entropy encoding (EC). AMD Video Cod ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Unified Video Decoder
Unified Video Decoder (UVD, previously called Universal Video Decoder) is the name given to AMD's dedicated video decoding ASIC. There are multiple versions implementing a multitude of video codecs, such as H.264 and VC-1. UVD was introduced with the Radeon HD 2000 Series and is integrated into some of AMD's GPUs and APUs. UVD occupies a considerable amount of the die surface at the time of its introduction and is not to be confused with AMD's Video Coding Engine (VCE). As of AMD Raven Ridge (released January 2018), UVD and VCE were succeeded by Video Core Next (VCN). Overview The UVD is based on an ATI Xilleon video processor, which is incorporated onto the same die as the GPU and is part of the ATI Avivo HD for hardware video decoding, along with the Advanced Video Processor (AVP). UVD, as stated by AMD, handles decoding of H.264/AVC, and VC-1 video codecs entirely in hardware. The UVD technology is based on the Cadence Tensilica Xtensa processor, which was originally licens ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Semiconductor Intellectual Property Core
In electronic design, a semiconductor intellectual property core (SIP core), IP core, or IP block is a reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of one party. IP cores can be licensed to another party or owned and used by a single party. The term comes from the licensing of the patent or source code copyright that exists in the design. Designers of application-specific integrated circuits (ASIC) and systems of field-programmable gate array (FPGA) logic can use IP cores as building blocks. History The licensing and use of IP cores in chip design came into common practice in the 1990s. There were many licensors and also many foundries competing on the market. In 2013, the most widely licensed IP cores are from Arm Holdings (43.2% market share), Synopsys Inc. (13.9% market share), Imagination Technologies (9% market share) and Cadence Design Systems (5.1% market share). Types of IP cores The use of an IP core in chip ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
