Semiconductor device fabrication is the process used to manufacture
semiconductor devices
A semiconductor device is an electronic component that relies on the electronic properties of a semiconductor material (primarily silicon, germanium, and gallium arsenide, as well as organic semiconductors) for its function. Its conductivity l ...
, typically
integrated circuit (IC) chips such as modern computer processors, microcontrollers, and memory chips such as
NAND flash
Flash memory is an electronic non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash, are named for the NOR and NAND logic gates. Both use ...
and
DRAM that are present in everyday
electrical
Electricity is the set of physical phenomena associated with the presence and motion of matter that has a property of electric charge. Electricity is related to magnetism, both being part of the phenomenon of electromagnetism, as described ...
and
electronic
Electronic may refer to:
*Electronics, the science of how to control electric energy in semiconductor
* ''Electronics'' (magazine), a defunct American trade journal
*Electronic storage, the storage of data using an electronic device
*Electronic co ...
devices. It is a multiple-step sequence of
photolithographic
In integrated circuit manufacturing, photolithography or optical lithography is a general term used for techniques that use light to produce minutely patterned thin films of suitable materials over a substrate, such as a silicon wafer, to protect ...
and chemical processing steps (such as
surface passivation
A surface, as the term is most generally used, is the outermost or uppermost layer of a physical object or space. It is the portion or region of the object that can first be perceived by an observer using the senses of sight and touch, and is ...
,
thermal oxidation
In microfabrication, thermal oxidation is a way to produce a thin layer of oxide (usually silicon dioxide) on the surface of a wafer. The technique forces an oxidizing agent to diffuse into the wafer at high temperature and react with it. The ra ...
,
planar diffusion and
junction isolation) during which
electronic circuits
An electronic circuit is composed of individual electronic components, such as resistors, transistors, capacitors, inductors and diodes, connected by conductive wires or traces through which electric current can flow. It is a type of electrical ...
are gradually created on a
wafer
A wafer is a crisp, often sweet, very thin, flat, light and dry biscuit, often used to decorate ice cream, and also used as a garnish on some sweet dishes. Wafers can also be made into cookies with cream flavoring sandwiched between them. They ...
made of pure
semiconducting
A semiconductor is a material which has an electrical resistivity and conductivity, electrical conductivity value falling between that of a electrical conductor, conductor, such as copper, and an insulator (electricity), insulator, such as glas ...
material.
Silicon
Silicon is a chemical element with the symbol Si and atomic number 14. It is a hard, brittle crystalline solid with a blue-grey metallic luster, and is a tetravalent metalloid and semiconductor. It is a member of group 14 in the periodic ta ...
is almost always used, but various
compound semiconductor
Semiconductor materials are nominally small band gap insulators. The defining property of a semiconductor material is that it can be compromised by doping it with impurities that alter its electronic properties in a controllable way.
Because of ...
s are used for specialized applications.
The entire manufacturing process takes time, from start to packaged chips ready for shipment, at least six to eight weeks (tape-out only, not including the circuit design) and is performed in highly specialized
semiconductor fabrication plant
In the microelectronics industry, a semiconductor fabrication plant (commonly called a fab; sometimes foundry) is a factory where devices such as integrated circuits are manufactured.
Fabs require many expensive devices to function. Estimate ...
s, also called foundries or fabs.
All fabrication takes place inside a clean room, which is the central part of a fab. In more advanced semiconductor devices, such as modern
14/
10/
7 nm
In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nm process as the MOSFET technology node following the 10 nm node. It is based on FinFET (fin field-effect transistor) technology, ...
nodes, fabrication can take up to 15 weeks, with 11–13 weeks being the industry average. Production in advanced fabrication facilities is completely automated and carried out in a hermetically sealed nitrogen environment to improve yield (the percent of microchips that function correctly in a wafer), with automated material handling systems taking care of the transport of wafers from machine to machine. Wafers are transported inside
FOUP
FOUP is an acronym for Front Opening Unified Pod or Front Opening Universal Pod.
It is a specialised plastic enclosure designed to hold silicon wafers
A wafer is a crisp, often sweet, very thin, flat, light and dry biscuit, often used to deco ...
s, special sealed plastic boxes. All machinery and FOUPs contain an internal nitrogen atmosphere. The air inside the machinery and FOUPs is usually kept cleaner than the surrounding air in the cleanroom. This internal atmosphere is known as a mini-environment. Fabrication plants need large amounts of liquid nitrogen to maintain the atmosphere inside production machinery and FOUPs, which is constantly purged with nitrogen.
Size
A specific semiconductor process has specific rules on the minimum size and spacing for features on each layer of the chip.
Often a newer semiconductor processes has smaller minimum sizes and tighter spacing which allow a simple
die shrink
The term die shrink (sometimes optical shrink or process shrink) refers to the scaling of metal-oxide-semiconductor (MOS) devices. The act of shrinking a die is to create a somewhat identical circuit using a more advanced fabrication process, ...
to reduce costs and improve performance.
partly due to an increase in transistor density (number of transistors per square millimeter).
Early semiconductor processes had arbitrary names such as
HMOS
In integrated circuits, depletion-load NMOS is a form of digital logic family that uses only a single power supply voltage, unlike earlier NMOS (n-type metal-oxide semiconductor) logic families that needed more than one different power supply ...
III,
CHMOS
CHMOS refers to one of a series of Intel CMOS processes developed from their HMOS process. (H stands for high-density). It was first developed in 1981.
CHMOS was used in the Intel 80C51BH, a new version of their standard MCS-51 microcontroll ...
V;
later ones are referred to by size such as
90 nm process
The 90 nm process refers to the level of MOSFET ( CMOS) fabrication process technology that was commercialized by the 2003–2005 timeframe, by leading semiconductor companies like Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, El ...
.
By industry standard, each generation of the semiconductor manufacturing process, also known as technology node or process node, is designated by the process’s minimum feature size. Technology nodes, also known as "process technologies" or simply "nodes", are typically indicated by the size in
nanometers
330px, Different lengths as in respect to the molecular scale.
The nanometre (international spelling as used by the International Bureau of Weights and Measures; SI symbol: nm) or nanometer (American and British English spelling differences#-re ...
(or historically
micrometers
The micrometre ( international spelling as used by the International Bureau of Weights and Measures; SI symbol: μm) or micrometer (American spelling), also commonly known as a micron, is a unit of length in the International System of Unit ...
) of the process'
transistor gate length. However, this has not been the case since 1994. Initially transistor gate length was smaller than that suggested by the process node name (e.g. 350 nm node); however this trend reversed in 2009. The nanometers used to name process nodes has become more of a marketing term that has no relation with actual feature sizes nor transistor density (number of transistors per square millimeter). For example, Intel's former 10 nm process actually has features (the tips of
FinFET
A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, ...
fins) with a width of 7 nm, Intel's former 10 nm process is similar in transistor density to TSMC's 7 nm processes, while GlobalFoundries' 12 and 14 nm processes have similar feature sizes.
History
20th century
An improved type of MOSFET technology,
CMOS, was developed by
Chih-Tang Sah and
Frank Wanlass Frank Marion Wanlass (May 17, 1933 in Thatcher, AZ – September 9, 2010 in Santa Clara, California) was an American electrical engineer. He is best known for inventing CMOS (complementary MOS) logic with Chih-Tang Sah in 1963. CMOS has since ...
at
Fairchild Semiconductor in 1963.
CMOS was commercialised by
RCA
The RCA Corporation was a major American electronics company, which was founded as the Radio Corporation of America in 1919. It was initially a patent trust owned by General Electric (GE), Westinghouse, AT&T Corporation and United Fruit Comp ...
in the late 1960s.
RCA commercially used CMOS for its
4000-series integrated circuits in 1968, starting with a 20µm process before gradually scaling to a
10 µm process over the next several years.
Semiconductor device manufacturing has since spread from
Texas
Texas (, ; Spanish: ''Texas'', ''Tejas'') is a state in the South Central region of the United States. At 268,596 square miles (695,662 km2), and with more than 29.1 million residents in 2020, it is the second-largest U.S. state by ...
and
California
California is a state in the Western United States, located along the Pacific Coast. With nearly 39.2million residents across a total area of approximately , it is the most populous U.S. state and the 3rd largest by area. It is also the m ...
in the 1960s to the rest of the world, including
Asia
Asia (, ) is one of the world's most notable geographical regions, which is either considered a continent in its own right or a subcontinent of Eurasia, which shares the continental landmass of Afro-Eurasia with Africa. Asia covers an are ...
,
Europe
Europe is a large peninsula conventionally considered a continent in its own right because of its great physical size and the weight of its history and traditions. Europe is also considered a subcontinent of Eurasia and it is located entirel ...
, and the
Middle East
The Middle East ( ar, الشرق الأوسط, ISO 233: ) is a geopolitical region commonly encompassing Arabia (including the Arabian Peninsula and Bahrain), Asia Minor (Asian part of Turkey except Hatay Province), East Thrace (Europ ...
.
21st century
The
semiconductor industry is a global business today. The leading semiconductor manufacturers typically have facilities all over the world.
Samsung Electronics
Samsung Electronics Co., Ltd. (, sometimes shortened to SEC and stylized as SΛMSUNG) is a South Korean multinational electronics corporation headquartered in Yeongtong-gu, Suwon, South Korea. It is the pinnacle of the Samsung chaebol, a ...
, the world's largest manufacturer of semiconductors, has facilities in South Korea and the US.
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...
, the second-largest manufacturer, has facilities in Europe and Asia as well as the US.
TSMC
Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational semiconductor contract manufacturing and design company. It is the world's most valuable semiconductor company, the world' ...
, the world's largest
pure play foundry, has facilities in Taiwan, China, Singapore, and the US.
Qualcomm and
Broadcom
Broadcom Inc. is an American designer, developer, manufacturer and global supplier of a wide range of semiconductor and infrastructure software products. Broadcom's product offerings serve the data center, networking, software, broadband, wirel ...
are among the biggest
fabless
Fabless manufacturing is the design and sale of hardware devices and semiconductor chips while outsourcing their fabrication (or ''fab'') to a specialized manufacturer called a semiconductor foundry. These foundries are typically, but not exclu ...
semiconductor companies, outsourcing their production to companies like TSMC. They also have facilities spread in different countries.
Since 2009, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch. For example,
GlobalFoundries
GlobalFoundries Inc. (GF or GloFo) is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, ...
'
7 nm
In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nm process as the MOSFET technology node following the 10 nm node. It is based on FinFET (fin field-effect transistor) technology, ...
process is similar to
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...
's
10 nm
The following are examples of orders of magnitude for different lengths.
__TOC__
Overview
Detailed list
To help compare different orders of magnitude, the following list describes various lengths between 1.6 \times 10^ metres and 10 ...
process, thus the conventional notion of a process node has become blurred. Additionally, TSMC and
Samsung
The Samsung Group (or simply Samsung) ( ko, 삼성 ) is a South Korean multinational manufacturing conglomerate headquartered in Samsung Town, Seoul, South Korea. It comprises numerous affiliated businesses, most of them united under the ...
's 10 nm processes are only slightly denser than Intel's 14 nm in transistor density. They are actually much closer to Intel's 14 nm process than they are to Intel's 10 nm process (e.g. Samsung's 10 nm processes' fin pitch is the exact same as that of Intel's 14 nm process: 42 nm).
As of 2019,
14 nanometer
The 14 nm process refers to the MOSFET technology node that is the successor to the 22 nm process, 22nm (or 20nm) node. The 14nm was so named by the International Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following ...
and
10 nanometer
In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nm process as the MOSFET technology node following the 14 nm node. 10 nm class denotes chips made using process technologies between 10 ...
chips are in mass production by Intel,
UMC, TSMC, Samsung,
Micron
The micrometre ( international spelling as used by the International Bureau of Weights and Measures; SI symbol: μm) or micrometer (American spelling), also commonly known as a micron, is a unit of length in the International System of Un ...
,
SK Hynix
SK hynix Inc. is a South Korean supplier of dynamic random-access memory (DRAM) chips and flash memory chips. Hynix is the world's second-largest memory chipmaker (after Samsung Electronics) and the world's third-largest semiconductor company. ...
,
Toshiba Memory and GlobalFoundries, with
7 nanometer
In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nm process as the MOSFET technology node following the 10 nm node. It is based on FinFET (fin field-effect transistor) technology, ...
process chips in mass production by
TSMC
Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational semiconductor contract manufacturing and design company. It is the world's most valuable semiconductor company, the world' ...
and
Samsung
The Samsung Group (or simply Samsung) ( ko, 삼성 ) is a South Korean multinational manufacturing conglomerate headquartered in Samsung Town, Seoul, South Korea. It comprises numerous affiliated businesses, most of them united under the ...
, although their 7nanometer node definition is similar to
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...
's 10 nanometer process. The
5 nanometer process began being produced by Samsung in 2018. As of 2019, the node with the highest
transistor density is TSMC's 5nanometer N5 node, with a density of 171.3million transistors per square millimeter. In 2019, Samsung and TSMC announced plans to produce
3 nanometer
In semiconductor manufacturing, the 3 nm process is the next die shrink after the 5 nanometer MOSFET (metal–oxide–semiconductor field-effect transistor) technology node. , Taiwanese chip manufacturer TSMC plans to put a 3 nm, se ...
nodes. GlobalFoundries has decided to stop the development of new nodes beyond 12 nanometers in order to save resources, as it has determined that setting up a new fab to handle sub-12 nm orders would be beyond the company's financial abilities. , Samsung is the industry leader in advanced semiconductor scaling, followed by TSMC and then Intel.
List of steps
This is a list of processing techniques that are employed numerous times throughout the construction of a modern electronic device; this list does not necessarily imply a specific order. Equipment for carrying out these processes is made by
a handful of companies. All equipment needs to be tested before a semiconductor fabrication plant is started. These processes are done after
integrated circuit design
Integrated circuit design, or IC design, is a sub-field of electronics engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic compon ...
.
* Wafer processing
** Wet cleans
*** Cleaning by solvents such as
acetone
Acetone (2-propanone or dimethyl ketone), is an organic compound with the formula . It is the simplest and smallest ketone (). It is a colorless, highly volatile and flammable liquid with a characteristic pungent odour.
Acetone is miscib ...
,
trichloroethylene
The chemical compound trichloroethylene is a halocarbon commonly used as an industrial solvent. It is a clear, colourless non-flammable liquid with a chloroform-like sweet smell. It should not be confused with the similar 1,1,1-trichloroethane, w ...
and
ultrapure water
Ultrapure water (UPW), high-purity water or highly purified water (HPW) is water that has been purified to uncommonly stringent specifications. Ultrapure water is a term commonly used in manufacturing to emphasize the fact that the water is treated ...
***
Piranha solution
Piranha solution, also known as piranha etch, is a mixture of sulfuric acid () and hydrogen peroxide (), used to clean organic compound, organic residues off substrates. Because the mixture is a strong oxidizing agent, it will decompose most orga ...
***
RCA clean
**
Surface passivation
A surface, as the term is most generally used, is the outermost or uppermost layer of a physical object or space. It is the portion or region of the object that can first be perceived by an observer using the senses of sight and touch, and is ...
**
Photolithography
**
Ion implantation
Ion implantation is a low-temperature process by which ions of one element are accelerated into a solid target, thereby changing the physical, chemical, or electrical properties of the target. Ion implantation is used in semiconductor device fa ...
(in which
dopant
A dopant, also called a doping agent, is a trace of impurity element that is introduced into a chemical material to alter its original electrical or optical properties. The amount of dopant necessary to cause changes is typically very low. When ...
s are embedded in the wafer creating regions of increased or decreased conductivity)
**
Etching (microfabrication)
Etching is used in microfabrication to chemically remove layers from the surface of a wafer during manufacturing. Etching is a critically important process module, and every wafer undergoes many etching steps before it is complete.
For many etch ...
***
Dry etching
Dry etching refers to the removal of material, typically a masked pattern of semiconductor material, by exposing the material to a bombardment of ions (usually a plasma of reactive gases such as fluorocarbons, oxygen, chlorine, boron trichloride; ...
(
Plasma etching
Plasma etching is a form of plasma processing used to fabricate integrated circuits. It involves a high-speed stream of glow discharge ( plasma) of an appropriate gas mixture being shot (in pulses) at a sample. The plasma source, known as etch spe ...
)
****
Reactive-ion etching
Reactive-ion etching (RIE) is an etching technology used in microfabrication. RIE is a type of dry etching which has different characteristics than wet etching. RIE uses chemically reactive plasma to remove material deposited on wafers. The pl ...
(RIE)
*****
Deep reactive-ion etching
*****
Atomic layer etching (ALE)
***
Wet etching
****
Buffered oxide etch Buffered oxide etch (BOE), also known as buffered HF or BHF, is a wet etchant used in microfabrication. Its primary use is in etching thin films of silicon dioxide (SiO2) or silicon nitride (Si3N4). It is a mixture of a buffering agent, such as a ...
**
Plasma ashing
In semiconductor manufacturing plasma ashing is the process of removing the photoresist (light sensitive coating) from an etched wafer. Using a plasma source, a monatomic (single atom) substance known as a reactive species is generated. Oxygen o ...
** Thermal treatments
***
Rapid thermal anneal
Rapid thermal processing (RTP) is a semiconductor manufacturing process which heats silicon wafers to temperatures exceeding 1,000°C for not more than a few seconds. During cooling wafer temperatures must be brought down slowly to prevent disloc ...
***
Furnace anneal
Furnace annealing is a process used in semiconductor device fabrication which consist of heating multiple semiconductor wafers in order to affect their electrical properties. Heat treatments are designed for different effects. Wafers can be heated ...
s
***
Thermal oxidation
In microfabrication, thermal oxidation is a way to produce a thin layer of oxide (usually silicon dioxide) on the surface of a wafer. The technique forces an oxidizing agent to diffuse into the wafer at high temperature and react with it. The ra ...
**
Chemical vapor deposition (CVD)
**
Atomic layer deposition (ALD)
**
Physical vapor deposition
Physical vapor deposition (PVD), sometimes called physical vapor transport (PVT), describes a variety of vacuum deposition methods which can be used to produce thin films and coatings on substrates including metals, ceramics, glass, and polym ...
(PVD)
**
Molecular beam epitaxy
Molecular-beam epitaxy (MBE) is an epitaxy method for thin-film deposition of single crystals. MBE is widely used in the manufacture of semiconductor devices, including transistors, and it is considered one of the fundamental tools for the devel ...
(MBE)
** Laser lift-off (for
LED production)
** Electrochemical deposition (ECD). See
Electroplating
**
Chemical-mechanical polishing
Chemical mechanical polishing (CMP) or planarization is a process of smoothing surfaces with the combination of chemical and mechanical forces. It can be thought of as a hybrid of chemical etching and free abrasive polishing.
Description
The pro ...
(CMP)
**
Wafer testing Wafer testing is a step performed during semiconductor device fabrication after BEOL process is finished. During this step, performed before a wafer is sent to die preparation, all individual integrated circuits that are present on the wafer are tes ...
(where the electrical performance is verified using
Automatic Test Equipment, binning and/or
laser trimming
{{Unreferenced, date=June 2015
Laser trimming is the manufacturing process of using a laser to adjust the operating parameters of an electronic circuit.
One of the most common applications uses a laser to burn away small portions of resistors, ...
may also be carried out at this step)
*
Die preparation
Die preparation is a step of semiconductor device fabrication during which a wafer is prepared for IC packaging and IC testing. The process of die preparation typically consists of two steps: wafer mounting and wafer dicing.
Wafer mounting
Wa ...
**
Through-silicon via
In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative ...
manufacture (For
three-dimensional integrated circuit
A three-dimensional integrated circuit (3D IC) is a MOS (metal-oxide semiconductor) integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or ...
s)
** Wafer mounting (wafer is mounted onto a metal frame using
Dicing tape
Dicing tape is a backing tape used during wafer dicing or some other microelectronic substrate separation, the cutting apart of pieces of semiconductor or other material following wafer or module microfabrication. The tape holds the pieces of the s ...
)
**
Wafer backgrinding and polishing (reduces the thickness of the wafer for thin devices like a
smartcard
A smart card, chip card, or integrated circuit card (ICC or IC card) is a physical electronic authentication device, used to control access to a resource. It is typically a plastic credit card-sized card with an embedded integrated circuit (IC) c ...
or
PCMCIA card
In computing, PC Card is a configuration for computer parallel communication peripheral interface, designed for laptop computers. Originally introduced as PCMCIA, the PC Card standard as well as its successors like CardBus were defined and develop ...
or wafer bonding and stacking, this can also occur during wafer dicing, in a process known as Dice Before Grind or DBG)
**
Wafer bonding
Wafer bonding is a packaging technology on wafer-level for the fabrication of microelectromechanical systems (MEMS), nanoelectromechanical systems (NEMS), microelectronics and optoelectronics, ensuring a mechanically stable and hermetically sealed ...
and stacking (For
Three-dimensional integrated circuit
A three-dimensional integrated circuit (3D IC) is a MOS (metal-oxide semiconductor) integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or ...
s and
MEMS
Microelectromechanical systems (MEMS), also written as micro-electro-mechanical systems (or microelectronic and microelectromechanical systems) and the related micromechatronics and microsystems constitute the technology of microscopic devices, ...
)
**
Redistribution layer
A redistribution layer (RDL) is an extra metal layer on an integrated circuit that makes its IO pads available in other locations of the chip, for better access to the pads where necessary.
When an integrated circuit is manufactured, it usually h ...
manufacture (for
WLCSP
A chip scale package or chip-scale package (CSP) is a type of integrated circuit package.
Originally, CSP was the acronym for ''chip-size packaging.'' Since only a few packages are chip size, the meaning of the acronym was adapted to ''chip-sca ...
packages)
** Wafer Bumping (For
Flip chip
Flip chip, also known as controlled collapse chip connection or its abbreviation, C4, is a method for interconnecting dies such as semiconductor devices, IC chips, integrated passive devices and microelectromechanical systems (MEMS), to exter ...
BGA (
Ball grid array
A ball grid array (BGA) is a type of surface-mount packaging (a chip carrier) used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be pu ...
), and WLCSP packages)
** Die cutting or
Wafer dicing
In the context of manufacturing integrated circuits, wafer dicing is the process by which die are separated from a wafer of semiconductor following the processing of the wafer. The dicing process can involve scribing and breaking, mechanical sa ...
*
IC packaging
**
Die attachment (The die is attached to a leadframe using conductive paste or die attach film)
** IC bonding:
Wire bonding
Wire bonding is the method of making interconnections between an integrated circuit (IC) or other semiconductor device and its packaging during semiconductor device fabrication. Although less common, wire bonding can be used to connect an IC ...
,
Thermosonic bonding
Thermosonic bonding is widely used to wire bond silicon integrated circuits into computers. Alexander Coucoulas was named "Father of Thermosonic Bonding" by George Harman, the world's foremost authority on wire bonding, where he referenced Coucoul ...
,
Flip chip
Flip chip, also known as controlled collapse chip connection or its abbreviation, C4, is a method for interconnecting dies such as semiconductor devices, IC chips, integrated passive devices and microelectromechanical systems (MEMS), to exter ...
or
Tape Automated Bonding
Tape-automated bonding (TAB) is a process that places bare semiconductor chips (dies) like integrated circuits onto a flexible circuit board (FPC) by attaching them to fine conductors in a polyamide or polyimide (like trade names Kapton or UPILE ...
(TAB)
**
IC encapsulation or integrated heat spreader (IHS) installation
*** Molding (using special Molding compound that may contain glass powder as filler)
*** Baking
***
Electroplating (plates the
copper
Copper is a chemical element with the symbol Cu (from la, cuprum) and atomic number 29. It is a soft, malleable, and ductile metal with very high thermal and electrical conductivity. A freshly exposed surface of pure copper has a pinkis ...
leads of the
lead frame
A lead frame (pronounced ) is the metal structure inside a chip package that carries signals from the die to the outside.
The lead frame consists of a central die pad, where the die is placed, surrounded by leads, metal conductors leading away ...
s with
tin
Tin is a chemical element with the symbol Sn (from la, stannum) and atomic number 50. Tin is a silvery-coloured metal.
Tin is soft enough to be cut with little force and a bar of tin can be bent by hand with little effort. When bent, t ...
to make
soldering
Soldering (; ) is a process in which two or more items are joined by melting and putting a filler metal (solder) into the joint, the filler metal having a lower melting point than the adjoining metal. Unlike welding, soldering does not involv ...
easier)
*** Laser marking or silkscreen printing
*** Trim and form (separates the lead frames from each other, and bends the lead frame's pins so that they can be mounted on a
Printed circuit board)
*
IC testing
Additionally steps such as
Wright etch
The Wright etch (also Wright-Jenkins etch) is a preferential etch for revealing defects in - and -oriented, p- and n-type silicon wafers used for making transistors, microprocessors, memories, and other components. Revealing, identifying, and remed ...
may be carried out.
Prevention of contamination and defects
When feature widths were far greater than about 10
micrometre
The micrometre ( international spelling as used by the International Bureau of Weights and Measures; SI symbol: μm) or micrometer (American spelling), also commonly known as a micron, is a unit of length in the International System of Unit ...
s, semiconductor purity was not as big of an issue as it is today in device manufacturing. As devices become more integrated,
cleanroom
A cleanroom or clean room is an engineered space, which maintains a very low concentration of airborne particulates. It is well isolated, well-controlled from contamination, and actively cleansed. Such rooms are commonly needed for scientif ...
s must become even cleaner. Today, fabrication plants are
pressurized
{{Wiktionary
Pressurization or pressurisation is the application of pressure in a given situation or environment.
Industrial
Industrial equipment is often maintained at pressures above or below atmospheric.
Atmospheric
This is the process by ...
with filtered air to remove even the smallest particles, which could come to rest on the wafers and contribute to defects. The ceilings of semiconductor cleanrooms have
fan filter unit
A fan filter unit (FFU) is a type of motorized air filtering equipment. It is used to supply purified air to cleanrooms, laboratories, medical facilities or microenvironments by removing harmful airborne particles from recirculating air. The units ...
s (FFUs) at regular intervals to constantly replace and filter the air in the cleanroom; semiconductor capital equipment may also have their own FFUs. The FFUs, combined with raised floors with grills, help ensure a laminar air flow, to ensure that particles are immediately brought down to the floor and do not stay suspended in the air due to turbulence. The workers in a semiconductor fabrication facility are required to wear
cleanroom suit
A cleanroom suit, clean room suit, or bunny suit, is an overall garment worn in a cleanroom, an environment with a controlled level of contamination. One common type is an all-in-one coverall worn by semiconductor and nanotechnology line product ...
s to protect the devices from human
contamination
Contamination is the presence of a constituent, impurity, or some other undesirable element that spoils, corrupts, infects, makes unfit, or makes inferior a material, physical body, natural environment, workplace, etc.
Types of contamination
...
. To prevent oxidation and to increase yield, FOUPs and semiconductor capital equipment may have a hermetically sealed pure nitrogen environment with ISO class 1 level of dust.
FOUP
FOUP is an acronym for Front Opening Unified Pod or Front Opening Universal Pod.
It is a specialised plastic enclosure designed to hold silicon wafers
A wafer is a crisp, often sweet, very thin, flat, light and dry biscuit, often used to deco ...
s and
SMIF pods isolate the wafers from the air in the cleanroom, increasing yield because they reduce the number of defects caused by dust particles. Also, fabs have as few people as possible in the cleanroom to make maintaining the cleanroom environment easier, since people, even when wearing cleanroom suits, shed large amounts of particles, especially when walking.
Wafers
A typical
wafer
A wafer is a crisp, often sweet, very thin, flat, light and dry biscuit, often used to decorate ice cream, and also used as a garnish on some sweet dishes. Wafers can also be made into cookies with cream flavoring sandwiched between them. They ...
is made out of extremely
pure silicon that is
grown into
mono-crystalline cylindrical
ingot
An ingot is a piece of relatively pure material, usually metal, that is cast into a shape suitable for further processing. In steelmaking, it is the first step among semi-finished casting products. Ingots usually require a second procedure of sha ...
s (
boules) up to 300 mm (slightly less than 12 inches) in diameter using the
Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polished to obtain a very regular and flat surface.
Processing
In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.
* ''Deposition'' is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include
physical vapor deposition
Physical vapor deposition (PVD), sometimes called physical vapor transport (PVT), describes a variety of vacuum deposition methods which can be used to produce thin films and coatings on substrates including metals, ceramics, glass, and polym ...
(PVD),
chemical vapor deposition (CVD),
electrochemical deposition (ECD),
molecular beam epitaxy
Molecular-beam epitaxy (MBE) is an epitaxy method for thin-film deposition of single crystals. MBE is widely used in the manufacture of semiconductor devices, including transistors, and it is considered one of the fundamental tools for the devel ...
(MBE), and more recently,
atomic layer deposition (ALD) among others. Deposition can be understood to include
oxide layer formation, by
thermal oxidation
In microfabrication, thermal oxidation is a way to produce a thin layer of oxide (usually silicon dioxide) on the surface of a wafer. The technique forces an oxidizing agent to diffuse into the wafer at high temperature and react with it. The ra ...
or, more specifically,
LOCOS
LOCOS, short for LOCal Oxidation of Silicon, is a microfabrication process where silicon dioxide is formed in selected areas on a silicon wafer having the Si-SiO2 interface at a lower point than the rest of the silicon surface. As of 2008 it was ...
.
* ''Removal'' is any process that removes material from the wafer; examples include etch processes (either
wet or
dry) and
chemical-mechanical planarization (CMP).
* ''Patterning'' is the shaping or altering of deposited materials, and is generally referred to as
lithography
Lithography () is a planographic method of printing originally based on the immiscibility of oil and water. The printing is from a stone (lithographic limestone) or a metal plate with a smooth surface. It was invented in 1796 by the German a ...
. For example, in conventional lithography, the wafer is coated with a chemical called a ''
photoresist
A photoresist (also known simply as a resist) is a light-sensitive material used in several processes, such as photolithography and photoengraving, to form a patterned coating on a surface. This process is crucial in the electronic industry.
...
''; then, a machine called a ''
stepper'' focuses, aligns, and moves a
mask
A mask is an object normally worn on the face, typically for protection, disguise, performance, or entertainment and often they have been employed for rituals and rights. Masks have been used since antiquity for both ceremonial and pra ...
, exposing select portions of the wafer below to short-wavelength light; the exposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed by "dry"
plasma ashing
In semiconductor manufacturing plasma ashing is the process of removing the photoresist (light sensitive coating) from an etched wafer. Using a plasma source, a monatomic (single atom) substance known as a reactive species is generated. Oxygen o ...
(photoresist stripping or strip). The photoresist may also be removed using wet chemical processes that coat the wafer in a liquid to remove the photoresist.
* ''Modification of electrical properties'' has historically entailed
doping transistor ''sources'' and ''drains'' (originally by diffusion furnaces and later by
ion implantation
Ion implantation is a low-temperature process by which ions of one element are accelerated into a solid target, thereby changing the physical, chemical, or electrical properties of the target. Ion implantation is used in semiconductor device fa ...
). These doping processes are followed by
furnace anneal
Furnace annealing is a process used in semiconductor device fabrication which consist of heating multiple semiconductor wafers in order to affect their electrical properties. Heat treatments are designed for different effects. Wafers can be heated ...
ing or, in advanced devices, by
rapid thermal anneal
Rapid thermal processing (RTP) is a semiconductor manufacturing process which heats silicon wafers to temperatures exceeding 1,000°C for not more than a few seconds. During cooling wafer temperatures must be brought down slowly to prevent disloc ...
ing (RTA); annealing serves to activate the implanted dopants. Modification of electrical properties now also extends to the reduction of a material's
dielectric constant in
low-k insulators via exposure to
ultraviolet light
Ultraviolet (UV) is a form of electromagnetic radiation with wavelength from 10 nanometer, nm (with a corresponding frequency around 30 Hertz, PHz) to 400 nm (750 Hertz, THz), shorter than that of visible light, but longer than ...
in UV processing (UVP). Modification is frequently achieved by
oxidation
Redox (reduction–oxidation, , ) is a type of chemical reaction in which the oxidation states of substrate change. Oxidation is the loss of electrons or an increase in the oxidation state, while reduction is the gain of electrons or a ...
, which can be carried out to create semiconductor-insulator junctions, such as in the local oxidation of
silicon
Silicon is a chemical element with the symbol Si and atomic number 14. It is a hard, brittle crystalline solid with a blue-grey metallic luster, and is a tetravalent metalloid and semiconductor. It is a member of group 14 in the periodic ta ...
(
LOCOS
LOCOS, short for LOCal Oxidation of Silicon, is a microfabrication process where silicon dioxide is formed in selected areas on a silicon wafer having the Si-SiO2 interface at a lower point than the rest of the silicon surface. As of 2008 it was ...
) to fabricate
metal oxide field effect transistors.
Modern chips have up to eleven or more metal levels produced in over 300 or more sequenced processing steps.
Front-end-of-line (FEOL) processing
FEOL processing refers to the formation of the
transistor
upright=1.4, gate (G), body (B), source (S) and drain (D) terminals. The gate is separated from the body by an insulating layer (pink).
A transistor is a semiconductor device used to Electronic amplifier, amplify or electronic switch, switch ...
s directly in the
silicon
Silicon is a chemical element with the symbol Si and atomic number 14. It is a hard, brittle crystalline solid with a blue-grey metallic luster, and is a tetravalent metalloid and semiconductor. It is a member of group 14 in the periodic ta ...
. The raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer through
epitaxy. In the most advanced
logic devices, ''prior'' to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a ''straining step'' wherein a silicon variant such as
silicon-germanium (SiGe) is deposited. Once the epitaxial silicon is deposited, the
crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called ''
silicon on insulator'' technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of transistors with reduced
parasitic effects.
Gate oxide and implants
Front-end surface engineering is followed by growth of the
gate dielectric
A gate dielectric is a dielectric used between the gate and substrate of a field-effect transistor (such as a MOSFET). In state-of-the-art processes, the gate dielectric is subject to many constraints, including:
* Electrically clean interface to ...
(traditionally
silicon dioxide
Silicon dioxide, also known as silica, is an oxide of silicon with the chemical formula , most commonly found in nature as quartz and in various living organisms. In many parts of the world, silica is the major constituent of sand. Silica is one ...
), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties. In
dynamic random-access memory (DRAM) devices, storage
capacitors are also fabricated at this time, typically stacked above the access transistor (the now defunct DRAM manufacturer
Qimonda
Qimonda AG ( ) was a German memory company split out of Infineon Technologies (itself a spun off business unit of Siemens AG) on 1 May 2006 to form at the time the second largest DRAM company worldwide, according to the industry research firm ...
implemented these capacitors with trenches etched deep into the silicon surface).
Back-end-of-line (BEOL) processing
Metal layers
Once the various semiconductor devices have been
created, they must be interconnected to form the desired electrical circuits. This occurs in a series of wafer processing steps collectively referred to as BEOL (not to be confused with ''back end'' of chip fabrication, which refers to the packaging and testing stages). BEOL processing involves creating metal interconnecting wires that are isolated by dielectric layers. The insulating material has traditionally been a form of SiO
2 or a
silicate glass
Glass is a non-crystalline, often transparent, amorphous solid that has widespread practical, technological, and decorative use in, for example, window panes, tableware, and optics. Glass is most often formed by rapid cooling (quenching) of ...
, but recently new
low dielectric constant materials are being used (such as silicon oxycarbide), typically providing dielectric constants around 2.7 (compared to 3.82 for SiO
2), although materials with constants as low as 2.2 are being offered to chipmakers.
High-κ dielectric The term high-κ dielectric refers to a material with a high dielectric constant (κ, kappa), as compared to silicon dioxide. High-κ dielectrics are used in semiconductor manufacturing processes where they are usually used to replace a silicon di ...
s may instead be used.
Interconnect
Historically, the metal wires have been composed
of aluminum. In this approach to wiring (often called ''subtractive aluminum''), blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires. Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes (called "''vias")'' in the insulating material and then depositing
tungsten
Tungsten, or wolfram, is a chemical element with the symbol W and atomic number 74. Tungsten is a rare metal found naturally on Earth almost exclusively as compounds with other elements. It was identified as a new element in 1781 and first isol ...
in them with a
CVD technique using
tungsten hexafluoride; this approach is still used in the fabrication of many memory chips such as
dynamic random-access memory (DRAM), because the number of interconnect levels is small (currently no more than four).
More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern
microprocessor
A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circ ...
, the timing delay in the wiring has become so significant as to prompt a change in wiring material (from aluminum to
copper interconnect layer) and a change in dielectric material (from silicon dioxides to newer
low-K insulators). This performance enhancement also comes at a reduced cost via
damascene processing, which eliminates processing steps. As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked, extending outside the depth of focus of available lithography, and thus interfering with the ability to pattern. CMP (
chemical-mechanical planarization) is the primary processing method to achieve such planarization, although dry ''etch back'' is still sometimes employed when the number of interconnect levels is no more than three. Copper interconnects use an electrically conductive barrier layer to prevent the copper from diffusing into ("poisoning") its surroundings.
Wafer test
The highly serialized nature of wafer processing has increased the demand for
metrology in between the various processing steps. For example, thin film metrology based on
ellipsometry
Ellipsometry is an optical technique for investigating the dielectric properties (complex refractive index or dielectric function) of thin films. Ellipsometry measures the change of polarization upon reflection or transmission and compares it t ...
or
reflectometry
Reflectometry uses the reflection of waves at surfaces and interfaces to detect or characterize objects.
There are many different forms of reflectometry. They can be classified in several ways: by the used radiation (electromagnetic, ultrasound, ...
is used to tightly control the thickness of gate oxide, as well as the thickness,
refractive index, and extinction coefficient of photoresist and other coatings.
Wafer test metrology equipment is used to verify that the wafers haven't been damaged by previous processing steps up until testing; if too many
dies on one wafer have failed, the entire wafer is scrapped to avoid the costs of further processing.
Virtual metrology has been used to predict wafer properties based on statistical methods without performing the physical measurement itself.
[Neurotechnology Group, Berlin Institute of Technology, IEEE Xplore Digital Library. ]
Regression Methods for Virtual Metrology of Layer Thickness in Chemical Vapor Deposition
.” January 17, 2014. Retrieved November 9, 2015.
Device test
Once the front-end process has been completed, the semiconductor devices or chips are subjected to a variety of electrical tests to determine if they function properly. The percent of devices on the wafer found to perform properly is referred to as the yield. Manufacturers are typically secretive about their yields, but it can be as low as 30%, meaning that only 30% of the chips on the wafer work as intended.
Process variation
Natural process variation, sometimes just called process variation, is the statistical description of natural fluctuations in process outputs.
Equations
The following equations are used for an ''x''-bar-control chart:
:\bar x = \sum_^n x_i/ ...
is one among many reasons for low yield. Testing is carried out to prevent faulty chips from being assembled into relatively expensive packages.
The yield is often but not necessarily related to device (die or chip) size. As an example, In December 2019, TSMC announced an average yield of ~80%, with a peak yield per wafer of >90% for their
5nm
In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the 5 nm process as the MOSFET technology node following the 7 nm node. In 2020, Samsung and TSMC entered volume production of 5 nm chips ...
test chips with a
die size of 17.92 mm
2. The yield went down to 32.0% with an increase in die size to 100 mm
2.
The fab
tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. Currently, electronic dye marking is possible if wafer test data (results) are logged into a central computer database and chips are "binned" (i.e. sorted into virtual bins) according to predetermined test limits such as maximum operating frequencies/clocks, number of working (fully functional) cores per chip, etc. The resulting binning data can be graphed, or logged, on a wafer map to trace manufacturing defects and mark bad chips. This map can also be used during wafer assembly and packaging. Binning allows chips that would otherwise be rejected to be reused in lower-tier products, as is the case with GPUs and CPUs, increasing device yield, especially since very few chips are fully functional (have all cores functioning correctly, for example).
eFUSE
In computing, an eFuse (electronic fuse) is a microscopic fuse put into a computer chip. This technology was invented by IBM in 2004 to allow for the dynamic real-time reprogramming of chips. In the abstract, computer logic is generally "etched ...
s may be used to disconnect parts of chips such as cores, either because they didn't work as intended during binning, or as part of market segmentation (using the same chip for low, mid and high-end tiers). Chips may have spare parts to allow the chip to fully pass testing even if it has several non-working parts.
Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as the "final test". Chips may also be imaged using x-rays.
Usually, the fab charges for testing time, with prices in the order of cents per second. Testing times vary from a few milliseconds to a couple of seconds, and the test software is optimized for reduced testing time. Multiple chip (multi-site) testing is also possible because many testers have the resources to perform most or all of the tests in parallel and on several chips at once.
Chips are often designed with "testability features" such as
scan chain
Scan chain is a technique used in design for testing. The objective is to make testing easier by providing a simple way to set and observe every flip-flop in an IC.The basic structure of scan include the following set of signals in order to con ...
s or a "
built-in self-test
A built-in self-test (BIST) or built-in test (BIT) is a mechanism that permits a machine to test itself. Engineers design BISTs to meet requirements such as:
*high reliability
*lower repair cycle times
or constraints such as:
*limited technic ...
" to speed testing and reduce testing costs. In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during testing, in order to achieve tightly distributed resistance values as specified by the design.
Good designs try to test and statistically manage ''
corners'' (extremes of silicon behavior caused by a high
operating temperature combined with the extremes of fab processing steps). Most designs cope with at least 64 corners.
Device yield
Device yield or die yield is the number of working chips or dies on a wafer, given in percentage since the number of chips on a wafer (Die per wafer, DPW) can vary depending on the chips' size and the wafer's diameter. Yield degradation is a reduction in yield, which historically was mainly caused by dust particles, however since the 1990s, yield degradation is mainly caused by process variation, the process itself and by the tools used in chip manufacturing, although dust still remains a problem in many older fabs. Dust particles have an increasing effect on yield as feature sizes are shrunk with newer processes. Automation and the use of mini environments inside of production equipment, FOUPs and SMIFs have enabled a reduction in defects caused by dust particles. Device yield must be kept high to reduce the selling price of the working chips since working chips have to pay for those chips that failed, and to reduce the cost of wafer processing. Yield can also be affected by the design and operation of the fab.
Tight control over contaminants and the production process are necessary to increase yield. Contaminants may be chemical contaminants or be dust particles. "Killer defects" are those caused by dust particles that cause complete failure of the device (such as a transistor). There are also harmless defects. A particle needs to be 1/5 the size of a feature to cause a killer defect. So if a feature is 100 nm across, a particle only needs to be 20 nm across to cause a killer defect. Electrostatic electricity can also affect yield adversely. Chemical contaminants or impurities include heavy metals such as iron, copper, nickel, zinc, chromium, gold, mercury and silver, alkali metals such as sodium, potassium and lithium, and elements such as aluminum, magnesium, calcium, chlorine, sulfur, carbon, and fluorine. It is important for these elements to not remain in contact with the silicon, as they could reduce yield. Chemical mixtures may be used to remove these elements from the silicon; different mixtures are effective against different elements.
Several models are used to estimate yield. They are Murphy's model, Poisson's model, the binomial model, Moore's model and Seeds' model. There is no universal model; a model has to be chosen based on actual yield distribution (the location of defective chips) For example, Murphy's model assumes that yield loss occurs more at the edges of the wafer (non-working chips are concentrated on the edges of the wafer), Poisson's model assumes that defective dies are spread relatively evenly across the wafer, and Seeds's model assumes that defective dies are clustered together.
Smaller dies cost less to produce (since more fit on a wafer, and wafers are processed and priced as a whole), and can help achieve higher yields since smaller dies have a lower chance of having a defect, due to their lower surface area on the wafer. However, smaller dies require smaller features to achieve the same functions of larger dies or surpass them, and smaller features require reduced process variation and increased purity (reduced contamination) to maintain high yields. Metrology tools are used to inspect the wafers during the production process and predict yield, so wafers predicted to have too many defects may be scrapped to save on processing costs.
Die preparation
Once tested, a wafer is typically reduced in thickness in a process also known as "backlap", "backfinish" or "wafer thinning" before the wafer is scored and then broken into individual dies, a process known as
wafer dicing
In the context of manufacturing integrated circuits, wafer dicing is the process by which die are separated from a wafer of semiconductor following the processing of the wafer. The dicing process can involve scribing and breaking, mechanical sa ...
. Only the good, unmarked chips are packaged.
Packaging
Plastic or ceramic packaging involves mounting the die, connecting the die pads to the pins on the package, and sealing the die. Tiny
bondwires are used to connect the pads to the pins. In the 'old days' (1970s), wires were attached by hand, but now specialized machines perform the task. Traditionally, these wires have been composed of gold, leading to a
lead frame
A lead frame (pronounced ) is the metal structure inside a chip package that carries signals from the die to the outside.
The lead frame consists of a central die pad, where the die is placed, surrounded by leads, metal conductors leading away ...
(pronounced "leed frame") of
solder
Solder (; NA: ) is a fusible metal alloy used to create a permanent bond between metal workpieces. Solder is melted in order to wet the parts of the joint, where it adheres to and connects the pieces after cooling. Metals or alloys suitable ...
-plated copper;
lead
Lead is a chemical element with the symbol Pb (from the Latin ) and atomic number 82. It is a heavy metal that is denser than most common materials. Lead is soft and malleable, and also has a relatively low melting point. When freshly cu ...
is poisonous, so lead-free "lead frames" are now mandated by
RoHS
The Restriction of Hazardous Substances Directive 2002/95/EC (RoHS 1), short for Directive on the restriction of the use of certain hazardous substances in electrical and electronic equipment, was adopted in February 2003 by the European Unio ...
.
Chip scale package
A chip scale package or chip-scale package (CSP) is a type of integrated circuit package.
Originally, CSP was the acronym for ''chip-size packaging.'' Since only a few packages are chip size, the meaning of the acronym was adapted to ''chip-scal ...
(CSP) is another packaging technology. A plastic
dual in-line package, like most packages, is many times larger than the actual die hidden inside, whereas CSP chips are nearly the size of the die; a CSP can be constructed for each die ''before'' the wafer is diced.
The packaged chips are retested to ensure that they were not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. A laser then etches the chip's name and numbers on the package.
Hazardous materials
Many toxic materials are used in the fabrication process.
[CNET. ]
Why tech pollution's going global
.” April 25, 2002. Retrieved November 9, 2015. These include:
* poisonous elemental
dopants
A dopant, also called a doping agent, is a trace of impurity element that is introduced into a chemical material to alter its original electrical or optical properties. The amount of dopant necessary to cause changes is typically very low. When ...
, such as
arsenic
Arsenic is a chemical element with the symbol As and atomic number 33. Arsenic occurs in many minerals, usually in combination with sulfur and metals, but also as a pure elemental crystal. Arsenic is a metalloid. It has various allotropes, ...
,
antimony
Antimony is a chemical element with the symbol Sb (from la, stibium) and atomic number 51. A lustrous gray metalloid, it is found in nature mainly as the sulfide mineral stibnite (Sb2S3). Antimony compounds have been known since ancient t ...
, and
phosphorus
Phosphorus is a chemical element with the symbol P and atomic number 15. Elemental phosphorus exists in two major forms, white phosphorus and red phosphorus, but because it is highly reactive, phosphorus is never found as a free element on Ear ...
.
* poisonous compounds, such as
arsine
Arsine (IUPAC name: arsane) is an inorganic compound with the formula As H3. This flammable, pyrophoric, and highly toxic pnictogen hydride gas is one of the simplest compounds of arsenic. Despite its lethality, it finds some applications in ...
,
phosphine
Phosphine (IUPAC name: phosphane) is a colorless, flammable, highly toxic compound with the chemical formula , classed as a pnictogen hydride. Pure phosphine is odorless, but technical grade samples have a highly unpleasant odor like rotting ...
,
tungsten hexafluoride and
silane
Silane is an inorganic compound with chemical formula, . It is a colourless, pyrophoric, toxic gas with a sharp, repulsive smell, somewhat similar to that of acetic acid. Silane is of practical interest as a precursor to elemental silicon. Sila ...
.
* highly reactive liquids, such as
hydrogen peroxide
Hydrogen peroxide is a chemical compound with the formula . In its pure form, it is a very pale blue liquid that is slightly more viscous than water. It is used as an oxidizer, bleaching agent, and antiseptic, usually as a dilute solution (3% ...
, fuming
nitric acid
Nitric acid is the inorganic compound with the formula . It is a highly corrosive mineral acid. The compound is colorless, but older samples tend to be yellow cast due to decomposition into oxides of nitrogen. Most commercially available nitri ...
,
sulfuric acid, and
hydrofluoric acid.
It is vital that workers should not be directly exposed to these dangerous substances. The high degree of automation common in the IC fabrication industry helps to reduce the risks of exposure. Most fabrication facilities employ exhaust management systems, such as wet scrubbers, combustors, heated absorber cartridges, etc., to control the risk to workers and to the environment.
Timeline of commercial MOSFET nodes
See also
*
Deathnium
*
Glossary of microelectronics manufacturing terms
*
List of semiconductor scale examples
Listed are many semiconductor scale examples for various metal–oxide–semiconductor field-effect transistor (MOSFET, or MOS transistor) semiconductor manufacturing process nodes.
Timeline of MOSFET demonstrations
PMOS and NMOS
CMOS ...
*
MOSFET
**
CMOS
*
Multigate device
A multigate device, multi-gate MOSFET or multi-gate field-effect transistor (MuGFET) refers to a metal–oxide–semiconductor field-effect transistor (MOSFET) that has more than one gate on a single transistor. The multiple gates may be control ...
**
FinFET
A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, ...
*
Semiconductor industry
**
Foundry model
The foundry model is a microelectronics engineering and manufacturing business model consisting of a semiconductor fabrication plant, or foundry, and an integrated circuit design operation, each belonging to separate companies or subsidiaries.
...
**
Semiconductor equipment sales leaders by year
*
International Technology Roadmap for Semiconductors
The International Technology Roadmap for Semiconductors (ITRS) is a set of documents produced by a group of semiconductor industry experts. These experts are representative of the sponsoring organisations which include the Semiconductor Industry A ...
*
Semiconductor consolidation
Semiconductor consolidation is the trend of semiconductor companies collaborating in order to come to a practical synergy with the goal of being able to operate in a business model that can sustain profitability.
History
Since the rapid adoptio ...
*
Local oxidation of silicon (LOCOS)
*
List of integrated circuit manufacturers
The following is an incomplete list of notable integrated circuit (i.e. microchip) manufacturers. Some are in business, others are defunct and some are Fabless.
0–9
*3dfx Interactive (acquired by Nvidia in 2002)
A
*Achronix
*Actions Sem ...
*
List of semiconductor fabrication plants
This is a list of semiconductor fabrication plants. A semiconductor fabrication plant is where integrated circuits (ICs), also known as microchips, are manufactured. They are either operated by Integrated Device Manufacturers (IDMs) who design a ...
*
Microfabrication
Microfabrication is the process of fabricating miniature structures of micrometre scales and smaller. Historically, the earliest microfabrication processes were used for integrated circuit fabrication, also known as "semiconductor manufacturing" ...
*
Semiconductor Equipment and Materials International
SEMI is an industry association comprising companies involved in the electronics design and manufacturing supply chain. They provide equipment, materials and services for the manufacture of semiconductors, photovoltaic panels, LED and flat pa ...
(SEMI) — the semiconductor industry trade association
*
SEMI font for labels on wafers
*
Etch pit density
*
Passivation
*
Planar process
*
Transistor count
The transistor count is the number of transistors in an electronic device (typically on a single substrate or "chip"). It is the most common measure of integrated circuit complexity (although the majority of transistors in modern microprocessors ...
References
Further reading
* , section 14.2.
Wiki related to Chip Technology
External links
Semiconductor glossaryWafer heatingDesigning a Heated Chuck for Semiconductor Processing Equipment
{{DEFAULTSORT:Semiconductor Device Fabrication
Cleanroom technology
MOSFETs