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The following is a list of Intel Core i7 brand microprocessors. Introduced in 2008, the Core i7 line of microprocessors are intended to be used by high-end users.


Desktop processors


Nehalem microarchitecture (1st generation)


"Bloomfield" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Hyper-threading, Turbo Boost, Smart Cache. * FSB has been replaced with QPI. * Transistors: 731 million *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 263 mm * Steppings: C0, D0


"Lynnfield" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), TXT, Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, Smart Cache. * Core i7-875K features an unlocked multiplier and does not support Intel TXT and Intel VT-d. * FSB has been replaced with
DMI DMI may refer to: Organizations * Danish Meteorological Institute * Data Management Inc., a time-and-attendance software company * Dead Man Incorporated, a predominantly white prison-gang formed in Maryland * Development Media International, a ...
. *Moves the QPI link and PCI-Express controller onto the processor itself (eliminating the northbridge), using DMI to interface a single-component "chipset" (now called PCH) that serves traditional southbridge functions. * Transistors: 774 million *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 296 mm * Stepping: B1


Westmere microarchitecture (1st generation)


"Gulftown" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Hyper-threading, Turbo Boost, AES-NI, Smart Cache. * Core i7-980X, 990X, and 995X feature an unlocked multiplier. * FSB has been replaced with QPI. * Transistors: 1.17 billion *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 239 mm * Steppings: B1


Sandy Bridge microarchitecture (2nd generation)


"Sandy Bridge" (32 nm)

* Most models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), TXT, Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, AES-NI, Smart Cache, Intel Insider, vPro * Support for up to 4 DIMMS of DDR3-1333 memory. *S processors feature lower-than-normal TDP (65 W on 4-core models). *K processors have unlocked turbo multiplier but does not support Intel TXT, Intel VT-d and vPro. * Non-K processors will have limited turbo overclocking. * Transistors: 1.16 billionAnand Lal Shimpi (September 14, 2011)
"Counting Transistors: Why 1.16B and 995M Are Both Correct"
 *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 216 mm


"Sandy Bridge-E" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, AES-NI, Smart Cache. * Support for up to 8 DIMMS of DDR3-1600 memory. * Transistors: 1.27 (M1 stepping) or 2.27 (C1, C2 steppings) billion *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 294 (M1 stepping) or 435 (C1, C2 steppings) mm


Ivy Bridge microarchitecture (3rd generation)


"Ivy Bridge" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Hyper-threading, Turbo Boost 2.0, AES-NI, Smart Cache, Intel Insider * Support for up to 4 DIMMS of DDR3-1600 memory. * All models except the K processors additionally support Intel TXT, Intel VT-d and vPro. *S processors feature lower-than-normal TDP (65 W on 4-core models). *T processors are power optimized *K processors have unlocked turbo multiplier but do not support Intel TXT, Intel VT-d or vPro. Non-K processors will have limited turbo overclocking. * Transistors: 1.4 billion *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 160 mm


"Ivy Bridge-E" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost 2.0, AES-NI, Smart Cache. * Support for up to 8 DIMMS of DDR3-1866 memory. * Transistors: 1.86 billion *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 256.5 mm


Haswell microarchitecture (4th generation)


"Haswell-DT" (quad-core, 22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, F16C, ( BMI1)(Bit Manipulation Instructions1)+BMI2, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Hyper-threading, Turbo Boost 2.0, AES-NI, Smart Cache, Intel Insider * All models except the i7-4770K additionally supported Intel TSX-NI at launch, but support was disabled in later stepping and microcode updates, due to the incorrect implementation, that could not be solved by microcode without hurting performance or fixing it fully. * All models except the i7-4770K additionally support Intel VT-d * All models except the i7-4770K and i7-4790K additionally support vPro and TXT * Transistors: 1.4 billion *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 177 mm


"Haswell-H" (MCP, quad-core, 22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, F16C, ( BMI1)(Bit Manipulation Instructions1)+BMI2, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost 2.0, AES-NI, Smart Cache, Intel Insider. *i7-4770R does not support TSX, TXT and Vpro. * Core i7-4770R also contains "Crystalwell": 128 MB
eDRAM Embedded DRAM (eDRAM) is dynamic random-access memory (DRAM) integrated on the same die or multi-chip module (MCM) of an application-specific integrated circuit (ASIC) or microprocessor. eDRAM's cost-per-bit is higher when compared to equivalen ...
built at 22 nm acting as L4 cache * Transistors: 1.4 billion *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 264 mm + 84 mm


"Haswell-E" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost 2.0, AES-NI, Smart Cache. * Support for up to 8 DIMMS of DDR4-2133 memory. * Transistors: 2.60 billion *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 356 mm * i7-5820K has 28 PCI Express lanes; i7-5930K and i7-5960X have 40


Broadwell microarchitecture (5th generation)


"Broadwell-H" (quad-core, 14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, F16C, ( BMI1)(Bit Manipulation Instructions1)+BMI2, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost 2.0, AES-NI, Smart Cache, Intel Insider, Intel TSX-NI * All models also contain "Crystal Well": 128 MB
eDRAM Embedded DRAM (eDRAM) is dynamic random-access memory (DRAM) integrated on the same die or multi-chip module (MCM) of an application-specific integrated circuit (ASIC) or microprocessor. eDRAM's cost-per-bit is higher when compared to equivalen ...
acting as L4 cache * Transistors: *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 166mm * PCI Express lanes: 16


"Broadwell-E" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost 3.0, AES-NI, Smart Cache. * Does not support Intel TSX-NI (disabled using microcode update, due to the hardware bugs in most of the steppings). * Support for up to 8 DIMMS of DDR4-2400 memory. * Transistors: *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 247mm * i7-6800K has 28 PCI Express lanes; all others have 40


Skylake microarchitecture (6th generation)


"Skylake-S" (quad-core, 14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, F16C, BMI1 (Bit Manipulation Instructions 1) and BMI2, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost 2.0, AES-NI, Smart Cache, Intel Insider,
Intel SGX Intel Software Guard Extensions (SGX) is a set of security-related instruction codes that are built into some Intel central processing units (CPUs). They allow user-level and operating system code to define protected private regions of memory, c ...
, Intel MPX, Intel TSX-NI * Embedded models also support: Intel vPro, Intel TXT. * Transistors: *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 122.4 mm * PCI Express lanes: 16


"Skylake-H" (quad-core, 14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, F16C, ( BMI1)(Bit Manipulation Instructions1)+BMI2, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost 2.0, AES-NI, Smart Cache, Intel Insider, Intel vPro, Intel TXT,
Intel SGX Intel Software Guard Extensions (SGX) is a set of security-related instruction codes that are built into some Intel central processing units (CPUs). They allow user-level and operating system code to define protected private regions of memory, c ...
, Intel MPX, Intel TSX-NI. * Transistors: *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: * PCI Express lanes: 16


"Skylake-X" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, AVX-512, FMA3, SGX, MPX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading, AES-NI, Intel TSX-NI, Smart Cache. * PCI Express lanes: 28 (78xx), 44 (98xx)


Kaby Lake microarchitecture (7th generation)


"Kaby Lake-S" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, SGX, MPX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading, AES-NI, Intel TSX-NI, Intel vPro, Intel TXT, Smart Cache. * Low power models also support configurable TDP (cTDP) down. * K models do not support Intel vPro, Intel TXT. *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 126.15 mm * PCI Express lanes: 16


"Kaby Lake-X" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, SGX, MPX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading, AES-NI, Intel TSX-NI, Smart Cache. * PCI Express lanes: 16


Coffee Lake microarchitecture (8th/9th generation)


"Coffee Lake-S" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, SGX, MPX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading (8xxx only), AES-NI, Intel TSX-NI, Intel vPro (except 8086K), Intel TXT, Smart Cache. *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 151 mm (6 cores), 177 mm (8 cores) * PCI Express lanes: 16


Comet Lake microarchitecture (10th generation)


"Comet Lake-S" (14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, SGX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Turbo Boost 3.0, Hyper-threading, AES-NI, Smart Cache. * All models support up to DDR4-2933 memory. * Low power and K models also support configurable TDP (cTDP) down. * Overclocking: Unlocked multiplier on K and KF models.


Cypress Cove microarchitecture (11th generation)


"Rocket Lake-S" (14 nm)

* All models support: SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, AVX-512, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost 3.0, Intel TXT, AES-NI, Smart Cache, DL Boost. * All models support up to DDR4-3200 memory, and 20 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
4.0. * Low power and K models also support configurable TDP (cTDP) down. * Overclocking: Unlocked multiplier on K and KF models.


Golden Cove +

Gracemont Gracemont is a town in Caddo County, Oklahoma, United States. The population was 318 at the 2010 census. The town name is a portmanteau of Grace and Montgomery, the names of two friends of the first postmaster, Alice L. Bailey. Geography Gracemo ...
microarchitecture (12th generation)


" Alder Lake" (Intel 7)

* All models support: '' SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost 3.0 (2.0 for embedded), AES-NI, Smart Cache, Thread Director, DL Boost, GNA 3.0, and Optane ''memory. * All models support up to DDR5-4800 or DDR4-3200 memory, and 16 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
5.0 + 4 lanes of PCIe 4.0. * Overclocking: Unlocked multiplier on K and KF models.


Raptor Cove Golden Cove is a codename for a CPU microarchitecture developed by Intel and released in November 2021. It succeeds four microarchitectures: Sunny Cove, Skylake, Willow Cove, and Cypress Cove. It is fabricated using Intel's Intel 7 process no ...
+
Gracemont Gracemont is a town in Caddo County, Oklahoma, United States. The population was 318 at the 2010 census. The town name is a portmanteau of Grace and Montgomery, the names of two friends of the first postmaster, Alice L. Bailey. Geography Gracemo ...
microarchitecture (13th generation)


Raptor Lake (Intel 7)

* All models support: '' SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost 3.0, AES-NI, Smart Cache, Thread Director, DL Boost, ''and'' GNA 3.0. * All models support up to DDR5-5600 or DDR4-3200 memory, and 16 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
5.0 + 4 lanes of PCIe 4.0. * Overclocking: Unlocked multiplier on K and KF models.


Mobile processors


Nehalem microarchitecture (1st generation)


"Clarksfield" (45 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), TXT, Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, Smart Cache. * FSB has been replaced with
DMI DMI may refer to: Organizations * Danish Meteorological Institute * Data Management Inc., a time-and-attendance software company * Dead Man Incorporated, a predominantly white prison-gang formed in Maryland * Development Media International, a ...
. * Transistors: 774 million *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 296 mm * Steppings: B1 *XM models feature an unlocked multiplier, allowing them to be overclocked.


Westmere microarchitecture (1st generation)


"Arrandale" (MCP, 32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), TXT, Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, AES-NI, Smart Cache. * FSB has been replaced with
DMI DMI may refer to: Organizations * Danish Meteorological Institute * Data Management Inc., a time-and-attendance software company * Dead Man Incorporated, a predominantly white prison-gang formed in Maryland * Development Media International, a ...
. * Contains 45 nm "Ironlake" GPU. * CPU Transistors: 382 million * CPU
die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 81 mm * Graphics and Integrated Memory Controller transistors: 177 million * Graphics and integrated memory controller die size: 114 mm * Steppings: C2, K0 * Core i7-610E, i7-620UE, i7-620LE and i7-660UE have support for ECC memory and PCI express port bifurcation.


Sandy Bridge microarchitecture (2nd generation)


"Sandy Bridge (dual-core)" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), TXT, Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, AES-NI, Smart Cache. * Core i7-2620M, Core i7-2640M, Core i7-2637M, and Core i7-2677M support Intel Insider * Core i7-2610UE, Core i7-2655LE does not support XD bit (Execute Disable bit). * Core i7-2610UE, Core i7-2655LE has support for ECC memory * Transistors: 624 million *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 149 mm


"Sandy Bridge (quad-core)" (32 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), TXT, Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, AES-NI, Smart Cache, Intel Insider. * Core i7-2630QM, Core i7-2635QM, Core i7-2670QM, Core i7-2675QM do not support TXT and Intel VT-d. * Core i7-2715QE has support for ECC memory. * Core i7-2710QE, Core i7-2715QE do not support Intel Insider and XD bit.(Execute Disable bit). * Transistors: 1.16 billion *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 216 mm *XM models feature an unlocked multiplier, allowing them to be overclocked.


Ivy Bridge microarchitecture (3rd generation)


"Ivy Bridge (dual-core)" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), TXT, Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost2.0, AES-NI, Smart Cache, Intel Insider. * Core i7-3517U and i7-3537U do not support Intel TXT. * Core i7-3555LE and Core i7-3517UE do not support Intel Insider.


"Ivy Bridge (quad-core)" (22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), TXT, Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, AES-NI, Smart Cache, Intel Insider. * Core i7-3610QM, Core i7-3612QM and Core i7-3630QM (Socket G2) do not support Intel VT-d. * Core i7-3610QE, Core i7-3615QE and Core i7-3612QE do not support Intel Insider. * Transistors: 1.4 billion *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 160 mm *XM models feature an unlocked multiplier, allowing them to be overclocked.


Haswell microarchitecture (4th generation)


"Haswell-MB" (dual-core, 22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel TXT, Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, AES-NI, Intel vPro, Smart Cache * Transistors: 1.3 billion *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 181 mm


"Haswell-ULT" (SiP, dual-core, 22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Hyper-threading, Turbo Boost, AES-NI, Smart Cache * Core i7-4550U and higher also support Intel VT-d * Core i7-4600U and i7-4650U also support Intel vPro and Intel TXT * Transistors: 1.3 billion *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 181 mm


"Haswell-ULX" (SiP, dual-core, 22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Hyper-threading, Turbo Boost, AES-NI, Smart Cache, Intel VT-d, Intel vPro and Intel TXT * Transistors: 1.3 billion *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 181 mm


"Haswell-MB" (quad-core, 22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, F16C, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Hyper-threading, Turbo Boost, AES-NI, Smart Cache, and Intel Insider * Core i7-48xxMQ, i7-49xxMQ, and all MX models also support Intel TXT, Intel VT-d, and vPro. * Transistors: 1.4 billion *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 177 mm *MX models feature an unlocked multiplier, allowing them to be overclocked.


"Haswell-H" (MCP, quad-core, 22 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Intel TXT, Hyper-threading, Turbo Boost, AES-NI, Smart Cache, Intel Insider. * Core i7-48xxHQ, i7-49xxHQ, and all EQ models also support Intel vPro and Intel TSX-NI * Models with Iris Pro Graphics 5200 also contain "Crystalwell": 128 MB
eDRAM Embedded DRAM (eDRAM) is dynamic random-access memory (DRAM) integrated on the same die or multi-chip module (MCM) of an application-specific integrated circuit (ASIC) or microprocessor. eDRAM's cost-per-bit is higher when compared to equivalen ...
built at (22 nm) acting as L4 cache * Overclocking: i7-4950HQ comes with an unlocked multiplier, allowing users to set the multiplier value higher than shipped value, to facilitate better overclocking. * EQ models support ECC memory * Transistors: *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 264 mm + 84 mm


Broadwell microarchitecture (5th generation)


"Broadwell-H" (MCP, quad-core, 14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Intel TXT, Hyper-threading, Turbo Boost, AES-NI, Smart Cache, Intel Insider, and configurable TDP (cTDP) down (47W→37W). * Models with Iris Pro Graphics 6200 also contain "Crystalwell": 128 MB
eDRAM Embedded DRAM (eDRAM) is dynamic random-access memory (DRAM) integrated on the same die or multi-chip module (MCM) of an application-specific integrated circuit (ASIC) or microprocessor. eDRAM's cost-per-bit is higher when compared to equivalen ...
acting as L4 cache * EQ models also support Intel vPro, Intel TSX-NI, and ECC memory. * Transistors: *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size:


"Broadwell-U" (dual-core, 14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, AES-NI, Smart Cache, configurable TDP (cTDP) down * Core i7-5600U and higher also support Intel vPro, Intel TXT, and Intel TSX-NI * Transistors: 1.3–1.9 billion *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 82–133 mm


Skylake microarchitecture (6th generation)


"Skylake-H" (MCP, quad-core, 14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, AES-NI, Smart Cache, Intel Insider, and configurable TDP (cTDP) down (45W→35W). * Core i7-6820HQ, Core i7-6920HQ, and embedded models also support Intel vPro, Intel TXT. * Core i7-6820HK, Core i7-6820HQ, Core i7-6920HQ, and embedded models also support Intel TSX-NI. * Core i7-6820HK features an unlocked multiplier, allowing it to be overclocked. * Transistors: *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: 122 mm


"Skylake-U" (dual-core, 14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, AES-NI, Smart Cache, Intel TSX-NI, and configurable TDP (cTDP) down * Core i7-6600U and higher also support Intel vPro, Intel TXT. * Transistors: *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size:


Kaby Lake microarchitecture (7th/8th generation)


"Kaby Lake-H" (quad-core, 14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, SGX, MPX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading, AES-NI, Smart Cache, configurable TDP (cTDP) down. * i7-7800 and up also support Intel TSX-NI * i7-7820HQ, i7-7920HQ and embedded models also support Intel vPro, Intel TXT. *i7-7820HK features an unlocked multiplier, allowing it to be overclocked. * Transistors: TBD *
Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...
size: * Embedded models support ECC memory


"Kaby Lake-U" (dual-core, 14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, SGX, MPX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading, AES-NI, Smart Cache, and configurable TDP (cTDP).


"Kaby Lake-Y" (dual-core, 14 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, SGX, MPX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading, AES-NI, Smart Cache, Intel TSX-NI, Intel vPro, Intel TXT, and configurable TDP (cTDP).


"Kaby Lake Refresh" (quad-core, 14 nm)


"Kaby Lake-G" (quad-core, 14 nm)


"Amber Lake-Y" (dual-core, 14 nm)


Coffee Lake microarchitecture (8th/9th generation)


"Coffee Lake-U" (quad-core, 14 nm)


"Coffee Lake-H" (hexa-core, 14 nm)


"Coffee Lake-B" (hexa-core, 14 nm)


"Whiskey Lake-U" (quad-core, 14 nm)


"Amber Lake-Y" (quad-core, 14 nm)


Comet Lake microarchitecture (10th generation)


"Comet Lake-H" (14 nm)


"Comet Lake-U" (14 nm)

* i7-10610U, 10810U also support Intel vPro.


Sunny Cove microarchitecture (10th generation)


"Ice Lake-U" (quad-core, 10 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, AVX-512, FMA3, SGX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading, AES-NI, Smart Cache, DL Boost, and configurable TDP (cTDP).


"Ice Lake-Y" (quad-core, 10 nm)

* All models support: MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
, SSE3, SSSE3, SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, AVX-512, FMA3, SGX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading, AES-NI, Smart Cache, DL Boost, and configurable TDP (cTDP).


Willow Cove microarchitecture (11th generation)


"Tiger Lake-H" (10 nm SuperFin)

* All models support: SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX2, AVX-512, FMA3, Speed Shift Technology (SST), Intel 64, Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading, AES-NI, Smart Cache, DL Boost, Optane memory, GNA 2.0, IPU6, TB4, and configurable TDP (cTDP). * 11850H also supports Intel vPro, Intel TXT.


"Tiger Lake-B" (10 nm SuperFin)


"Tiger Lake-H35" (10 nm SuperFin)

* All models support: SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX2, AVX-512, FMA3, Speed Shift Technology (SST), Intel 64, Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading, AES-NI, Smart Cache, DL Boost, Optane memory, GNA 2.0, IPU6, TB4, and configurable TDP (cTDP).


"Tiger Lake-UP3" (10 nm SuperFin)

* All models support: SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX2, AVX-512, FMA3, Speed Shift Technology (SST), Intel 64, Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading, AES-NI, Smart Cache, DL Boost, Optane memory, GNA 2.0, IPU6 (except SRK02), TB4, and configurable TDP (cTDP). * 1185G7, 1185G7E and 1185GRE also support Intel vPro, Intel TXT. * -RE models support ECC memory.


"Tiger Lake-UP4" (10 nm SuperFin)

* All models support: SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX2, AVX-512, FMA3, Speed Shift Technology (SST), Intel 64, Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading, AES-NI, Smart Cache, DL Boost, Optane memory, GNA 2.0, IPU6, TB4, and configurable TDP (cTDP). * 1180 also supports Intel vPro, Intel TXT.


Golden Cove +

Gracemont Gracemont is a town in Caddo County, Oklahoma, United States. The population was 318 at the 2010 census. The town name is a portmanteau of Grace and Montgomery, the names of two friends of the first postmaster, Alice L. Bailey. Geography Gracemo ...
microarchitecture (12th generation)


" Alder Lake-HX" (Intel 7)

* All models support: '' SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, Speed Shift Technology (SST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost 3.0, AES-NI, Smart Cache, Thread Director, DL Boost, and GNA 3.0''. * All models support up to DDR5-4800 or DDR4-3200 memory, and 20 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
5.0/4.0. * 12850HX also supports '' Intel vPro, Intel TXT''


" Alder Lake-H" (Intel 7)

* All models support: '' SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, Speed Shift Technology (SST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost 3.0, AES-NI, Smart Cache, Thread Director, DL Boost, and GNA 3.0''. * All models support up to DDR5-4800, LPDDR5-5200, DDR4-3200, or LPDDR4X-4266 memory, and 28 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
4.0/3.0.


" Alder Lake-P" (Intel 7)

* All models support: '' SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, Speed Shift Technology (SST), Intel 64, Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, AES-NI, IPU6, TB4, Smart Cache, Thread Director, DL Boost, and GNA 3.0''. * All models support up to DDR5-4800, LPDDR5-5200, DDR4-3200, or LPDDR4X-4266 memory, and 20 lanes of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
4.0/3.0. * Model numbers 1270 and higher also support '' Intel vPro, Intel TXT, and XD bit''.


" Alder Lake-U" (Intel 7)

* All models support: '' SSE4.1,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, AVX, AVX2, FMA3, Speed Shift Technology (SST), Intel 64, Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, AES-NI, IPU6'' (except SRLFR)'', TB4, Smart Cache, Thread Director, DL Boost, and GNA 3.0''. * Support 20 lanes (UP3) or 14 lanes (UP4) of
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
4.0/3.0. * All models support up to LPDDR5-5200 or LPDDR4X-4266 memory * Standard power models also support up to DDR5-4800 or DDR4-3200 memory. * Model numbers 1260 and higher also support '' Intel vPro, Intel TXT, and XD bit''.


See also

* Intel Core * Comparison of Intel processors * List of Intel Celeron microprocessors * List of Intel Pentium microprocessors * List of Intel Core i3 microprocessors * List of Intel Core i5 microprocessors * List of Intel Core i9 microprocessors


Notes


References


External links


Intel Core i7 desktop processor product order code table




* ttp://www.intel.com/support/processors/mobile/corei7extreme/sb/CS-030874.htm Intel Core i7 mobile processor Extreme Edition product order code table
Search MDDS Database

Intel ARK Database








* ttps://web.archive.org/web/20141104224122/http://www.intc.com/pricelist.cfm Intel Corporation – Processor Price List
Intel CPU Transition Roadmap 2008–2013


{{DEFAULTSORT:List Of Intel Core i7 Microprocessors *Core i7 Intel Core i7