AMD Microprocessors
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The following is a list of AMD
CPU A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, and ...
microarchitecture In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular processor. A given ISA may be impl ...
s.


Nomenclature

Historically, AMD's CPU families were given a "K-number" (which originally stood for
Kryptonite Kryptonite is a fictional material that appears primarily in Superman stories published by DC Comics. In its best-known form, it is a green, crystalline material originating from Superman's home world of Krypton that emits a unique, poisonous r ...
, an allusion to the
Superman Superman is a superhero who appears in American comic books published by DC Comics. The character was created by writer Jerry Siegel and artist Joe Shuster, and debuted in the comic book ''Action Comics'' #1 (cover-dated June 1938 and publi ...
comic book character's fatal weakness) starting with their first internal x86 CPU design, the K5, to represent generational changes. AMD has not used K-nomenclature codenames in official AMD documents and press releases since the beginning of 2005, when ''K8'' described the
Athlon 64 The Athlon 64 is a ninth-generation, AMD64-architecture microprocessor produced by Advanced Micro Devices (AMD), released on September 23, 2003. It is the third processor to bear the name ''Athlon'', and the immediate successor to the Athlon XP. T ...
processor family. AMD now refers to the codename K8 processors as the ''Family 0Fh'' processors. 10h and 0Fh refer to the main result of the CPUID x86 processor instruction. In
hexadecimal In mathematics and computing, the hexadecimal (also base-16 or simply hex) numeral system is a positional numeral system that represents numbers using a radix (base) of 16. Unlike the decimal system representing numbers using 10 symbols, hexa ...
numbering, 0F(h) (where the ''h'' represents hexadecimal numbering) equals the
decimal The decimal numeral system (also called the base-ten positional numeral system and denary or decanary) is the standard system for denoting integer and non-integer numbers. It is the extension to non-integer numbers of the Hindu–Arabic numeral ...
number 15, and 10(h) equals the decimal number 16. (The "K10h" form that sometimes pops up is an improper hybrid of the "K" code and ''Family XXh'' identifier number.) The Family hexadecimal identifier number can be determined for a particular processor using the freeware system profiling application CPU-Z, which shows the Family number in the ''Ext. Family'' field of the application, as can be seen on various screenshots on th
CPU-Z Validator World Records
website.


x86 microarchitectures

Below is a list of microarchitectures many of which have codenames associated: * AMD K5 – AMD's first original x86 microarchitecture. The ''K5'' was based on the AMD Am29k micro architecture with the addition of an x86 decoder. Although the design was similar in idea to a Pentium Pro, the actual performance was more like that of a Pentium. * AMD K6 – the ''K6'' was not based on the ''K5'' and was instead based on the Nx686 processor that was being designed by
NexGen NexGen (Milpitas, California) was a private semiconductor company that designed x86 microprocessors until it was purchased by AMD in 1996. NexGen was a fabless design house that designed its chips but relied on other companies for production. N ...
when that company was bought by AMD. The ''K6'' was generally pin-compatible with the Intel Pentium (unlike NexGen's existing processors). ** AMD K6-2 – an improved ''K6'' with the addition of the
3DNow! 3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of float ...
SIMD instructions. ** AMD K6-III Sharptooth – a further improved ''K6'' with three levels of cache – 64 KB L1, 256 KB full-speed on-die L2, and a variable (up to 2 MB) L3. * AMD K7 Athlon – microarchitecture of the AMD Athlon classic and Athlon XP microprocessors. Was a very advanced design for its day. First generation was built with a separate L2-cache chip on a board inserted into a slot ( A) and introduced
extended MMX Extended MMX refers to one of two possible extensions to the MMX instruction set for x86. Intel Extended MMX Included in Intel's Streaming SIMD Extensions were a number of new instructions that extended the functionality of MMX. AMD incorporat ...
. The second generation returned to the traditional socket form factor with fully integrated L2-cache running at full speed. The third generation, branded as XP, introduced full support for SSE. * AMD K8 Hammer – also known as ''AMD Family 0Fh''. Based on the ''K7'' but was designed around a 64-bit ISA, added an integrated memory controller, HyperTransport communication fabric, L2 cache sizes up to 1  MB (1128 KB total cache), and
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
. Later ''K8'' added SSE3. The ''K8'' was the first mainstream Windows-compatible 64-bit microprocessor and was released April 22, 2003. ''K8'' replaced the traditional front-side bus with a HyperTransport communication fabric. ''SledgeHammer'' was the first design which implemented it. *
AMD K9 The AMD K9 represents a microarchitecture by AMD designed to replace the K8 processors, featuring dual-core processing. Development K9 appears originally to have been an ambitious 8 issue per clock cycle core redesign of the K7 or the K8 pr ...
– unfinished successor to K8. The codename was recycled at least once until ultimately being dropped before any public mention of it. * AMD Family 10h (K10) – based on the ''K8'' microarchitecture. Shared Level 3 Cache, 128-bit floating point units,
AMD-V Nested Paging Second Level Address Translation (SLAT), also known as nested paging, is a hardware-assisted virtualization technology which makes it possible to avoid the overhead associated with software-managed shadow page tables. AMD has supported SLAT through ...
virtualization, and HyperTransport 3.0 are introduced. ''Barcelona'' was the first design which implemented it. * AMD Family 11h – combined elements of ''K8'' and ''K10'' designs for
Turion X2 Ultra AMD Turion is the brand name AMD applies to its x86-64 low-power consumption (''mobile'') processors codenamed ''K8L''. The Turion 64 and Turion 64 X2/Ultra processors compete with Intel's mobile processors, initially the ''Pentium M'' and the Int ...
/ Puma mobile platform. * AMD Fusion Family 12h – based on the ''10h/K10'' design. Includes CPU cores, GPU and Northbridge in the same chip. ''Llano'' was the first design which implemented it. ''Fusion'' was later re-branded as the ''
APU APU or Apu may refer to: Film and television * ''The Apu Trilogy'', a series of three Bengali films, directed by Satyajit Ray, with the fictional character Apu Roy, comprising: ** ''Pather Panchali'' (''Song of the Little Road'') (1955), the first ...
''. * AMD Bobcat Family 14h – a new distinct line, which is aimed in the 1  W to 10 W low power microprocessor category. ''Ontario'' and ''Zacate'' were the first designs which implemented it. ** AMD Jaguar Family 16h – the successor to ''Bobcat''. ''Kabini'' and ''Temash''. CPUID model numbers are 00h-0Fh. ** AMD Puma Family 16h (2nd-gen) – the successor to ''Jaguar''. ''Beema'' and ''Mullins''. CPUID model numbers are 30h-3Fh. * AMD Bulldozer Family 15h – the successor to ''10h/K10''. ''Bulldozer'' is designed for processors in the 10 to 220  W category, implementing XOP, FMA4 and CVT16 instruction sets. ''Orochi'' was the first design which implemented it. For Bulldozer, CPUID model numbers are 00h and 01h. ** AMD Piledriver Family 15h (2nd-gen) – second generation ''Bulldozer'' (First optimisation). CPUID model numbers are 02h (earliest "Vishera" Piledrivers) and 10h-1Fh. ** AMD Steamroller Family 15h (3rd-gen) – third-generation ''Bulldozer'' (Second optimisation and die shrink to 28 nm). CPUID model numbers are 30h-3Fh. ** AMD Excavator Family 15h (4th-gen) – fourth-generation ''Bulldozer'' (Final optimisation). CPUID model numbers are 60h-6Fh, later updated revisions have model numbers 70h-7Fh. * AMD Zen Family 17h – the successor to ''Bulldozer''. First AMD architecture to implement simultaneous multithreading and Infinity Fabric. Based on
14 nm The 14 nm process refers to the MOSFET technology node that is the successor to the 22nm (or 20nm) node. The 14nm was so named by the International Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following 22nm was expe ...
process, included in the Ryzen CPU line. ** AMD Zen+ Family 17h – second generation ''Zen'' architecture (optimisation and die shrink to 12 nm). ** AMD Zen 2 Family 17h – successor to the ''Zen'' and ''Zen+'' architectures based on 7 nm process, first architecture designed around
chiplet A chiplet is a tiny integrated circuit (IC) that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an interposer in a single package. A set of chiplets can be implemented in a mix-and-match "LEGO ...
technology. ** AMD Zen 3 Family 19h – architecture in the optimised 7 nm process, successor to the ''Zen 2'' architecture. ** AMD Zen 3+ – 2022 revision of ''Zen 3'' used in Ryzen 6000 mobile processors using a 6 nm process. ** AMD Zen 4 Family 19h – successor to the ''Zen 3'' architecture, in 5 nm process. Used in
Ryzen 7000 Ryzen ( ) is a brand of multi-core x86-64 microprocessors designed and marketed by AMD for desktop, mobile, server, and embedded platforms based on the Zen microarchitecture. It consists of central processing units (CPUs) marketed for mainst ...
consumer processors on the new AM5 platform with DDR5 and PCIe 5.0 support. Adds support for AVX-512 instruction set. ** AMD Zen 5 – successor to the ''Zen 4'' architecture, planned in 3 nm.


Other microarchitectures

* AMD Am2900Bit-slice architecture designed in 1975. * AMD Am29000 – Popular line of 32-bit
RISC In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set comput ...
microprocessors and
microcontroller A microcontroller (MCU for ''microcontroller unit'', often also MC, UC, or μC) is a small computer on a single VLSI integrated circuit (IC) chip. A microcontroller contains one or more CPUs (processor cores) along with memory and programmable i ...
s. *
AMD K12 K12 was to be AMD's first custom microarchitecture based on the ARMv8-A (AArch64) instruction set with a planned release in 2017. Its predecessor, the Opteron A1100 series, also ARMv8-A, used ARM Cortex-A57 cores. the product still hasn't been re ...
ARM64/ARMv8-A


See also

* List of Intel CPU microarchitectures * List of AMD processors *
Table of AMD processors References See also * List of AMD microprocessors * List of AMD CPU microarchitectures * List of AMD mobile microprocessors * List of AMD Athlon microprocessors * List of AMD Athlon XP microprocessors * List of AMD Athlon 64 microprocesso ...
*
Transient execution CPU vulnerability Transient execution CPU vulnerabilities are vulnerabilities in a computer system in which a speculative execution optimization implemented in a microprocessor is exploited to leak secret data to an unauthorized party. The classic example is Spect ...


References


External links


AMD website
{{DEFAULTSORT:AMD CPU microarchitectures * Lists of microprocessors