A field-programmable gate array (FPGA) is an integrated circuit
designed to be configured by a customer or a designer after
manufacturing – hence "field-programmable". The FPGA
configuration is generally specified using a hardware description
language (HDL), similar to that used for an application-specific
integrated circuit (ASIC). (Circuit diagrams were previously used to
specify the configuration, as they were for ASICs, but this is
A Spartan FPGA from Xilinx
FPGAs contain an array of programmable logic blocks, and a hierarchy
of reconfigurable interconnects that allow the blocks to be "wired
together", like many logic gates that can be inter-wired in different
configurations. Logic blocks can be configured to perform complex
combinational functions, or merely simple logic gates like AND and
XOR. In most FPGAs, logic blocks also include memory elements, which
may be simple flip-flops or more complete blocks of memory.
1 Technical design
2.1 21st century developments
2.2.2 Market size
2.2.3 Design starts
3.1 Complex programmable logic devices (CPLD)
3.2 Security considerations
5.1 Logic blocks
5.2 Hard blocks
5.4 3D architectures
6 Design and programming
7 Basic process technology types
8 Major manufacturers
9 See also
11 Further reading
12 External links
Contemporary field-programmable gate arrays (FPGAs) have large
resources of logic gates and RAM blocks to implement complex digital
computations. As FPGA designs employ very fast I/O rates and
bidirectional data buses, it becomes a challenge to verify correct
timing of valid data within setup time and hold time. Floor planning
enables resource allocation within FPGAs to meet these time
constraints. FPGAs can be used to implement any logical function that
ASIC could perform. The ability to update the functionality after
shipping, partial re-configuration of a portion of the design and
the low non-recurring engineering costs relative to an
(notwithstanding the generally higher unit cost), offer advantages for
Some FPGAs have analog features in addition to digital functions. The
most common analog feature is a programmable slew rate on each output
pin, allowing the engineer to set low rates on lightly loaded pins
that would otherwise ring or couple unacceptably, and to set higher
rates on heavily loaded pins on high-speed channels that would
otherwise run too slowly. Also common are quartz-crystal
oscillators, on-chip resistance-capacitance oscillators, and
phase-locked loops with embedded voltage-controlled oscillators used
for clock generation and management and for high-speed
serializer-deserializer (SERDES) transmit clocks and receiver clock
recovery. Fairly common are differential comparators on input pins
designed to be connected to differential signaling channels. A few
"mixed signal FPGAs" have integrated peripheral analog-to-digital
converters (ADCs) and digital-to-analog converters (DACs) with analog
signal conditioning blocks allowing them to operate as a
system-on-a-chip. Such devices blur the line between an FPGA, which
carries digital ones and zeros on its internal programmable
interconnect fabric, and field-programmable analog array (FPAA), which
carries analog values on its internal programmable interconnect
The FPGA industry sprouted from programmable read-only memory (PROM)
and programmable logic devices (PLDs). PROMs and PLDs both had the
option of being programmed in batches in a factory or in the field
(field-programmable). However, programmable logic was hard-wired
between logic gates.
In the late 1980s, the
Naval Surface Warfare Center
Naval Surface Warfare Center funded an
experiment proposed by Steve Casselman to develop a computer that
would implement 600,000 reprogrammable gates. Casselman was successful
and a patent related to the system was issued in 1992.
Some of the industry's foundational concepts and technologies for
programmable logic arrays, gates, and logic blocks are founded in
patents awarded to David W. Page and LuVerne R. Peterson in
Altera was founded in 1983 and delivered the industry's first
reprogrammable logic device in 1984 – the EP300 – which featured a
quartz window in the package that allowed users to shine an
ultra-violet lamp on the die to erase the
EPROM cells that held the
Ross Freeman and
Bernard Vonderschmitt invented the
first commercially viable field-programmable gate array in
1985 – the XC2064.[not in citation given] The XC2064
had programmable gates and programmable interconnects between gates,
the beginnings of a new technology and market. The XC2064 had 64
configurable logic blocks (CLBs), with two three-input lookup tables
(LUTs). More than 20 years later, Freeman was entered into the
National Inventors Hall of Fame
National Inventors Hall of Fame for his invention.
Xilinx continued unchallenged and quickly grew from 1985 to
the mid-1990s, when competitors sprouted up, eroding significant
market share. By 1993,
Actel (now Microsemi) was serving about 18
percent of the market. By 2013,
Altera (31 percent),
Xilinx (36 percent) together represented approximately 77
percent of the FPGA market.
The 1990s were a period of rapid growth for FPGAs, both in circuit
sophistication and the volume of production. In the early 1990s, FPGAs
were primarily used in telecommunications and networking. By the end
of the decade, FPGAs found their way into consumer, automotive, and
21st century developments
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A recent[when?] trend has been to take the coarse-grained
architectural approach a step further by combining the logic blocks
and interconnects of traditional FPGAs with embedded microprocessors
and related peripherals to form a complete "system on a programmable
chip". This work mirrors the architecture created by Ron Perlof and
Hana Potash of Burroughs Advanced Systems Group in 1982 which combined
a reconfigurable CPU architecture on a single chip called the SB24.
Examples of such hybrid technologies can be found in the Xilinx
Zynq-7000 All Programmable SoC, which includes a 1.0 GHz
ARM Cortex-A9 MPCore processor embedded within the FPGA's
logic fabric or in the
Altera Arria V FPGA, which includes an
800 MHz dual-core
ARM Cortex-A9 MPCore. The
Atmel FPSLIC is
another such device, which uses an AVR processor in combination with
Atmel's programmable logic architecture. The
devices incorporate an ARM Cortex-M3 hard processor core (with up to
512 kB of flash and 64 kB of RAM) and analog peripherals
such as a multi-channel ADC and DACs to their flash-based FPGA fabric.
Xilinx Zynq-7000 All Programmable System on a Chip.
An alternate approach to using hard-macro processors is to make use of
soft processor cores that are implemented within the FPGA logic. Nios
Mico32 are examples of popular softcore processors.
Many modern FPGAs are programmed at "run time", and this is leading to
the idea of reconfigurable computing or reconfigurable
systems – CPUs that reconfigure themselves to suit the task at
hand. Additionally, new, non-FPGA architectures are beginning to
emerge. Software-configurable microprocessors such as the Stretch
S5000 adopt a hybrid approach by providing an array of processor cores
and FPGA-like programmable cores on the same chip.
Companies like Microsoft have started to use FPGA to accelerate
high-performance, computationally intensive systems (like the data
centers that operate their Bing search engine), due to the performance
per watt advantage FPGAs deliver.
1982: 8,192 gates, Burroughs Advances Systems Group, integrated into
the S-Type 24-bit processor for reprogrammable I/O.
1987: 9,000 gates, Xilinx
1992: 600,000, Naval Surface Warfare Department
Early 2000s: Millions
2013: 50 Million, Xilinx
1985: First commercial FPGA :
1987: $14 million
≈1993: >$385 million
2005: $1.9 billion
2010 estimates: $2.75 billion* 2013: $5.4 billion * 2020
estimate: $9.8 billion 
A design start is a new custom design for implementation on an FPGA.
Historically, FPGAs have been slower, less energy efficient and
generally achieved less functionality than their fixed ASIC
counterparts. An older study[when?] had shown that designs implemented
on FPGAs need on average 40 times as much area, draw 12 times as much
dynamic power, and run at one third the speed of corresponding ASIC
implementations. More recently, FPGAs such as the
Xilinx Virtex-7 or the
Stratix 5 have come to rival
ASIC and ASSP solutions by providing significantly
reduced power usage, increased speed, lower materials cost, minimal
implementation real-estate, and increased possibilities for
re-configuration 'on-the-fly'. Where previously a design may have
included 6 to 10 ASICs, the same design can now be achieved using only
Advantages of FPGAs include the ability to re-program in the field to
fix bugs, and may include a shorter time to market and lower
non-recurring engineering costs. Vendors can also take a middle road
by developing their hardware on ordinary FPGAs, but manufacture their
final version as an
ASIC so that it can no longer be modified after
the design has been committed.
Xilinx claims that several market and technology dynamics are changing
the ASIC/FPGA paradigm:
Integrated circuit development costs are rising aggressively
ASIC complexity has lengthened development time
R&D resources and headcount are decreasing
Revenue losses for slow time-to-market are increasing
Financial constraints in a poor economy are driving low-cost
These trends make FPGAs a better alternative than ASICs for a larger
number of higher-volume applications than they have been historically
used for, to which the company attributes the growing number of FPGA
design starts (see History).
Some FPGAs have the capability of partial re-configuration that lets
one portion of the device be re-programmed while other portions
Complex programmable logic devices (CPLD)
The primary differences between CPLDs (complex programmable logic
devices) and FPGAs are architectural. A
CPLD has a somewhat
restrictive structure consisting of one or more programmable
sum-of-products logic arrays feeding a relatively small number of
clocked registers. The result of this is less flexibility, with the
advantage of more predictable timing delays and a higher
logic-to-interconnect ratio. The FPGA architectures, on the other
hand, are dominated by interconnect. This makes them far more flexible
(in terms of the range of designs that are practical for
implementation within them) but also far more complex to design for.
In practice, the distinction between FPGAs and CPLDs is often one of
size as FPGAs are usually much larger in terms of resources than
CPLDs. Typically only FPGAs contain more complex embedded functions
such as adders, multipliers, memory, and serdes. Another common
distinction is that CPLDs contain embedded flash to store their
configuration while FPGAs usually, but not always, require external
With respect to security, FPGAs have both advantages and disadvantages
as compared to ASICs or secure microprocessors. FPGAs' flexibility
makes malicious modifications during fabrication a lower risk.
Previously, for many FPGAs, the design bitstream was exposed while the
FPGA loads it from external memory (typically on every power-on). All
major FPGA vendors now offer a spectrum of security solutions to
designers such as bitstream encryption and authentication. For
Xilinx offer AES (up to 256 bit) encryption for
bitstreams stored in an external flash memory.
FPGAs that store their configuration internally in nonvolatile flash
memory, such as Microsemi's ProAsic 3 or Lattice's XP2 programmable
devices, do not expose the bitstream and do not need encryption. In
addition, flash memory for a lookup table provides single event upset
protection for space applications.[clarification needed]. Customers
wanting a higher guarantee of tamper resistance can use write-once,
Antifuse FPGAs from vendors such as Microsemi.
Stratix 10 FPGAs and SoCs,
Altera introduced a Secure Device
Manager and physically uncloneable functions to provide high levels of
protection against physical attacks.
In 2012 researchers Sergei Skorobogatov and Christopher Woods
demonstrated that FPGAs can be vulnerable to hostile intent. They
discovered a critical backdoor vulnerability had been manufactured in
silicon as part of the Actel/
Microsemi ProAsic 3 making it vulnerable
on many levels such as reprogramming crypto and access keys, accessing
unencrypted bitstream, modifying low-level silicon features, and
extracting configuration data.
An FPGA can be used to solve any problem which is computable. This is
trivially proven by the fact FPGA can be used to implement a soft
microprocessor, such as the
Altera Nios II. Their
advantage lies in that they are sometimes significantly faster for
some applications because of their parallel nature and optimality in
terms of the number of gates used for a certain process.
FPGAs originally began as competitors to CPLDs to implement glue logic
for PCBs. As their size, capabilities, and speed increased, they took
over additional functions to the point where some are now marketed as
full systems on chips (SoC). Particularly with the introduction of
dedicated multipliers into FPGA architectures in the late 1990s,
applications which had traditionally been the sole reserve of DSPs
began to incorporate FPGAs instead.
Another trend in the use of FPGAs is hardware acceleration, where one
can use the FPGA to accelerate certain parts of an algorithm and share
part of the computation between the FPGA and a generic processor.
Traditionally, FPGAs have been reserved for specific vertical
applications where the volume of production is small. For these
low-volume applications, the premium that companies pay in hardware
cost per unit for a programmable chip is more affordable than the
development resources spent on creating an ASIC. Today, new cost and
performance dynamics have broadened the range of viable applications.
Common FPGA Applications:
Aerospace and Defense
Missiles & Munitions
Digital Signal Processing (DSP)
High Resolution Video
Vehicle Networking and Connectivity
Real-Time Video Engine
Switches and Routers
Hardware security module
Hardware security module 
High Performance Computing
High-end Beam Forming Systems
Data Mining Systems
Integrated Circuit Design
Computer Hardware Emulation
Hardware security module
Hardware security module 
Video & Image Processing
High Resolution Video
Video Over IP Gateway
Optical Transport Networks
Main article: Logic block
Simplified example illustration of a logic cell
The most common FPGA architecture consists of an array of logic
blocks (called configurable logic block, CLB, or logic array block,
LAB, depending on vendor), I/O pads, and routing channels. Generally,
all the routing channels have the same width (number of wires).
Multiple I/O pads may fit into the height of one row or the width of
one column in the array.
An application circuit must be mapped into an FPGA with adequate
resources. While the number of CLBs/LABs and I/Os required is easily
determined from the design, the number of routing tracks needed may
vary considerably even among designs with the same amount of logic.
For example, a crossbar switch requires much more routing than a
systolic array with the same gate count. Since unused routing tracks
increase the cost (and decrease the performance) of the part without
providing any benefit, FPGA manufacturers try to provide just enough
tracks so that most designs that will fit in terms of lookup tables
(LUTs) and I/Os can be routed. This is determined by estimates such as
those derived from
Rent's rule or by experiments with existing
In general, a logic block (CLB or LAB) consists of a few logical cells
(called ALM, LE, slice etc.). A typical cell consists of a 4-input
LUT[timeframe?], a full adder (FA) and a D-type flip-flop, as shown
below. The LUTs are in this figure split into two 3-input LUTs. In
normal mode those are combined into a 4-input LUT through the left
mux. In arithmetic mode, their outputs are fed to the FA. The
selection of mode is programmed into the middle multiplexer. The
output can be either synchronous or asynchronous, depending on the
programming of the mux to the right, in the figure example. In
practice, entire or parts of the FA are put as functions into the LUTs
in order to save space.
Modern FPGA families expand upon the above capabilities to include
higher level functionality fixed into the silicon. Having these common
functions embedded into the silicon reduces the area required and
gives those functions increased speed compared to building them from
primitives. Examples of these include multipliers, generic DSP blocks,
embedded processors, high speed I/O logic and embedded memories.
Higher-end FPGAs can contain high speed multi-gigabit transceivers and
hard IP cores such as processor cores,
Ethernet MACs, PCI/PCI Express
controllers, and external memory controllers. These cores exist
alongside the programmable fabric, but they are built out of
transistors instead of LUTs so they have
ASIC level performance and
power consumption while not consuming a significant amount of fabric
resources, leaving more of the fabric free for the
application-specific logic. The multi-gigabit transceivers also
contain high performance analog input and output circuitry along with
high-speed serializers and deserializers, components which cannot be
built out of LUTs. Higher-level PHY layer functionality such as line
coding may or may not be implemented alongside the serializers and
deserializers in hard logic, depending on the FPGA.
Most of the circuitry built inside of an FPGA is synchronous circuitry
that requires a clock signal. FPGAs contain dedicated global and
regional routing networks for clock and reset so they can be delivered
with minimal skew. Also, FPGAs generally contain analog
PLL and/or DLL
components to synthesize new clock frequencies as well as attenuate
jitter. Complex designs can use multiple clocks with different
frequency and phase relationships, each forming separate clock
domains. These clock signals can be generated locally by an oscillator
or they can be recovered from a high speed serial data stream. Care
must be taken when building clock domain crossing circuitry to avoid
metastability. FPGAs generally contain block RAMs that are capable of
working as dual port RAMs with different clocks, aiding in the
construction of building FIFOs and dual port buffers that connect
differing clock domains.
To shrink the size and power consumption of FPGAs, vendors such as
Xilinx have introduced 3D or stacked architectures.
Following the introduction of its 28 nm 7-series FPGAs, Xilinx
said that several of the highest-density parts in those FPGA product
lines will be constructed using multiple dies in one package,
employing technology developed for 3D construction and stacked-die
Xilinx's approach stacks several (three or four) active FPGA dies
side-by-side on a silicon interposer – a single piece of
silicon that carries passive interconnect. The multi-die
construction also allows different parts of the FPGA to be created
with different process technologies, as the process requirements are
different between the FPGA fabric itself and the very high speed 28
Gbit/s serial transceivers. An FPGA built in this way is called a
Altera's heterogeneous approach involves using a single monolithic
FPGA die and connecting other die/technologies to the FPGA using
Intel's embedded multi-die interconnect bridge (EMIB) technology.
Design and programming
To define the behavior of the FPGA, the user provides a design in a
hardware description language (HDL) or as a schematic design. The HDL
form is more suited to work with large structures because it's
possible to just specify them numerically rather than having to draw
every piece by hand. However, schematic entry can allow for easier
visualisation of a design.
Then, using an electronic design automation tool, a technology-mapped
netlist is generated. The netlist can then be fit to the actual FPGA
architecture using a process called place-and-route, usually performed
by the FPGA company's proprietary place-and-route software. The user
will validate the map, place and route results via timing analysis,
simulation, and other verification methodologies. Once the design and
validation process is complete, the binary file generated (also using
the FPGA company's proprietary software) is used to (re)configure the
FPGA. This file is transferred to the FPGA/
CPLD via a serial interface
(JTAG) or to an external memory device like an EEPROM.
The most common HDLs are
VHDL and Verilog, although in an attempt to
reduce the complexity of designing in HDLs, which have been compared
to the equivalent of assembly languages, there are moves[by whom?] to
raise the abstraction level through the introduction of alternative
languages. National Instruments'
LabVIEW graphical programming
language (sometimes referred to as "G") has an FPGA add-in module
available to target and program FPGA hardware.
To simplify the design of complex systems in FPGAs, there exist
libraries of predefined complex functions and circuits that have been
tested and optimized to speed up the design process. These predefined
circuits are commonly called IP cores, and are available from FPGA
vendors and third-party IP suppliers (rarely free, and typically
released under proprietary licenses). Other predefined circuits are
available from developer communities such as
released under free and open source licenses such as the GPL, BSD or
similar license), and other sources.
In a typical design flow, an FPGA application developer will simulate
the design at multiple stages throughout the design process. Initially
the RTL description in
Verilog is simulated by creating test
benches to simulate the system and observe results. Then, after the
synthesis engine has mapped the design to a netlist, the netlist is
translated to a gate level description where simulation is repeated to
confirm the synthesis proceeded without errors. Finally the design is
laid out in the FPGA at which point propagation delays can be added
and the simulation run again with these values back-annotated onto the
More recently, OpenCL is being used by programmers to take advantage
of the performance and power efficiencies that FPGAs provide. OpenCL
allows programmers to develop code in the C programming language and
target FPGA functions as OpenCL kernels using OpenCL constructs.
Basic process technology types
SRAM – based on static memory technology. In-system programmable and
re-programmable. Requires external boot devices. CMOS.
Currently[when?] in use. It is worth noting that flash or EEPROM
devices may often load contents into internal SRAM that controls
routing and logic.
Fuse – One-time programmable. Bipolar. Obsolete.
Antifuse – One-time programmable. CMOS.
PROM – Programmable Read-Only Memory technology. One-time
programmable because of plastic packaging. Obsolete.
EPROM – Erasable Programmable Read-Only Memory technology. One-time
programmable but with window, can be erased with ultraviolet (UV)
light. CMOS. Obsolete.
EPROM – Electrically Erasable Programmable Read-Only Memory
technology. Can be erased, even in plastic packages. Some but not all
EPROM devices can be in-system programmed. CMOS.
Flash – Flash-erase
EPROM technology. Can be erased, even in plastic
packages. Some but not all flash devices can be in-system programmed.
Usually, a flash cell is smaller than an equivalent E
EPROM cell and is
therefore less expensive to manufacture. CMOS.
In 2016, long-time industry rivals
Altera (now Intel) were
the FPGA market leaders. At that time, they controlled nearly 90
percent of the market.
Altera provide proprietary Windows and
software (ISE/Vivado and Quartus) which enables engineers to design,
analyse, simulate, and synthesize (compile) their designs.
Other manufacturers include:
Microsemi (previously Actel, antifuse, flash-based, mixed-signal)
Lattice Semiconductor (SRAM based with integrated configuration flash,
instant-on, low power, live reconfiguration)
SiliconBlue Technologies (extremely low power SRAM-based FPGAs with
optional integrated nonvolatile configuration memory; acquired by
Lattice in 2011)
QuickLogic (Ultra Low Power Sensor Hubs, extremely low powered,
low density SRAM-based FPGAs, Display bridges MIPI & RGB inputs,
MIPI, RGB and LVDS outputs)
Atmel (second source of some Altera-compatible devices; also FPSLIC
mentioned above; acquired by Microchip in 2016))
Achronix (SRAM based, 1.5 GHz fabric speed),
In March 2010, Tabula announced their FPGA technology that uses
time-multiplexed logic and interconnect that claims potential cost
savings for high-density applications. On March 24, 2015, Tabula
officially shut down.
On June 1, 2015,
Intel announced it would acquire
approximately $16.7 billion and completed the acquisition on December
List of HDL simulators
VHDL (Very High Speed Integrated Circuit) Hardware Description
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microprogram control units for programmable devices. Zielona Góra:
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2007. Retrieved 2013-07-11.
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22, 2001. Retrieved February 10, 2009.
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revolutionary 65nm FPGA architecture: the Virtex-5 family. May 15,
2006. Retrieved February 5, 2009.
^ Press Release, "
Ross Freeman Honored as 2009
National Inventors Hall of Fame
National Inventors Hall of Fame Inductee for Invention of FPGA"
^ US 4870302, Freeman, Ross H., "Configurable electrical circuit
having configurable logic elements and configurable interconnects",
published 19 February 1988, issued 26 September 1989
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^ a b Maxfield, Clive (2004). The Design Warrior's Guide to FPGAs:
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^ "Microsoft Supercharges Bing Search With Programmable Chips". WIRED.
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^ Maxfield, Max. "
Xilinx UltraScale FPGA Offers 50 Million Equivalent
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Markets Clean Bill of Health". June 13, 2005. Retrieved February 5,
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and ASICs". Proceedings of the international symposium on Field
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Design Platform: Fulfilling the Programmable Imperative Archived
2009-02-06 at the Wayback Machine.." February 2, 2009. Retrieved
February 2, 2009
^ Huffmire Paper "Managing Security in FPGA-Based Embedded Systems."
Nov-Dec 2008. Retrieved Sept 22, 2009
^ "EETimes on PUF: Security features for non-security experts –
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^ "Breakthrough Silicon Scanning Discovers Backdoor in Military Chip".
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FPGA Center, tutorials and examples
What is an FPGA? on YouTube
Bipolar junction transistor
Bipolar junction transistor (BJT)
Field-effect transistor (FET)
Constant-current diode (CLD, CRD)
Heterostructure barrier varactor
Insulated-gate bipolar transistor
Insulated-gate bipolar transistor (IGBT)
Integrated circuit (IC)
Light-emitting diode (LED)
Silicon controlled rectifier
Silicon controlled rectifier (SCR)
Unijunction transistor (UJT)
Pentagrid (Hexode, Heptode, Octode)
Vacuum tubes (RF)
Backward-wave oscillator (BWO)
Crossed-field amplifier (CFA)
Inductive output tube
Inductive output tube (IOT)
Traveling-wave tube (TWT)
Cathode ray tubes
Beam deflection tube
Magic eye tube
Video camera tube
audio and video
DO-204 (DO-7 / DO-35 / DO-41)
DO-214 (SMA / SMB / SMC)
SOD (SOD-123 / SOD-323 / SOD-523 / SOD-923)
SOT / TSOT
TO-3 (TH / Panel)
TO-66 (TH / Panel)
TO-126 (TH / Panel)
TO-220 (TH / Panel)
TO-247 (TH / Panel)
TO-251 (IPAK) (SMT)
TO-252 (DPAK) (SMT)
TO-262 (I2PAK) (SMT)
TO-263 (D2PAK) (SMT)
TO-273 (Super-220) (SMT)
TO-274 (Super-247) (SMT)
SIP / SIL
DIP / DIL
SO / SOIC
SOP / SSOP
TSOP / TSSOP
QUIP / QUIL
WL-CSP / WLP
Integrated circuit packaging
List of integrated circuit packaging types
Printed circuit board
Note: It's relatively common to find packages that contain other
components than their designated ones, such as diodes or voltage
regulators in transistor packages, etc.
Integrated circuit (IC)
Digital signal (electronics)
Logic in computer science
Digital signal (signal processing)
Digital signal processing
Switching circuit theory
Formal equivalence checking
C to HDL
Flow to HDL