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OpenCores
OpenCores is a community developing digital open-source hardware through electronic design automation (EDA), with a similar ethos as the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies have been reported as adopting OpenCores IP in chips,Andrew Orlowski, "Flextronics demos open source chips", ''The Register'', 12 December 2003/ref> or as adjuncts to EDA tools. OpenCores is also cited from time to time in the electronics press as an example of open source in the electronics hardware community. OpenCores has always been a commercially owned organization. In 2015, the core active users of OpenCores established the independent Free and Open Source Silicon Foundation (FOSSi Foundation), and registered the libreCores.org website as the basis for all future development, independent of commercial control. History Damjan Lampret, one of the founders of OpenCores, stated on his website that it began in 1999. Th ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
OpenCores Logo
OpenCores is a community developing Digital data, digital open-source hardware through electronic design automation (EDA), with a similar ethos as the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies have been reported as adopting OpenCores IP in chips,Andrew Orlowski, "Flextronics demos open source chips", ''The Register'', 12 December 2003/ref> or as adjuncts to EDA tools. OpenCores is also cited from time to time in the electronics press as an example of open source in the electronics hardware community. OpenCores has always been a commercially owned organization. In 2015, the core active users of OpenCores established the independent Free and Open Source Silicon Foundation (FOSSi Foundation), and registered the libreCores.org website as the basis for all future development, independent of commercial control. History Damjan Lampret, one of the founders of OpenCores, stated on his website that it bega ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
OpenRISC
OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community. The first (and only) architectural description is for the OpenRISC 1000 ("OR1k"), describing a family of 32-bit and 64-bit processors with optional floating-point arithmetic and vector processing support. The OpenRISC 1200 implementation of this specification was designed by Damjan Lampret in 2000, written in the Verilog hardware description language (HDL). The later mor1kx implementation, which has some advantages compared to the OR 1200, was designed by Julius Baxter and is also written in Verilog. Additionally software simulators exist, which implement the OR1k specification. The hardware design was released under the GNU Lesser General Public License (LGPL), while t ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Open-source Hardware
Open-source hardware (OSH) consists of physical artifacts of technology designed and offered by the open-design movement. Both free and open-source software (FOSS) and open-source hardware are created by this open-source culture movement and apply a like concept to a variety of components. It is sometimes, thus, referred to as FOSH (free and open-source hardware). The term usually means that information about the hardware is easily discerned so that others can make it – coupling it closely to the maker movement. Hardware design (i.e. mechanical drawings, schematics, bills of material, PCB layout data, HDL source code and integrated circuit layout data), in addition to the software that drives the hardware, are all released under free/libre terms. The original sharer gains feedback and potentially improvements on the design from the FOSH community. There is now significant evidence that such sharing can drive a high return on investment for the scientific community. It is n ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Free And Open Source Silicon Foundation
The Free and Open Source Silicon Foundation (FOSSi Foundation) is a non-profit foundation with the mission to promote and assist free and open digital hardware designs and their related ecosystems. It was set up by the core OpenRISC development team in response to decreasing support from the commercial owners of the OpenCores, opencores.org website. The main sponsor of the FOSSi Foundation is Google and past sponsors included Cadence Design Systems and Embecosm. The FOSSi Foundation should not be confused with the Free Silicon Foundation. The FOSSi Foundation operates as an open, inclusive, vendor-independent group. It identifies its mission as the following activities: * support and promote open standards development and their use; * support community events and organize regular events; * encourage industry participation in open source IP design; * assist hobbyists and academic institutions with opening their work to the public; and * support the development and maintenance of a ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Semiconductor Intellectual Property Core
In electronic design, a semiconductor intellectual property core (SIP core), IP core, or IP block is a reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of one party. IP cores can be licensed to another party or owned and used by a single party. The term comes from the licensing of the patent or source code copyright that exists in the design. Designers of application-specific integrated circuits (ASIC) and systems of field-programmable gate array (FPGA) logic can use IP cores as building blocks. History The licensing and use of IP cores in chip design came into common practice in the 1990s. There were many licensors and also many foundries competing on the market. In 2013, the most widely licensed IP cores are from Arm Holdings (43.2% market share), Synopsys Inc. (13.9% market share), Imagination Technologies (9% market share) and Cadence Design Systems (5.1% market share). Types of IP cores The use of an IP core in chip ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Wishbone (computer Bus)
The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip. The Wishbone Bus is used by many designs in the OpenCores project. Wishbone is intended as a "logic bus". It does not specify electrical information or the bus topology. Instead, the specification is written in terms of "signals", clock cycles, and high and low levels. This ambiguity is intentional. Wishbone is made to let designers combine several designs written in Verilog, VHDL or some other logic-description language for electronic design automation (EDA). Wishbone provides a standard way for designers to combine these hardware logic designs (called "cores"). Wishbone is defined to have 8, 16, 32, and 64-bit buses. All signals are synchronous to a single clock but some slave responses must be generated combinatorially for maximum performance. Wishbone per ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Field-programmable Gate Array
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturinghence the term '' field-programmable''. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools. FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects allowing blocks to be wired together. Logic blocks can be configured to perform complex combinational functions, or act as simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. Many FPGAs can be reprogrammed to implement different logic functions, allowing flexible reconfigur ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Application-specific Integrated Circuit
An application-specific integrated circuit (ASIC ) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficiency video codec. Application-specific standard product (ASSP) chips are intermediate between ASICs and industry standard integrated circuits like the 7400 series or the 4000 series. ASIC chips are typically fabricated using metal-oxide-semiconductor (MOS) technology, as MOS integrated circuit chips. As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 logic gates to over 100 million. Modern ASICs often include entire microprocessors, memory blocks including ROM, RAM, EEPROM, flash memory and other large building blocks. Such an ASIC is often termed a SoC (system-on-chip). Designers of digital ASICs often use a hardware descrip ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Amber (processor Core)
The Amber processor core is an ARM architecture-compatible 32-bit reduced instruction set computing (RISC) processor. It is Open-source software, open source, hosted on the OpenCores website, and is part of a movement to develop a library of open source hardware projects. Overview The Amber core is fully compatible with the ARMv2a instruction set and is thus supported by the GNU toolchain. This older version of the ARM instruction set is supported because it is not covered by patents, and so can be implemented with no license from ARM Holdings, unlike some prior open source projects (e.g.nnARM. The cores were developed in Verilog 2001 and are optimized for field-programmable gate array (FPGA) synthesis. For example, there is no reset logic: all registers are reset as part of FPGA initialization. The Amber project provides a complete embedded field-programmable gate array (FPGA) system incorporating the Amber core and several peripherals, including universal asynchronous receiver/tr ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Software License
A software license is a legal instrument (usually by way of contract law, with or without printed material) governing the use or redistribution of software. Under United States copyright law, all software is copyright protected, in both source code and object code forms, unless that software was developed by the United States Government, in which case it cannot be copyrighted. Authors of copyrighted software can donate their software to the public domain, in which case it is also not covered by copyright and, as a result, cannot be licensed. A typical software license grants the licensee, typically an end-user, permission to use one or more copies of software in ways where such a use would otherwise potentially constitute copyright infringement of the software owner's exclusive rights under copyright. Software licenses and copyright law Most distributed software can be categorized according to its license type (see table). Two common categories for software under copyright ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
EE Times
''EE Times'' (''Electronic Engineering Times'') is an electronics industry magazine published in the United States since 1972. EE Times is currently owned by AspenCore, a division of Arrow Electronics since August 2016. Since its acquisition by AspenCore, EE Times has seen major editorial and publishing technology investment and a renewed emphasis on investigative coverage. New features include The Dispatch, which profiles frontline engineers and unpacks the real-life design problems and their solutions in technical yet conversational reporting. Ownership and status ''EE Times'' was launched in 1972 by Gerard G. Leeds of CMP Publications Inc. In 1999, the Leeds family sold CMP to United Business Media for $900 million. After 2000, ''EE Times'' moved more into web publishing. The shift in advertising from print to online began to accelerate in 2007 and the periodical shed staff to adjust to the downturn in revenue. In July 2013, the digital edition migrated to UBM TechWeb's ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
RISC
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions (more code) in order to accomplish a task because the individual instructions are written in simpler code. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an instruction pipeline, which may be simpler given simpler instructions. The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). The RISC computer usually has many (16 or 32) high-speed, general-purpose registers with a load/store architecture in which the code for the register-register instructions (for performing arithmetic and tests) are separate fr ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
