SSE4 (Streaming SIMD Extensions 4) is a
SIMD CPU
instruction set used in the
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 ser ...
Core microarchitecture and
AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006
Intel Developer Forum, with vague details in a
white paper
A white paper is a report or guide that informs readers concisely about a complex issue and presents the issuing body's philosophy on the matter. It is meant to help readers understand an issue, solve a problem, or make a decision. A white paper ...
; more precise details of 47 instructions became available at the Spring 2007 Intel Developer Forum in
Beijing
}
Beijing ( ; ; ), Chinese postal romanization, alternatively romanized as Peking ( ), is the Capital city, capital of the China, People's Republic of China. It is the center of power and development of the country. Beijing is the world's Li ...
, in the presentation. SSE4 is fully compatible with software written for previous generations of Intel 64 and IA-32 architecture microprocessors. All existing software continues to run correctly without modification on microprocessors that incorporate SSE4, as well as in the presence of existing and new applications that incorporate SSE4.
SSE4 subsets
Intel SSE4 consists of 54 instructions. A subset consisting of 47 instructions, referred to as ''SSE4.1'' in some Intel documentation, is available in
Penryn. Additionally, ''SSE4.2'', a second subset consisting of the 7 remaining instructions, is first available in
Nehalem-based
Core i7. Intel credits feedback from developers as playing an important role in the development of the instruction set.
Starting with
Barcelona
Barcelona ( , , ) is a city on the coast of northeastern Spain. It is the capital and largest city of the autonomous community of Catalonia, as well as the second most populous municipality of Spain. With a population of 1.6 million within c ...
-based processors,
AMD introduced the ''SSE4a'' instruction set, which has 4 SSE4 instructions and 4 new SSE instructions. These instructions are not found in Intel's processors supporting SSE4.1 and AMD processors only started supporting Intel's SSE4.1 and SSE4.2 (the full SSE4 instruction set) in the
Bulldozer-based FX processors. With SSE4a the misaligned SSE feature was also introduced which meant unaligned load instructions were as fast as aligned versions on aligned addresses. It also allowed disabling the alignment check on non-load SSE operations accessing memory. Intel later introduced similar speed improvements to unaligned SSE in their Nehalem processors, but did not introduce misaligned access by non-load SSE instructions until
AVX.
Name confusion
What is now known as
SSSE3 (Supplemental Streaming
SIMD Extensions 3), introduced in the
Intel Core 2 processor line, was referred to as SSE4 by some media until Intel came up with the SSSE3 moniker. Internally dubbed Merom New Instructions, Intel originally did not plan to assign a special name to them, which was criticized by some journalists.
[My Experience With "Conroe"](_blank)
, DailyTech Intel eventually cleared up the confusion and reserved the SSE4 name for their next instruction set extension.
[ tp://download.intel.com/technology/architecture/new-instructions-paper.pdf Extending the World’s Most Popular Processor Architecture, Intel]
Intel is using the marketing term ''HD Boost'' to refer to SSE4.
New instructions
Unlike all previous iterations of SSE, SSE4 contains instructions that execute operations which are not specific to multimedia applications. It features a number of instructions whose action is determined by a constant field and a set of instructions that take XMM0 as an implicit third operand.
Several of these instructions are enabled by the single-cycle shuffle engine in Penryn. (Shuffle operations reorder bytes within a register.)
SSE4.1
These instructions were introduced with
Penryn microarchitecture, the 45 nm shrink of Intel's
Core microarchitecture. Support is indicated via the CPUID.01H:ECX.SSE41
it 19
It or IT may refer to:
* It (pronoun), in English
* Information technology
Arts and media Film and television
* ''It'' (1927 film), a film starring Clara Bow
* ''It! The Terror from Beyond Space'', a 1958 science fiction film
* ''It!'' (1967 f ...
flag.
SSE4.2
SSE4.2 added STTNI (String and Text New Instructions), several new instructions that perform character searches and comparison on two operands of 16 bytes at a time. These were designed (among other things) to speed up the parsing of
XML
Extensible Markup Language (XML) is a markup language and file format for storing, transmitting, and reconstructing arbitrary data. It defines a set of rules for encoding documents in a format that is both human-readable and machine-readable. T ...
documents. It also added a CRC32 instruction to compute
cyclic redundancy checks as used in certain data transfer protocols. These instructions were first implemented in the
Nehalem-based
Intel Core i7 product line and complete the SSE4 instruction set. Support is indicated via the CPUID.01H:ECX.SSE42
it 20flag.
POPCNT and LZCNT
These instructions operate on integer rather than SSE registers, because they are not SIMD instructions, but appear at the same time and although introduced by AMD with the SSE4a instruction set, they are counted as separate extensions with their own dedicated CPUID bits to indicate support. Intel implements POPCNT beginning with the
Nehalem microarchitecture and LZCNT beginning with the
Haswell microarchitecture. AMD implements both beginning with the
Barcelona microarchitecture.
AMD calls this pair of instructions
''Advanced Bit Manipulation'' (ABM).
The encoding of ''lzcnt'' is similar enough to ''bsr'' (bit scan reverse) that if ''lzcnt'' is performed on a CPU not supporting it such as Intel CPU's prior to Haswell, it will perform the ''bsr'' operation instead of raising an invalid instruction error despite the different result values of ''lzcnt'' and ''bsr''.
Trailing zeros can be counted using the ''bsf'' (bit scan forward) or ''tzcnt'' instructions.
SSE4a
The SSE4a instruction group was introduced in AMD's
Barcelona microarchitecture. These instructions are not available in Intel processors. Support is indicated via the CPUID.80000001H:ECX.SSE4A
it 6flag.
Supporting CPUs
*
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 ser ...
**
Silvermont processors (SSE4.1, SSE4.2 and POPCNT supported)
**
Goldmont processors (SSE4.1, SSE4.2 and POPCNT supported)
**
Goldmont Plus processors (SSE4.1, SSE4.2 and POPCNT supported)
**
Tremont processors (SSE4.1, SSE4.2 and POPCNT supported)
**
Penryn processors (SSE4.1 supported, except
Pentium Dual-Core and
Celeron
Celeron is Intel's brand name for low-end IA-32 and x86-64 computer microprocessor models targeted at low-cost personal computers.
Celeron processors are compatible with IA-32 software. They typically offer less performance per clock speed co ...
)
**
Nehalem processors and
Westmere processors (SSE4.1, SSE4.2 and POPCNT supported, except
Pentium and
Celeron
Celeron is Intel's brand name for low-end IA-32 and x86-64 computer microprocessor models targeted at low-cost personal computers.
Celeron processors are compatible with IA-32 software. They typically offer less performance per clock speed co ...
)
**
Sandy Bridge processors and newer (SSE4.1, SSE4.2 and POPCNT supported, include
Pentium and
Celeron
Celeron is Intel's brand name for low-end IA-32 and x86-64 computer microprocessor models targeted at low-cost personal computers.
Celeron processors are compatible with IA-32 software. They typically offer less performance per clock speed co ...
)
**
Haswell processors and newer (SSE4.1, SSE4.2, POPCNT and LZCNT supported)
*
AMD
**
K10-based processors (SSE4a, POPCNT and LZCNT supported)
** "Cat" low-power processors
***
Bobcat-based processors (SSE4a, POPCNT and LZCNT supported)
***
Jaguar-based processors and newer (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)
***
Puma-based processors and newer (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)
** "Heavy Equipment" processors (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)
***
Bulldozer-based processors
***
Piledriver-based processors
***
Steamroller-based processors
***
Excavator-based processors and newer
**
Zen-based processors (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)
**
Zen+-based processors (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)
**
Zen2-based processors (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)
**
Zen3-based processors (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)
*
VIA
Via or VIA may refer to the following:
Science and technology
* MOS Technology 6522, Versatile Interface Adapter
* ''Via'' (moth), a genus of moths in the family Noctuidae
* Via (electronics), a through-connection
* VIA Technologies, a Taiwa ...
**
Nano 3000, X2, QuadCore processors (SSE4.1 supported)
**
Nano QuadCore C4000-series processors (SSE4.1, SSE4.2 supported)
**
Eden X4 processors (SSE4.1, SSE4.2 supported)
*
Zhaoxin
** ZX-C processors and newer (SSE4.1, SSE4.2 supported)
References
External links
SSE4 Programming Referenceby Intel
archived a
Ghostarchive.orgat May 10, 2022
{{Multimedia extensions
X86 instructions
SIMD computing