The Puma Family 16h is a low-power
microarchitecture
In electronics, computer science and computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as μarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular ...
by
AMD
Advanced Micro Devices, Inc. (AMD) is an American multinational corporation and technology company headquartered in Santa Clara, California and maintains significant operations in Austin, Texas. AMD is a hardware and fabless company that de ...
for its
APUs
Apus is a small constellation in the Southern Celestial Hemisphere, southern sky. It represents a bird-of-paradise, and its name means "without feet" in Greek language, Greek because the bird-of-paradise was once wrongly believed to lack feet. ...
. It succeeds the
Jaguar
The jaguar (''Panthera onca'') is a large felidae, cat species and the only extant taxon, living member of the genus ''Panthera'' that is native to the Americas. With a body length of up to and a weight of up to , it is the biggest cat spe ...
as a second-generation version, targets the same market, and belongs to the same AMD architecture Family 16h. The ''Beema'' line of processors are aimed at low-power notebooks, and ''Mullins'' are targeting the tablet sector.
Design
The Puma cores use the same microarchitecture as Jaguar, and inherits the design:
*
Out-of-order execution
In computer engineering, out-of-order execution (or more formally dynamic execution) is an instruction scheduling paradigm used in high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In t ...
and
Speculative execution
Speculative execution is an optimization (computer science), optimization technique where a computer system performs some task that may not be needed. Work is done before it is known whether it is actually needed, so as to prevent a delay that woul ...
, up to 4 CPU cores
* Two-way integer execution
* Two-way 128-bit wide floating-point and packed integer execution
* Integer hardware divider
* Puma does not feature
clustered multi-thread (CMT), meaning that there are no "modules"
* Puma does not feature
Heterogeneous System Architecture
Heterogeneous System Architecture (HSA) is a cross-vendor set of specifications that allow for the integration of central processing units and graphics processors on the same bus, with shared memory and tasks. The HSA is being developed by the HS ...
or
zero-copy
In computer science, zero-copy refers to techniques that enable data transfer between memory spaces without requiring the CPU to copy the data. By avoiding redundant copying, zero-copy methods minimize CPU usage and memory bandwidth, leading ...
* 32 KiB instruction + 32 KiB data L1
cache
Cache, caching, or caché may refer to:
Science and technology
* Cache (computing), a technique used in computer storage for easier data access
* Cache (biology) or hoarding, a food storing behavior of animals
* Cache (archaeology), artifacts p ...
per core
* 1–2 MiB unified L2 cache shared by two or four cores
* Integrated single channel
memory controller
A memory controller, also known as memory chip controller (MCC) or a memory controller unit (MCU), is a digital circuit that manages the flow of data going to and from a computer's main memory. When a memory controller is integrated into anothe ...
supporting 64bit
DDR3L
* 3.1 mm
2 area per core
Instruction set support
Like Jaguar, the ''Puma'' core has support for the following instruction sets and instructions:
MMX,
SSE,
SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. SSE2 instructions allow the use of ...
,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
History
SSSE3 was first introduced with Intel processors based on the Core microarchitect ...
,
SSE4a
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; , SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT,
ABM (POPCNT/LZCNT), and
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware- ...
.
Improvements over ''Jaguar''
* 19% CPU core
leakage reduction at 1.2V
* 38% GPU leakage reduction
* 500 mW reduction in memory controller power
* 200 mW reduction in display interface power
* Chassis temperature aware turbo boost
* Selective boosting according to application needs (intelligent boost)
* Support for ARM
TrustZone via integrated
Cortex-A5 processor
* Support for
DDR3L-1866 memory
Puma+
AMD released a revision of the Puma microarchitecture, Puma+, which is integrated into the Carrizo-L APU platform.
Features
APU features table
Processors
Desktop/Mobile (Beema)
Tablet (Mullins)
References
External links
Software Optimization Guide for Family 16h Processors2014 AMD Low-Power Mobile APUs
Jaguar presentation (video)at
ISSCC 2013
Discussion initiated on RWT forums by Jeff Rupley, Chief Architect of the Jaguar coreBKDG for Family 16h Models 00h-0Fh ProcessorsRevision Guide for Family 16h Models 00h-0Fh Processors(Jaguar)
Revision Guide for Family 16h Models 30h-3Fh Processors(Puma)
{{Single-board computer
AMD x86 microprocessors
AMD microarchitectures