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The Intel Core microarchitecture (provisionally referred to as Next Generation Micro-architecture, and developed as Merom) is a multi-core
processor Processor may refer to: Computing Hardware * Processor (computing) **Central processing unit (CPU), the hardware within a computer that executes a program *** Microprocessor, a central processing unit contained on a single integrated circuit (I ...
microarchitecture In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular processor. A given ISA may be impl ...
launched by
Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...
in mid-2006. It is a major evolution over the Yonah, the previous iteration of the P6 microarchitecture series which started in 1995 with
Pentium Pro The Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel and introduced on November 1, 1995. It introduced the P6 microarchitecture (sometimes termed i686) and was originally intended to replace the original P ...
. It also replaced the NetBurst microarchitecture, which suffered from high power consumption and heat intensity due to an inefficient
pipeline Pipeline may refer to: Electronics, computers and computing * Pipeline (computing), a chain of data-processing stages or a CPU optimization found on ** Instruction pipelining, a technique for implementing instruction-level parallelism within a s ...
designed for high
clock rate In computing, the clock rate or clock speed typically refers to the frequency at which the clock generator of a processor can generate pulses, which are used to synchronize the operations of its components, and is used as an indicator of the pr ...
. In early 2004 the new version of NetBurst (Prescott) needed very high power to reach the clocks it needed for competitive performance, making it unsuitable for the shift to dual/multi-core CPUs. On May 7, 2004 Intel confirmed the cancellation of the next NetBurst. Intel had been developing Merom, the 64-bit evolution of the
Pentium M The Pentium M is a family of mobile 32-bit single-core x86 microprocessors (with the modified Intel P6 microarchitecture) introduced in March 2003 and forming a part of the Intel Carmel notebook platform under the then new Centrino brand. The '' ...
, since 2001, and decided to expand it to all market segments, replacing NetBurst in desktop computers and servers. It inherited from Pentium M the choice of a short and efficient pipeline, delivering superior performance despite not reaching the high clocks of NetBurst. The first processors that used this architecture were code-named ' Merom', ' Conroe', and ' Woodcrest'; Merom is for mobile computing, Conroe is for desktop systems, and Woodcrest is for servers and workstations. While architecturally identical, the three processor lines differ in the socket used, bus speed, and power consumption. The first Core-based desktop and mobile processors were branded ''
Core 2 Intel Core 2 is the processor family encompassing a range of Intel's consumer 64-bit x86-64 single-, dual-, and quad-core microprocessors based on the Core microarchitecture. The single- and dual-core models are single- die, whereas the quad-cor ...
'', later expanding to the lower-end ''
Pentium Dual-Core The Pentium Dual-Core brand was used for mainstream x86-architecture microprocessors from Intel from 2006 to 2009 when it was renamed to Pentium. The processors are based on either the 32-bit '' Yonah'' or (with quite different microarchitectur ...
'', ''
Pentium Pentium is a brand used for a series of x86 architecture-compatible microprocessors produced by Intel. The original Pentium processor from which the brand took its name was first released on March 22, 1993. After that, the Pentium II and Pe ...
'' and ''
Celeron Celeron is Intel's brand name for low-end IA-32 and x86-64 computer microprocessor models targeted at low-cost personal computers. Celeron processors are compatible with IA-32 IA-32 (short for "Intel Architecture, 32-bit", commonly called ...
'' brands; while server and workstation Core-based processors were branded ''
Xeon Xeon ( ) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same arc ...
''.


Features

The Core microarchitecture returned to lower
clock rate In computing, the clock rate or clock speed typically refers to the frequency at which the clock generator of a processor can generate pulses, which are used to synchronize the operations of its components, and is used as an indicator of the pr ...
s and improved the use of both available clock cycles and power when compared with the preceding NetBurst microarchitecture of the
Pentium 4 Pentium 4 is a series of single-core CPUs for desktops, laptops and entry-level servers manufactured by Intel. The processors were shipped from November 20, 2000 until August 8, 2008. The production of Netburst processors was active from 2000 ...
and D-branded CPUs. The Core microarchitecture provides more efficient decoding stages, execution units,
cache Cache, caching, or caché may refer to: Places United States * Cache, Idaho, an unincorporated community * Cache, Illinois, an unincorporated community * Cache, Oklahoma, a city in Comanche County * Cache, Utah, Cache County, Utah * Cache Count ...
s, and
buses A bus (contracted from omnibus, with variants multibus, motorbus, autobus, etc.) is a road vehicle that carries significantly more passengers than an average car or van. It is most commonly used in public transport, but is also in use for cha ...
, reducing the
power consumption Electric energy consumption is the form of energy consumption that uses electrical energy. Electric energy consumption is the actual energy demand made on existing electricity supply for transportation, residential, industrial, commercial, and o ...
of Core 2-branded CPUs while increasing their processing capacity. Intel's CPUs have varied widely in power consumption according to clock rate, architecture, and semiconductor process, shown in the
CPU power dissipation Processor power dissipation or processing unit power dissipation is the process in which computer processors consume electrical energy, and dissipate this energy in the form of heat due to the resistance in the electronic circuits. Power manage ...
tables. Like the last NetBurst CPUs, Core based processors feature multiple cores and hardware virtualization support (marketed as
Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
), and
Intel 64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
and
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitecture ...
. However, Core-based processors do not have the
hyper-threading Hyper-threading (officially called Hyper-Threading Technology or HT Technology and abbreviated as HTT or HT) is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multip ...
technology as in Pentium 4 processors. This is because the Core microarchitecture is based on the
P6 microarchitecture The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686. It was succeeded by the NetBurst microarch ...
used by Pentium Pro, II, III, and M. The L1 cache of the Core microarchitecture at 64 KB L1 cache/core (32 KB L1 Data + 32 KB L1 Instruction) is as large as in Pentium M, up from 32 KB on Pentium II / III (16 KB L1 Data + 16 KB L1 Instruction). The consumer version also lacks an L3 cache as in the Gallatin core of the Pentium 4 Extreme Edition, though it is exclusively present in high-end versions of Core-based Xeons. Both an L3 cache and hyper-threading were reintroduced again to consumer line in the
Nehalem microarchitecture Nehalem is the codename for Intel's 45 nm microarchitecture released in November 2008. It was used in the first-generation of the Intel Core i5 and i7 processors, and succeeds the older Core microarchitecture used on Core 2 processors. The ...
.


Roadmap


Technology

While the Core microarchitecture is a major architectural revision, it is based in part on the
Pentium M The Pentium M is a family of mobile 32-bit single-core x86 microprocessors (with the modified Intel P6 microarchitecture) introduced in March 2003 and forming a part of the Intel Carmel notebook platform under the then new Centrino brand. The '' ...
processor family designed by Intel Israel. The
pipeline Pipeline may refer to: Electronics, computers and computing * Pipeline (computing), a chain of data-processing stages or a CPU optimization found on ** Instruction pipelining, a technique for implementing instruction-level parallelism within a s ...
of Core/ Penryn is 14 stages long – less than half of Prescott's. Penryn's successor Nehalem has a two cycles higher branch misprediction penalty than Core/Penryn. Core can ideally sustain up to 4
instructions per cycle In computer architecture, instructions per cycle (IPC), commonly called instructions per clock is one aspect of a processor's performance: the average number of instructions executed for each clock cycle. It is the multiplicative inverse of cycl ...
(IPC) execution rate, compared to the 3 IPC capability of P6,
Pentium M The Pentium M is a family of mobile 32-bit single-core x86 microprocessors (with the modified Intel P6 microarchitecture) introduced in March 2003 and forming a part of the Intel Carmel notebook platform under the then new Centrino brand. The '' ...
and
NetBurst The NetBurst microarchitecture, called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of central processing units (CPUs) made by Intel. The first CPU to use this architecture was the Willamette-core Pentium 4 ...
microarchitectures. The new architecture is a dual core design with a shared
L2 cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which ...
engineered for maximum
performance per watt In computing, performance per watt is a measure of the energy efficiency of a particular computer architecture or computer hardware. Literally, it measures the rate of computation that can be delivered by a computer for every watt of power consume ...
and improved scalability. One new technology included in the design is Macro-Ops Fusion, which combines two
x86 x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introd ...
instructions into a single
micro-operation In computer central processing units, micro-operations (also known as micro-ops or μops, historically also as micro-actions) are detailed low-level instructions used in some designs to implement complex machine instructions (sometimes termed m ...
. For example, a common code sequence like a compare followed by a conditional jump would become a single micro-op. However, this technology does not work in 64-bit mode. Core can speculatively execute loads ahead of preceding stores with unknown addresses. Other new technologies include 1 cycle throughput (2 cycles previously) of all 128-bit SSE instructions and a new power saving design. All components will run at minimum speed, raising speed dynamically as needed (similar to AMD's
Cool'n'Quiet AMD Cool'n'Quiet is a CPU dynamic frequency scaling and power saving technology introduced by AMD with its Athlon XP processor line. It works by reducing the processor's clock rate and voltage when the processor is idle. The aim of this technolo ...
power-saving technology, and Intel's own
SpeedStep Enhanced SpeedStep is a series of dynamic frequency scaling technologies (codenamed Geyserville and including SpeedStep, SpeedStep II, and SpeedStep III) built into some Intel microprocessors that allow the clock speed of the processor to be dynami ...
technology from earlier mobile processors). This allows the chip to produce less heat, and minimize power use. For most Woodcrest CPUs, the
front-side bus A front-side bus (FSB) is a computer communication interface (bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between the ...
(FSB) runs at 1333
MT/s In computer technology, transfers per second and its more common secondary terms gigatransfers per second (abbreviated as GT/s) and megatransfers per second (MT/s) are informal language that refer to the number of operations transferring data that ...
; however, this is scaled down to 1066 MT/s for lower end 1.60 and 1.86 GHz variants. The Merom mobile variant was initially targeted to run at an FSB of 667 MT/s while the second wave of Meroms, supporting 800 MT/s FSB, were released as part of the Santa Rosa platform with a different socket in May 2007. The desktop-oriented Conroe began with models having an FSB of 800 MT/s or 1066 MT/s with a 1333 MT/s line officially launched on July 22, 2007. The power use of these processors is very low: average energy use is to be in the 1–2 watt range in ultra low voltage variants, with
thermal design power The thermal design power (TDP), sometimes called thermal design point, is the maximum amount of heat generated by a computer chip or component (often a CPU, GPU or system on a chip) that the cooling system in a computer is designed to dissipate ...
s (TDPs) of 65 watts for Conroe and most Woodcrests, 80 watts for the 3.0 GHz Woodcrest, and 40 or 35 watts for the low-voltage Woodcrest. In comparison, a 2.2 GHz AMD
Opteron Opteron is AMD's x86 former server and workstation processor line, and was the first processor which supported the AMD64 instruction set architecture (known generically as x86-64 or AMD64). It was released on April 22, 2003, with the ''SledgeHa ...
875HE processor consumes 55 watts, while the energy efficient
Socket AM2 The Socket AM2, renamed from Socket M2 (to prevent using the same name as Cyrix MII processors), is a CPU socket designed by AMD for desktop processors, including the performance, mainstream and value segments. It was released on May 23, 2006, as ...
line fits in the 35 watt
thermal envelope A building envelope is the physical separator between the conditioned and unconditioned environment of a building including the resistance to air, water, heat, light, and noiseSyed, Asif. ''Advanced building technologies for sustainability''. Hoboke ...
(specified a different way so not directly comparable). Merom, the mobile variant, is listed at 35 watts TDP for standard versions and 5 watts TDP for ultra low voltage (ULV) versions. Previously, Intel announced that it would now focus on power efficiency, rather than raw performance. However, at
Intel Developer Forum The Intel Developer Forum (IDF) was a biannual gathering of technologists to discuss Intel products and products based on Intel products. The first IDF was held in 1997. To emphasize the importance of China, the Spring 2007 IDF was held in Beiji ...
(IDF) in spring 2006, Intel advertised both. Some of the promised numbers were: * 20% more performance for Merom at the same power level; compared to
Core Duo Intel Core is a line of streamlined midrange consumer, workstation and enthusiast computer central processing units (CPUs) marketed by Intel Corporation. These processors displaced the existing mid- to high-end Pentium processors at the time ...
* 40% more performance for Conroe at 40% less power; compared to
Pentium D Pentium D is a range of desktop 64-bit x86-64 processors based on the NetBurst microarchitecture, which is the dual-core variant of the Pentium 4 manufactured by Intel. Each CPU comprised two dies, each containing a single core, residing next to ...
* 80% more performance for Woodcrest at 35% less power; compared to the original dual-core Xeon


Processor cores

The processors of the Core microarchitecture can be categorized by number of cores, cache size, and socket; each combination of these has a unique code name and product code that is used across several brands. For instance, code name "Allendale" with product code 80557 has two cores, 2 MB L2 cache and uses the desktop socket 775, but has been marketed as Celeron, Pentium, Core 2, and Xeon, each with different sets of features enabled. Most of the mobile and desktop processors come in two variants that differ in the size of the L2 cache, but the specific amount of L2 cache in a product can also be reduced by disabling parts at production time. Tigerton dual-cores and all quad-core processors except Dunnington QC are multi-chip modules combining two dies. For the 65 nm processors, the same product code can be shared by processors with different dies, but the specific information about which one is used can be derived from the stepping.


Conroe/Merom (65 nm)

The original Core 2 processors are based on the same dies that can be identified as
CPUID In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from CPU IDentification) allowing software to discover details of the processor. It was introduced by Intel i ...
Family 6 Model 15. Depending on their configuration and packaging, their code names are Conroe (
LGA 775 LGA 775 (land grid array 775), also known as Socket T, is an Intel desktop CPU socket. Unlike PGA CPU sockets, such as its predecessor Socket 478, LGA 775 has no socket holes; instead, it has 775 protruding pins which touch contact points on the ...
, 4 MB L2 cache), Allendale (LGA 775, 2 MB L2 cache), Merom (
Socket M Socket M (mPGA478MT) is a CPU interface introduced by Intel in 2006 for the Intel Core line of mobile processors. Technical specifications Socket M is used in all Intel Core products, as well as the Core-derived Dual-Core Xeon codenamed Sossama ...
, 4 MB L2 cache) and Kentsfield (
multi-chip module A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or "pins") where multiple integrated circuits (ICs or "chips"), semiconductor dies and/or other discrete components are int ...
, LGA 775, 2x4MB L2 cache). Merom and Allendale processors with limited features are in
Pentium Dual Core The Pentium Dual-Core brand was used for mainstream x86-architecture microprocessors from Intel from 2006 to 2009 when it was renamed to Pentium. The processors are based on either the 32-bit '' Yonah'' or (with quite different microarchitectu ...
and
Celeron Celeron is Intel's brand name for low-end IA-32 and x86-64 computer microprocessor models targeted at low-cost personal computers. Celeron processors are compatible with IA-32 IA-32 (short for "Intel Architecture, 32-bit", commonly called ...
processors, while Conroe, Allendale and Kentsfield also are sold as
Xeon Xeon ( ) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same arc ...
processors. Additional code names for processors based on this model are Woodcrest (LGA 771, 4 MB L2 cache), Clovertown (MCM, LGA 771, 2×4MB L2 cache) and Tigerton (MCM,
Socket 604 Socket 604 is a 604-pin microprocessor socket designed to interface an Intel's Xeon processor to the rest of the computer. It provides both an electrical interface as well as physical support. This socket is designed to support a heatsink. Launch ...
, 2×4MB L2 cache), all of which are marketed only under the Xeon brand.


Conroe-L/Merom-L

The Conroe-L and Merom-L processors are based around the same core as Conroe and Merom, but only contain a single core and 1 MB of L2 cache, significantly reducing production cost and power consumption of the processor at the expense of performance compared to the dual-core version. It is used only in ultra-low voltage Core 2 Solo U2xxx and in Celeron processors and is identified as CPUID family 6 model 22.


Penryn/Wolfdale (45 nm)

In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket P), Wolfdale (LGA 775) and Yorkfield (MCM, LGA 775), some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the Wolfdale-DP and Harpertown code names are used for LGA 771 based MCMs with two or four active Wolfdale cores. Architecturally, 45 nm Core 2 processors feature SSE4.1 and new divide/shuffle engine. The chips come in two sizes, with 6 MB and 3 MB L2 cache. The smaller version is commonly called Penryn-3M and Wolfdale-3M and Yorkfield-6M, respectively. The single-core version of Penryn, listed as Penryn-L here, is not a separate model like Merom-L but a version of the Penryn-3M model with only one active core.


Dunnington

The Xeon "Dunnington" processor (CPUID Family 6, model 29) is closely related to Wolfdale but comes with six cores and an on-chip L3 cache and is designed for servers with Socket 604, so it is marketed only as Xeon, not as Core 2.


Steppings

The Core microarchitecture uses several
stepping level In integrated circuits, the stepping level or revision level is a version number that refers to the introduction or revision of one or more photolithographic photomasks within the set of photomasks that is used to pattern an integrated circuit. ...
s (steppings), which unlike prior microarchitectures, represent incremental improvements, and different sets of features like cache size and low power modes. Most of these steppings are used across brands, typically by disabling some features and limiting clock frequencies on low-end chips. Steppings with a reduced cache size use a separate naming scheme, which means that the releases are no longer in alphabetic order. Added steppings have been used in internal and engineering samples, but are unlisted in the tables. Many of the high-end Core 2 and Xeon processors use
Multi-chip module A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or "pins") where multiple integrated circuits (ICs or "chips"), semiconductor dies and/or other discrete components are int ...
s of two chips in order to get larger cache sizes or more than two cores.


Steppings using 65 nm process

Early ES/QS steppings are: B0 (CPUID 6F4h), B1 (6F5h) and E0 (6F9h). Steppings B2/B3, E1, and G0 of model 15 (cpuid 06fx) processors are evolutionary steps of the standard Merom/Conroe die with 4 MB L2 cache, with the short-lived E1 stepping only being used in mobile processors. Stepping L2 and M0 are the '' Allendale'' chips with just 2 MB L2 cache, reducing production cost and power consumption for low-end processors. The G0 and M0 steppings improve idle power consumption in C1E state and add the C2E state in desktop processors. In mobile processors, all of which support C1 through C4 idle states, steppings E1, G0, and M0 add support for the Mobile Intel 965 Express (
Santa Rosa Santa Rosa is the Italian, Portuguese and Spanish name for Saint Rose. Santa Rosa may also refer to: Places Argentina *Santa Rosa, Mendoza, a city * Santa Rosa, Tinogasta, Catamarca * Santa Rosa, Valle Viejo, Catamarca *Santa Rosa, La Pampa * Sa ...
) platform with
Socket P The Intel Socket P (mPGA478MN) is the mobile processor socket replacement for Core microarchitecture chips such as Core 2 Duo. It launched on May 9, 2007, as part of the Santa Rosa platform with the Merom and Penryn processors. Technical spec ...
, while the earlier B2 and L2 steppings only appear for the
Socket M Socket M (mPGA478MT) is a CPU interface introduced by Intel in 2006 for the Intel Core line of mobile processors. Technical specifications Socket M is used in all Intel Core products, as well as the Core-derived Dual-Core Xeon codenamed Sossama ...
based Mobile Intel 945 Express ( Napa refresh) platform. The model 22 stepping A1 (cpuid 10661h) marks a significant design change, with just a single core and 1 MB L2 cache further reducing the power consumption and manufacturing cost for the low-end. Like the earlier steppings, A1 is not used with the Mobile Intel 965 Express platform. Steppings G0, M0 and A1 mostly replaced all older steppings in 2008. In 2009, a new stepping G2 was introduced to replace the original stepping B2.


Steppings using 45 nm process

In the model 23 (cpuid 01067xh), Intel started marketing stepping with full (6 MB) and reduced (3 MB) L2 cache at the same time, and giving them identical cpuid values. All steppings have the new
SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; mor ...
instructions. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad core processors and only used in those. Stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and replaces all earlier steppings. In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express ( Santa Rosa refresh) platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express ( Montevina) platform. Model 30 stepping A1 (cpuid 106d1h) adds an L3 cache and six instead of the usual two cores, which leads to an unusually large die size of 503 mm². As of February 2008, it has only found its way into the very high-end Xeon 7400 series (
Dunnington Dunnington is a village and civil parish in the City of York and ceremonial county of North Yorkshire, England. The population of the civil parish was 3,230 at the 2011 Census. The village is approximately east from York city centre. The vi ...
).


System requirements


Motherboard compatibility

Conroe, Conroe XE and Allendale all use Socket
LGA 775 LGA 775 (land grid array 775), also known as Socket T, is an Intel desktop CPU socket. Unlike PGA CPU sockets, such as its predecessor Socket 478, LGA 775 has no socket holes; instead, it has 775 protruding pins which touch contact points on the ...
; however, not every
motherboard A motherboard (also called mainboard, main circuit board, mb, mboard, backplane board, base board, system board, logic board (only in Apple computers) or mobo) is the main printed circuit board (PCB) in general-purpose computers and other expand ...
is compatible with these processors. Supporting
chipset In a computer system, a chipset is a set of electronic components An electronic component is any basic discrete device or physical entity in an electronic system used to affect electrons or their associated fields. Electronic components are ...
s are: *
Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...
: 865G/PE/P, 945G/GZ/GC/P/PL, 965G/P, 975X, P/G/Q965, Q963, 946GZ/PL, P3x, G3x, Q3x, X38, X48, P4x, 5400 Express (See also:
List of Intel chipsets This article provides a list of motherboard chipsets made by Intel, divided into three main categories: those that use the PCI bus for interconnection (the 4xx series), those that connect using specialized "hub links" (the 8xx series), and those ...
) *
NVIDIA Nvidia CorporationOfficially written as NVIDIA and stylized in its logo as VIDIA with the lowercase "n" the same height as the uppercase "VIDIA"; formerly stylized as VIDIA with a large italicized lowercase "n" on products from the mid 1990s to ...
:
nForce4 The nForce4 is a motherboard chipset released by Nvidia in October 2004. The chipset supports AMD 64-bit processors (Socket 939, Socket AM2 and Socket 754) and Intel Pentium 4 LGA 775 processors. Models nForce4/nForce4-4x nForce4 is the second ...
Ultra/SLI X16 for Intel, nForce 570/590 SLI for Intel, nForce 650i Ultra/650i SLI/680i LT SLI/680i SLI and nForce 750i SLI/780i SLI/790i SLI/790i Ultra SLI. *
VIA Via or VIA may refer to the following: Science and technology * MOS Technology 6522, Versatile Interface Adapter * ''Via'' (moth), a genus of moths in the family Noctuidae * Via (electronics), a through-connection * VIA Technologies, a Taiwan ...
: P4M800, P4M800PRO, P4M890, P4M900, PT880 Pro/Ultra, PT890. (See also:
List of VIA chipsets This is a list of computer motherboard chipsets made by VIA Technologies. Northbridge chips are listed first, primarily by CPU-socket or CPU-family; southbridge chips are listed in a later table. Background VIA chipsets support CPUs from Intel, ...
) * SiS: 662, 671, 671fx, 672, 672fx *
ATI Ati or ATI may refer to: * Ati people, a Negrito ethnic group in the Philippines **Ati language (Philippines), the language spoken by this people group ** Ati-Atihan festival, an annual celebration held in the Philippines *Ati language (China), a ...
: Radeon Xpress 200 and CrossFire Xpress 3200 for Intel The Yorkfield XE model QX9770 (45 nm with 1600 MT/s FSB) has limited chipset compatibility - with only X38, P35 (With
Overclocking In computing, overclocking is the practice of increasing the clock rate of a computer to exceed that certified by the manufacturer. Commonly, operating voltage is also increased to maintain a component's operational stability at accelerated spe ...
) and some high-performance X48 and P45 motherboards being compatible. BIOS updates were gradually being released to provide support for the Penryn technology, and the QX9775 is only compatible with the Intel D5400XS motherboard. The Wolfdale-3M model E7200 also has limited compatibility (at least the Xpress 200 chipset is incompatible). Although a motherboard may have the required chipset to support Conroe, some motherboards based on the above-mentioned chipsets do not support Conroe. This is because all Conroe-based processors require a new power delivery feature set specified i
Voltage Regulator-Down (VRD) 11.0
This requirement is a result of Conroe's significantly lower power consumption, compared to the Pentium 4/D CPUs it replaced. A motherboard that has both a supporting chipset and VRD 11 supports Conroe processors, but even then some boards will need an updated
BIOS In computing, BIOS (, ; Basic Input/Output System, also known as the System BIOS, ROM BIOS, BIOS ROM or PC BIOS) is firmware used to provide runtime services for operating systems and programs and to perform hardware initialization during the ...
to recognize Conroe's FID (Frequency ID) and VID (Voltage ID).


Synchronous memory modules

Unlike the prior
Pentium 4 Pentium 4 is a series of single-core CPUs for desktops, laptops and entry-level servers manufactured by Intel. The processors were shipped from November 20, 2000 until August 8, 2008. The production of Netburst processors was active from 2000 ...
and
Pentium D Pentium D is a range of desktop 64-bit x86-64 processors based on the NetBurst microarchitecture, which is the dual-core variant of the Pentium 4 manufactured by Intel. Each CPU comprised two dies, each containing a single core, residing next to ...
design, the Core 2 technology sees a greater benefit from memory running synchronously with the
front-side bus A front-side bus (FSB) is a computer communication interface (bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between the ...
(FSB). This means that for the Conroe CPUs with FSB of 1066 MT/s, the ideal memory performance for DDR2 is PC2-8500. In a few configurations, using PC2-5300 instead of PC2-4200 can actually decrease performance. Only when going to PC2-6400 is there a significant performance increase. While DDR2 memory models with tighter timing specifications do improve performance, the difference in real world games and applications is often negligible. Optimally, the memory bandwidth afforded should match the bandwidth of the FSB, that is to say that a CPU with a 533 MT/s rated bus speed should be paired with RAM matching the same rated speed, for example DDR2 533, or PC2-4200. A common myth is that installing interleaved RAM will offer double the bandwidth. However, at most the increase in bandwidth by installing interleaved RAM is roughly 5–10%. Th
AGTL+ PSB
used by all
NetBurst The NetBurst microarchitecture, called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of central processing units (CPUs) made by Intel. The first CPU to use this architecture was the Willamette-core Pentium 4 ...
processors and current and medium-term (pre-
QuickPath The Intel QuickPath Interconnect (QPI) is a point-to-point processor interconnect developed by Intel which replaced the front-side bus (FSB) in Xeon, Itanium, and certain desktop platforms starting in 2008. It increased the scalability and availa ...
) Core 2 processors provide a 64-bit data path. Current chipsets provide for a couple of either DDR2 or DDR3 channels. On jobs requiring large amounts of memory access, the quad-core Core 2 processors can benefit significantly from using PC2-8500 memory, which runs at the same speed as the CPU's FSB; this is not an officially supported configuration, but several motherboards support it. The Core 2 processor does not require the use of DDR2. While the Intel 975X and P965 chipsets require this memory, some motherboards and chipsets support both Core 2 processors and
DDR DDR or ddr may refer to: *ddr, ISO 639-3 code for the Dhudhuroa language *DDr., title for a double doctorate in Germany *DDR, station code for Dadar railway station, Mumbai, India *' (German Democratic Republic), official name of the former East ...
memory. When using DDR memory, performance may be reduced because of the lower available memory bandwidth.


Chip errata

The Core 2
memory management unit A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware unit having all memory references passed through itself, primarily performing the translation of virtual memory addresses to physical ad ...
(MMU) in X6800, E6000 and E4000 processors does not operate to prior specifications implemented in prior generations of
x86 x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introd ...
hardware. This may cause problems, many of them serious security and stability issues, with extant
operating system An operating system (OS) is system software that manages computer hardware, software resources, and provides common services for computer programs. Time-sharing operating systems schedule tasks for efficient use of the system and may also in ...
software. Intel's documentation states that their programming manuals will be updated "in the coming months" with information on recommended methods of managing the
translation lookaside buffer A translation lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory to physical memory. It is used to reduce the time taken to access a user memory location. It can be called an address-translation cache. ...
(TLB) for Core 2 to avoid issues, and admits that, "in rare instances, improper TLB invalidation may result in unpredictable system behavior, such as hangs or incorrect data." Among the issues stated: * Non-execute bit is shared across the cores. * Floating point instruction non-coherencies. * Allowed memory corruptions outside of the range of permitted writing for a process by running common instruction sequences. Intel
errata An erratum or corrigendum (plurals: errata, corrigenda) (comes from la, errata corrige) is a correction of a published text. As a general rule, publishers issue an erratum for a production error (i.e., an error introduced during the publishing pro ...
Ax39, Ax43, Ax65, Ax79, Ax90, Ax99 are said to be particularly serious. 39, 43, 79, which can cause unpredictable behavior or system hang, have been fixed in recent steppings. Among those who have stated the errata to be particularly serious are
OpenBSD OpenBSD is a security-focused, free and open-source, Unix-like operating system based on the Berkeley Software Distribution (BSD). Theo de Raadt created OpenBSD in 1995 by forking NetBSD 1.0. According to the website, the OpenBSD project em ...
's
Theo de Raadt Theo de Raadt (; ; born May 19, 1968) is a South African-born software engineer who lives in Calgary, Alberta, Canada. He is the founder and leader of the OpenBSD and OpenSSH projects and was also a founding member of NetBSD. In 2004, De Raadt wo ...
and
DragonFly BSD DragonFly BSD is a free and open-source Unix-like operating system forked from FreeBSD 4.8. Matthew Dillon, an Amiga developer in the late 1980s and early 1990s and FreeBSD developer between 1994 and 2003, began working on DragonFly BSD in Ju ...
's
Matthew Dillon Matthew Dillon (born 1966) is an American software engineer known for Amiga software, contributions to FreeBSD and for starting and leading the DragonFly BSD project since 2003. Biography Dillon studied electronic engineering and computer scien ...
. Taking a contrasting view was
Linus Torvalds Linus Benedict Torvalds ( , ; born 28 December 1969) is a Finnish software engineer who is the creator and, historically, the lead developer of the Linux kernel, used by Linux distributions and other operating systems such as Android. He also c ...
, calling the TLB issue "totally insignificant", adding, "The biggest problem is that Intel should just have documented the TLB behavior better." Microsoft has issued update KB936357 to address the errata by
microcode In processor design, microcode (μcode) is a technique that interposes a layer of computer organization between the central processing unit (CPU) hardware and the programmer-visible instruction set architecture of a computer. Microcode is a laye ...
update, with no performance penalty. BIOS updates are also available to fix the issue.


See also

*
x86 architecture x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introd ...
*
List of Intel CPU microarchitectures The following is a ''partial'' list of Intel CPU microarchitectures. The list is ''incomplete''. Additional details can be found in Intel's Tick–tock model and Process–architecture–optimization model. x86 microarchitectures 16-bit ; ...


References


External links


Intel Core Microarchitecture website
* ttp://www.intel.com/pressroom/archive/releases/20060307corp.htm Intel press release introducing the Core Microarchitecturebr>Intel processor roadmapA Detailed Look at Intel's New Core ArchitectureIntel names the Core Microarchitecture
* ttps://web.archive.org/web/20060322051611/http://www.tgdaily.com/2006/03/07/idf_keynotes_welcome_to_intel_3-point-0/ IDF keynotes, advertising the performance of the new processorsbr>The Core of Intel's new chipsRealWorld Tech's overview of the Core microarchitectureDetailed overview of the Core microarchitecture at Ars TechnicaIntel Core versus AMD's K8 architecture at AnandtechRelease dates of upcoming Intel Core processors using the Intel Core MicroarchitectureBenchmarks Comparing the Computational Power of Core Architecture against Older Intel Netburst and AMD Athlon64 Central Processing Units
{{Intel processors, core
Core microarchitecture The Intel Core microarchitecture (provisionally referred to as Next Generation Micro-architecture, and developed as Merom) is a multi-core processor microarchitecture launched by Intel in mid-2006. It is a major evolution over the Yonah, the p ...
Core Core or cores may refer to: Science and technology * Core (anatomy), everything except the appendages * Core (manufacturing), used in casting and molding * Core (optical fiber), the signal-carrying portion of an optical fiber * Core, the central ...
Core Core or cores may refer to: Science and technology * Core (anatomy), everything except the appendages * Core (manufacturing), used in casting and molding * Core (optical fiber), the signal-carrying portion of an optical fiber * Core, the central ...