Opteron is
AMD
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactur ...
's
x86
x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introd ...
former server and workstation
processor
Processor may refer to:
Computing Hardware
* Processor (computing)
**Central processing unit (CPU), the hardware within a computer that executes a program
*** Microprocessor, a central processing unit contained on a single integrated circuit (I ...
line, and was the first processor which supported the
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
instruction set architecture
In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ' ...
(known generically as
x86-64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
or AMD64). It was released on April 22, 2003, with the ''SledgeHammer'' core (K8) and was intended to compete in the
server
Server may refer to:
Computing
*Server (computing), a computer program or a device that provides functionality for other programs or devices, called clients
Role
* Waiting staff, those who work at a restaurant or a bar attending customers and su ...
and
workstation
A workstation is a special computer designed for technical or scientific applications. Intended primarily to be used by a single user, they are commonly connected to a local area network and run multi-user operating systems. The term ''workstat ...
markets, particularly in the same segment as the Intel
Xeon
Xeon ( ) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same arc ...
processor. Processors based on the
AMD K10
The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. Though there were once reports that the K10 had been canceled, microarchitecture (codenamed ''Barcelona'') were announced on September 10, 2007, featuring a new
quad-core
A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions (such a ...
configuration. The most-recently released Opteron CPUs are the
Piledriver-based Opteron 4300 and 6300 series processors, codenamed "Seoul" and "Abu Dhabi" respectively.
In January 2016, the first
ARMv8-A
ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer (RISC) instruction set architectures for computer processors, configured ...
based Opteron-branded SoC was released,
though it is unclear what, if any, heritage this Opteron-branded product line shares with the original Opteron technology other than intended use in the server space.
Technical description
Two key capabilities
Opteron combines two important capabilities in a single processor:
# native execution of legacy x86
32-bit
In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculation ...
applications without speed penalties
# native execution of x86-64
64-bit
In computer architecture, 64-bit Integer (computer science), integers, memory addresses, or other Data (computing), data units are those that are 64 bits wide. Also, 64-bit central processing unit, CPUs and arithmetic logic unit, ALUs are those ...
applications
The first capability is notable because at the time of Opteron's introduction, the only other
64-bit
In computer architecture, 64-bit Integer (computer science), integers, memory addresses, or other Data (computing), data units are those that are 64 bits wide. Also, 64-bit central processing unit, CPUs and arithmetic logic unit, ALUs are those ...
architecture marketed with
32-bit
In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculation ...
x86
x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introd ...
compatibility (Intel's
Itanium
Itanium ( ) is a discontinued family of 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). Launched in June 2001, Intel marketed the processors for enterprise servers and high-performance computin ...
) ran
x86
x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introd ...
legacy-applications only with significant speed degradation. The second capability, by itself, is less noteworthy, as major
RISC
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set comput ...
architectures (such as
SPARC
SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed ...
,
Alpha
Alpha (uppercase , lowercase ; grc, ἄλφα, ''álpha'', or ell, άλφα, álfa) is the first letter of the Greek alphabet. In the system of Greek numerals, it has a value of one. Alpha is derived from the Phoenician letter aleph , whic ...
,
PA-RISC
PA-RISC is an instruction set architecture (ISA) developed by Hewlett-Packard. As the name implies, it is a reduced instruction set computer (RISC) architecture, where the PA stands for Precision Architecture. The design is also referred to as ...
,
PowerPC
PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple Inc., App ...
,
MIPS) have been 64-bit for many years. In combining these two capabilities, however, the Opteron earned recognition for its ability to run the vast installed base of x86 applications economically, while simultaneously offering an upgrade-path to
64-bit computing
In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit CPUs and ALUs are those that are based on processor registers, address buses, or data buses of that size. A compute ...
.
The Opteron processor possesses an integrated
memory controller
The memory controller is a digital circuit that manages the flow of data going to and from the computer's main memory. A memory controller can be a separate chip or integrated into another chip, such as being placed on the same die or as an int ...
supporting
DDR SDRAM
Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 ...
,
DDR2 SDRAM
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DDR3 ...
or
DDR3 SDRAM
Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth (" double data rate") interface, and has been in use since 2007. It is the higher-speed ...
(depending on processor generation). This both reduces the latency penalty for accessing the main
RAM
Ram, ram, or RAM may refer to:
Animals
* A male sheep
* Ram cichlid, a freshwater tropical fish
People
* Ram (given name)
* Ram (surname)
* Ram (director) (Ramsubramaniam), an Indian Tamil film director
* RAM (musician) (born 1974), Dutch
* ...
and eliminates the need for a separate
northbridge chip.
Multi-processor features
In multi-processor systems (more than one Opteron on a single
motherboard
A motherboard (also called mainboard, main circuit board, mb, mboard, backplane board, base board, system board, logic board (only in Apple computers) or mobo) is the main printed circuit board (PCB) in general-purpose computers and other expand ...
), the
CPUs
A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, and ...
communicate using the
Direct Connect Architecture over high-speed
HyperTransport
HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low- latency point-to-point link that was introduced on April 2 ...
links. Each CPU can access the main memory of another processor, transparent to the programmer. The Opteron approach to multi-processing is not the same as standard
symmetric multiprocessing
Symmetric multiprocessing or shared-memory multiprocessing (SMP) involves a multiprocessor computer hardware and software architecture where two or more identical processors are connected to a single, shared main memory, have full access to all ...
; instead of having one bank of memory for all CPUs, each CPU has its own memory. Thus the Opteron is a
Non-Uniform Memory Access
Non-uniform memory access (NUMA) is a computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to the processor. Under NUMA, a processor can access its own local memory faster than non- ...
(NUMA) architecture. The Opteron CPU directly supports up to an 8-way configuration, which can be found in mid-level servers. Enterprise-level servers use additional (and expensive) routing chips to support more than 8 CPUs per box.
In a variety of computing benchmarks, the Opteron architecture has demonstrated better multi-processor scaling than the Intel
Xeon
Xeon ( ) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same arc ...
which didn't have a point to point system until QPI and integrated memory controllers with the Nehalem design. This is primarily because adding another Opteron processor increases memory bandwidth, while that is not always the case for Xeon systems, and the fact that the Opterons use a
switched fabric
Switched fabric or switching fabric is a network topology in which network Node (networking), nodes interconnect via one or more network switches (particularly crossbar switches). Because a switched fabric network spreads network traffic across m ...
, rather than a shared
bus
A bus (contracted from omnibus, with variants multibus, motorbus, autobus, etc.) is a road vehicle that carries significantly more passengers than an average car or van. It is most commonly used in public transport, but is also in use for cha ...
. In particular, the Opteron's integrated memory controller allows the CPU to access local
RAM
Ram, ram, or RAM may refer to:
Animals
* A male sheep
* Ram cichlid, a freshwater tropical fish
People
* Ram (given name)
* Ram (surname)
* Ram (director) (Ramsubramaniam), an Indian Tamil film director
* RAM (musician) (born 1974), Dutch
* ...
very quickly. In contrast, multiprocessor Xeon system CPUs share only two common buses for both processor-processor and processor-memory communication. As the number of CPUs increases in a typical Xeon system,
contention
Contention or contentious may refer to:
* Resource contention, in computer science, a conflict over access to a shared resource
* Contention (telecommunications), a media access method to share a broadcast medium
* Bus contention, an undesirable ...
for the shared bus causes computing efficiency to drop. Intel migrated to a memory architecture similar to the Opteron's for the
Intel Core i7
The following is a list of Intel Core i7 brand microprocessors. Introduced in 2008, the Core i7 line of microprocessors are intended to be used by high-end users.
Desktop processors
Nehalem microarchitecture (1st generation)
"Bloomfield" ...
family of processors and their Xeon derivatives.
Multi-core Opterons
![AMD Opteron Six Cores](https://upload.wikimedia.org/wikipedia/commons/1/1c/AMD_Opteron_Six_Cores.jpg)
In April 2005, AMD introduced its first multi-core Opterons. At the time, AMD's use of the term multi-core in practice meant
dual-core
A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions (such a ...
; each physical Opteron chip contained two processor cores. This effectively doubled the computing performance available to each motherboard processor socket. One socket could then deliver the performance of two processors, two sockets could deliver the performance of four processors, and so on. Because motherboard costs increase dramatically as the number of CPU sockets increase, multicore CPUs enable a multiprocessing system to be built at lower cost.
AMD's model number scheme has changed somewhat in light of its new multicore lineup. At the time of its introduction, AMD's fastest multicore Opteron was the model 875, with two cores running at 2.2
GHz
The hertz (symbol: Hz) is the unit of frequency in the International System of Units (SI), equivalent to one event (or cycle) per second. The hertz is an SI derived unit whose expression in terms of SI base units is s−1, meaning that one he ...
each. AMD's fastest single-core Opteron at this time was the model 252, with one core running at 2.6 GHz. For
multithreaded applications, or many single threaded applications, the model 875 would be much faster than the model 252.
Second-generation Opterons are offered in three series: the 1000 Series (single socket only), the 2000 Series (dual socket-capable), and the 8000 Series (quad or octo socket-capable). The 1000 Series uses the
AM2 socket. The 2000 Series and 8000 Series use
Socket F
Socket F is a CPU socket designed by Advanced Micro Devices, AMD for its Opteron line of Central processing unit, CPUs released on August 15, 2006. In 2010 Socket F was replaced by Socket C32 for entry-level servers and Socket G34 for high-end ser ...
br>
AMD announced its third-generation
quad-core
A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions (such a ...
Opteron chips on September 10, 2007
with hardware vendors announcing servers in the following month. Based on a core design codenamed ''Barcelona'', new power and thermal management techniques were planned for the chips. Earlier dual core DDR2 based platforms were upgradeable to quad core chips.
The fourth generation was announced in June 2009 with the ''Istanbul'' hexa-cores. It introduced ''HT Assist'', an additional directory for data location, reducing the overhead for probing and broadcasts. HT Assist uses 1 MB L3 cache per CPU when activated.
In March 2010 AMD released the ''Magny-Cours'' Opteron 6100 series CPUs for
Socket G34
Socket G34 is a land grid array CPU socket designed by AMD to support AMD's multi-chip module Opteron 6000-series server processors. G34 was launched on March 29, 2010, alongside the initial grouping of Opteron 6100 processors designed for it. S ...
. These are 8- and 12-core
multi-chip module
A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or "pins") where multiple integrated circuits (ICs or "chips"), semiconductor dies and/or other discrete components are int ...
CPUs consisting of two four or six-core dies with a
HyperTransport
HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low- latency point-to-point link that was introduced on April 2 ...
3.1 link connecting the two dies. These CPUs updated the multi-socket Opteron platform to use DDR3 memory and increased the maximum HyperTransport link speed from 2.40 GHz (4.80 GT/s) for the ''Istanbul'' CPUs to 3.20 GHz (6.40 GT/s).
AMD changed the naming scheme for its Opteron models. Opteron 4000 series CPUs on Socket C32 (released July 2010) are dual-socket capable and are targeted at uniprocessor and dual-processor uses. The Opteron 6000 series CPUs on Socket G34 are quad-socket capable and are targeted at high-end dual-processor and quad-processor applications.
Socket 939
AMD released
Socket 939
Socket 939 is a CPU socket released by AMD in June 2004 to supersede the previous Socket 754 for Athlon 64 processors. Socket 939 was succeeded by Socket AM2 in May 2006. It is the second socket designed for AMD's AMD64 range of processors.
Avai ...
Opterons, reducing the cost of motherboards for low-end servers and workstations. Except for the fact they have 1
MB L2 Cache (versus 512
KB for the Athlon64) the Socket 939 Opterons are identical to the San Diego and Toledo core
Athlon 64
The Athlon 64 is a ninth-generation, AMD64-architecture microprocessor produced by Advanced Micro Devices (AMD), released on September 23, 2003. It is the third processor to bear the name ''Athlon'', and the immediate successor to the Athlon XP. T ...
s, but are run at lower clock speeds than the cores are capable of, making them more stable.
Socket AM2
Socket AM2 Opterons are available for servers that only have a single-chip setup. Codenamed Santa Ana, rev. F dual core AM2 Opterons feature 2 × 1 MB L2 cache, unlike the majority of their
Athlon 64 X2
The Athlon 64 X2 is the first native dual-core desktop central processing unit (CPU) designed by Advanced Micro Devices (AMD). It was designed from scratch as native dual-core by using an already multi-CPU enabled Athlon 64, joining it with ano ...
cousins which feature 2 × 512 KB L2 cache. These CPUs are given model numbers ranging from 1210 to 1224.
Socket AM2+
AMD introduced three quad-core Opterons on Socket AM2+ for single-CPU servers in 2007. These CPUs are produced on a 65 nm manufacturing process and are similar to the ''Agena''
Phenom
Phenom may refer to:
* AMD Phenom, the 64-bit AMD desktop processor line based on the K10 microarchitecture
** Phenom II, a family of AMD's multi-core 45 nm processors using the AMD K10 microarchitecture
* Phenom (electron microscope), a fast elec ...
X4 CPUs. The Socket AM2+ quad-core Opterons are code-named "Budapest." The Socket AM2+ Opterons carry model numbers of 1352 (2.10 GHz), 1354 (2.20 GHz), and 1356 (2.30 GHz.)
Socket AM3
AMD introduced three quad-core Opterons on Socket AM3 for single-CPU servers in 2009. These CPUs are produced on a 45 nm manufacturing process and are similar to the ''Deneb''-based Phenom II X4 CPUs. The Socket AM3 quad-core Opterons are code-named "Suzuka." These CPUs carry model numbers of 1381 (2.50 GHz), 1385 (2.70 GHz), and 1389 (2.90 GHz.)
Socket AM3+
Socket AM3+
AM3+ is a modification of the AM3 Socket, released in mid-2011, designed for CPUs which use the AMD Bulldozer microarchitecture and retains compatibility with AM3 processors. The Vishera line of AMD CPUs also all use Socket AM3+. It is the last A ...
was introduced in 2011 and is a modification of AM3 for the
Bulldozer
A bulldozer or dozer (also called a crawler) is a large, motorized machine equipped with a metal blade to the front for pushing material: soil, sand, snow, rubble, or rock during construction work. It travels most commonly on continuous track ...
microarchitecture. Opteron CPUs in the AM3+ package are named Opteron 3xxx.
Socket F
Socket F
Socket F is a CPU socket designed by Advanced Micro Devices, AMD for its Opteron line of Central processing unit, CPUs released on August 15, 2006. In 2010 Socket F was replaced by Socket C32 for entry-level servers and Socket G34 for high-end ser ...
(
LGA 1207 contacts) is AMD’s second generation of Opteron socket. This socket supports processors such as the Santa Rosa, Barcelona, Shanghai, and Istanbul codenamed processors. The “''Lidded
land grid array
The land grid array (LGA) is a type of surface-mount packaging for integrated circuits (ICs) that is notable for having the pins on the socket (when a socket is used) rather than the integrated circuit. An LGA can be electrically connected to a ...
''” socket adds support for
DDR2 SDRAM
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DDR3 ...
and improved
HyperTransport
HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low- latency point-to-point link that was introduced on April 2 ...
version 3 connectivity. Physically the socket and processor package are nearly identical, although not generally compatible with
socket 1207 FX.
Socket G34
Socket G34
Socket G34 is a land grid array CPU socket designed by AMD to support AMD's multi-chip module Opteron 6000-series server processors. G34 was launched on March 29, 2010, alongside the initial grouping of Opteron 6100 processors designed for it. S ...
(LGA 1944 contacts) is one of the third generation of Opteron sockets, along with
Socket C32
Socket C32 is a zero insertion force land grid array CPU socket designed by AMD for their single-CPU and dual-CPU Opteron 4000 series server CPUs. It is the successor to Socket AM3 for single-CPU servers and the successor for Socket F for l ...
. This socket supports ''Magny-Cours'' Opteron 6100, Bulldozer-based ''Interlagos'' Opteron 6200, and Piledriver-based "Abu Dhabi" Opteron 6300 series processors. This socket supports four channels of
DDR3 SDRAM
Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth (" double data rate") interface, and has been in use since 2007. It is the higher-speed ...
(two per CPU die). Unlike previous multi-CPU Opteron sockets, Socket G34 CPUs will function with unbuffered ECC or non-ECC RAM in addition to the traditional registered ECC RAM.
Socket C32
Socket C32
Socket C32 is a zero insertion force land grid array CPU socket designed by AMD for their single-CPU and dual-CPU Opteron 4000 series server CPUs. It is the successor to Socket AM3 for single-CPU servers and the successor for Socket F for l ...
(LGA 1207 contacts) is the other member of the third generation of Opteron sockets. This socket is physically similar to
Socket F
Socket F is a CPU socket designed by Advanced Micro Devices, AMD for its Opteron line of Central processing unit, CPUs released on August 15, 2006. In 2010 Socket F was replaced by Socket C32 for entry-level servers and Socket G34 for high-end ser ...
but is not compatible with Socket F CPUs. Socket C32 uses DDR3 SDRAM and is keyed differently so as to prevent the insertion of Socket F CPUs that can use only DDR2 SDRAM. Like Socket G34, Socket C32 CPUs will be able to use unbuffered ECC or non-ECC RAM in addition to registered ECC SDRAM.
Micro-architecture update
The Opteron line saw an update with the implementation of the
AMD K10
The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. Though there were once reports that the K10 had been canceled, microarchitecture. New processors, launched in the third quarter of 2007 (codename ''Barcelona''), incorporate a variety of improvements, particularly in memory prefetching, speculative loads,
SIMD
Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal (part of the hardware design) and it can be directly accessible through an instruction set architecture (ISA), but it should ...
execution and
branch prediction
In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g., an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow ...
, yielding an appreciable performance improvement over K8-based Opterons, within the same power envelope.
In 2007 AMD introduced a scheme to characterize the power consumption of new processors under "average" daily usage, named
average CPU power
The thermal design power (TDP), sometimes called thermal design point, is the maximum amount of heat generated by a computer chip or component (often a CPU, GPU or system on a chip) that the cooling system in a computer is designed to dissipat ...
(ACP).
Socket FT3
The Opteron X1150 and Opteron X2150 APU are used with the BGA-769 or
Socket FT3
AMD's Socket FT3 or BGA-769 targets mobile devices and was designed for APUs codenamed ''Kabini'' and ''Temash'', ''Beema'' and ''Mullins'' (Socket FT3b).
''"Kabini"''- and ''"Temash"''-branded products combine Jaguar with Islands (GCN), UVD 3 ...
.
Features
CPUs
x86 CPU features table
APUs
APU features table
Models
For Socket 940 and Socket 939 Opterons, each chip has a three-digit model number, in the form ''Opteron XYY''. For Socket F and Socket AM2 Opterons, each chip has a four-digit model number, in the form ''Opteron XZYY''. For all first, second, and third-generation Opterons, the first digit (the X) specifies the number of CPUs on the target machine:
* 1 – Designed for
uniprocessor systems
* 2 – Designed for
dual-processor systems
* 8 – Designed for
systems with 4 or 8 processors
For Socket F and Socket AM2 Opterons, the second digit (the Z) represents the processor generation. Presently, only 2 (dual-core, DDR2), 3 (quad-core, DDR2) and 4 (six-core, DDR2) are used.
Socket C32 and G34 Opterons use a new four-digit numbering scheme. The first digit refers to the number of CPUs in the target machine:
*4 – Designed for uniprocessor and dual-processor systems.
*6 – Designed for dual-processor and four-processor systems.
Like the previous second and third generation Opterons, the second number refers to the processor generation. "1" refers to AMD K10-based units (''Magny-Cours'' and ''Lisbon''), "2" refers to the
Bulldozer
A bulldozer or dozer (also called a crawler) is a large, motorized machine equipped with a metal blade to the front for pushing material: soil, sand, snow, rubble, or rock during construction work. It travels most commonly on continuous track ...
-based ''Interlagos'', ''Valencia'', and ''Zurich''-based units, and "3" refers to the
Piledriver-based ''Abu Dhabi'', ''Seoul'', and ''Delhi''-based units.
For all Opterons, the last two digits in the model number (the YY) indicate the clock frequency of a CPU, a higher number indicating a higher clock frequency. This speed indication is comparable to processors of the same generation if they have the same amount of cores, single-cores and dual-cores have different indications despite sometimes having the same clock frequency.
The suffix HE or EE indicates a high-efficiency/energy-efficiency model having a lower
TDP than a standard Opteron. The suffix SE indicates a top-of-the-line model having a higher TDP than a standard Opteron.
Starting from 65 nm fabrication process, the Opteron codenames have been based on
Formula 1
Formula One (also known as Formula 1 or F1) is the highest class of international racing for open-wheel single-seater formula racing cars sanctioned by the Fédération Internationale de l'Automobile (FIA). The World Drivers' Championship, ...
hosting cities; AMD has a long term sponsorship with F1's most successful team,
Ferrari
Ferrari S.p.A. (; ) is an Italian luxury sports car manufacturer based in Maranello, Italy. Founded by Enzo Ferrari (1898–1988) in 1939 from the Alfa Romeo racing division as ''Auto Avio Costruzioni'', the company built its first car in ...
.
Opteron (130 nm SOI)
; Single-core – ''SledgeHammer'' (1yy, 2yy, 8yy)
* CPU-Steppings: B3, C0, CG
* L1-Cache: 64 + 64 KB (Data + Instructions)
* L2-Cache: 1024 KB, full speed
*
MMX, Extended
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of float ...
,
SSE,
SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
*
Socket 940
Socket 940 is a 940-pin socket for 64-bit AMD Opteron server processors and AMD Athlon 64 FX consumer processors. This socket is entirely square in shape and pins are arranged in a grid with the exception of four key pins used to align the process ...
,
800 MHz HyperTransport
* Registered
DDR SDRAM
Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 ...
required,
ECC possible
* VCore: 1.50 V – 1.55 V
* Max Power (TDP): 89 W
* First Release: April 22, 2003
* Clockrate: 1.4–2.4 GHz (x40 – x50)
Opteron (90 nm SOI, DDR)
; Single-core – ''Venus'' (1yy), ''Troy'' (2yy), ''Athens'' (8yy)
* CPU-Steppings: E4
* L1-Cache: 64 + 64 KB (Data + Instructions)
* L2-Cache: 1024 KB, full speed
*
MMX, Extended
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of float ...
,
SSE,
SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
*
Socket 940
Socket 940 is a 940-pin socket for 64-bit AMD Opteron server processors and AMD Athlon 64 FX consumer processors. This socket is entirely square in shape and pins are arranged in a grid with the exception of four key pins used to align the process ...
,
800 MHz HyperTransport
*
Socket 939
Socket 939 is a CPU socket released by AMD in June 2004 to supersede the previous Socket 754 for Athlon 64 processors. Socket 939 was succeeded by Socket AM2 in May 2006. It is the second socket designed for AMD's AMD64 range of processors.
Avai ...
/
Socket 940
Socket 940 is a 940-pin socket for 64-bit AMD Opteron server processors and AMD Athlon 64 FX consumer processors. This socket is entirely square in shape and pins are arranged in a grid with the exception of four key pins used to align the process ...
,
1000 MHz HyperTransport
* Registered
DDR SDRAM
Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 ...
required for socket 940,
ECC possible
* VCore: 1.35 V – 1.4 V
* Max power (TDP): 95 W
*
NX Bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
* 64-bit segment limit checks for VMware-style binary-translation virtualization.
* Optimized Power Management (OPM)
* First Release: December 2004
* Clockrate: 1.6 – 3.0 GHz (x42 – x56)
; Dual-core – ''Denmark'' (1yy), ''Italy'' (2yy), ''Egypt'' (8yy)
* CPU-Steppings: E1, E6
* First Release: April 2005
* Clockrate: 1.6–2.8 GHz (x60, x65, x70, x75, x80, x85, x90)
*
Socket 939
Socket 939 is a CPU socket released by AMD in June 2004 to supersede the previous Socket 754 for Athlon 64 processors. Socket 939 was succeeded by Socket AM2 in May 2006. It is the second socket designed for AMD's AMD64 range of processors.
Avai ...
/
Socket 940
Socket 940 is a 940-pin socket for 64-bit AMD Opteron server processors and AMD Athlon 64 FX consumer processors. This socket is entirely square in shape and pins are arranged in a grid with the exception of four key pins used to align the process ...
,
1000 MHz HyperTransport
*
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
Opteron (90 nm SOI, DDR2)
; Dual-core – ''Santa Ana'' (12yy), ''Santa Rosa'' (22yy, 82yy)
* CPU steppings: F2, F3
* L1-Cache: 64 + 64 KB (Data + Instructions)
* L2-Cache: 2 × 1024 KB, full speed
*
MMX, Extended
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of float ...
,
SSE,
SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
*
Socket F
Socket F is a CPU socket designed by Advanced Micro Devices, AMD for its Opteron line of Central processing unit, CPUs released on August 15, 2006. In 2010 Socket F was replaced by Socket C32 for entry-level servers and Socket G34 for high-end ser ...
,
1000 MHz HyperTransport – Opteron 22yy, 82yy
*
Socket AM2
The Socket AM2, renamed from Socket M2 (to prevent using the same name as Cyrix MII processors), is a CPU socket designed by AMD for desktop processors, including the performance, mainstream and value segments. It was released on May 23, 2006, as ...
,
1000 MHz HyperTransport – Opteron 12yy
* VCore: 1.35 V
* Max power (TDP): 95 W
*
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
* AMD-V
Virtualization
In computing, virtualization or virtualisation (sometimes abbreviated v12n, a numeronym) is the act of creating a virtual (rather than actual) version of something at the same abstraction level, including virtual computer hardware platforms, stor ...
* Optimized Power Management (OPM)
* First release: ?????? 2006
* Clockrate: 1.8–3.2 GHz (xx10, xx12, xx14, xx16, xx18, xx20, xx22, xx24)
Opteron (65 nm SOI)
; Quad-core – ''Barcelona'' (23xx, 83xx) 2360/8360 and below, ''Budapest'' (13yy) 1356 and below
* CPU steppings: BA, B3
* L1-Cache: 64 + 64 KB (Data + Instructions) per core
* L2-Cache: 512 KB, full speed per core
* L3-Cache: 2048 KB, shared
*
MMX, Extended
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of float ...
,
SSE,
SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
,
SSE4a
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
,
ABM
*
Socket F
Socket F is a CPU socket designed by Advanced Micro Devices, AMD for its Opteron line of Central processing unit, CPUs released on August 15, 2006. In 2010 Socket F was replaced by Socket C32 for entry-level servers and Socket G34 for high-end ser ...
,
Socket AM2+
Socket AM2+ is a CPU socket, which is the immediate successor to Socket AM2 that is used by several AMD processors such as Athlon 64 X2. Socket AM2+ is a mid-migration from Socket AM2 to Socket AM3 and both AM2+ and AM2 socket CPUs and motherboa ...
,
HyperTransport 3.0 (1.6 GHz-2 GHz)
* Registered
DDR2 SDRAM
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DDR3 ...
required,
ECC possible
* VCore: 1.2
V
* Max power (TDP): 95 Watts
*
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
* 2nd-generation AMD-V
Virtualization
In computing, virtualization or virtualisation (sometimes abbreviated v12n, a numeronym) is the act of creating a virtual (rather than actual) version of something at the same abstraction level, including virtual computer hardware platforms, stor ...
with
Rapid Virtualization Indexing Second Level Address Translation (SLAT), also known as nested paging, is a hardware-assisted virtualization technology which makes it possible to avoid the overhead associated with software-managed shadow page tables.
AMD has supported SLAT through ...
(RVI)
* Split power plane dynamic power management
* First release: September 10, 2007
* Clockrate: 1.7–2.5
GHz
The hertz (symbol: Hz) is the unit of frequency in the International System of Units (SI), equivalent to one event (or cycle) per second. The hertz is an SI derived unit whose expression in terms of SI base units is s−1, meaning that one he ...
Opteron (45 nm SOI)
; Quad-core – ''Shanghai'' (23xx, 83xx) 2370/8370 and above, ''Suzuka'' (13yy) 1381 and above
* CPU-Steppings: C2
* L3-Cache: 6 MB, shared
* Clockrate: 2.3–2.9 GHz
* HyperTransport 1.0, 3.0
* 20% reduction in idle power consumptio
* support for DDR2 800 MHz memory (Socket
* support for DDR3 1333 MHz memory (Socket AM3)
; 6-core – ''Istanbul'' (24xx, 84xx)
Released June 1, 2009.
* CPU-Steppings: D0
* L3-Cache: 6 MB, shared
* Clockrate: 2.2–2.8 GHz
* HyperTransport 3.0
* HT Assist
* support for DDR2 800 MHz memor
; 8-core – ''Magny-Cours'' MCM (6124–6140)
Released March 29, 2010.
* CPU-Steppings: D1
* Multi-chip module consisting of two quad-core dies
* L2-Cache, 8 × 512 KB
* L3-Cache: 2 × 6 MB, shared
* Clockrate: 2.0–2.6 GHz
* Four HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
* HT Assist
* support for DDR3 1333 MHz memory
*
Socket G34
Socket G34 is a land grid array CPU socket designed by AMD to support AMD's multi-chip module Opteron 6000-series server processors. G34 was launched on March 29, 2010, alongside the initial grouping of Opteron 6100 processors designed for it. S ...
; 12-core – ''Magny-Cours'' MCM (6164-6180SE)
Released March 29, 2010
* CPU-Steppings: D1
* Multi-chip module consisting of two hex-core dies
* L2-Cache, 12 × 512 KB
* L3-Cache: 2 × 6 MB, shared
* Clockrate: 1.7–2.5 GHz
* Four HyperTransport 3.1 links at 3.2 GHz (6.40 GT/s)
* HT Assist
* support for DDR3 1333 MHz memory
*
Socket G34
Socket G34 is a land grid array CPU socket designed by AMD to support AMD's multi-chip module Opteron 6000-series server processors. G34 was launched on March 29, 2010, alongside the initial grouping of Opteron 6100 processors designed for it. S ...
; Quad-core – ''Lisbon'' (4122, 4130)
Released June 23, 2010
* CPU-Steppings: D0
* L3-Cache: 6 MB
* Clockrate: 2.2 GHz (4122), 2.6 GHz (4130)
* Two HyperTransport links at 3.2 GHz (6.40 GT/s)
* HT Assist
* Support for DDR3-1333 memory
*
Socket C32
Socket C32 is a zero insertion force land grid array CPU socket designed by AMD for their single-CPU and dual-CPU Opteron 4000 series server CPUs. It is the successor to Socket AM3 for single-CPU servers and the successor for Socket F for l ...
; Hex-core – ''Lisbon'' (4162-4184)
Released June 23, 2010
* CPU-Steppings: D1
* L3-Cache: 6 MB
* Clockrate: 1.7-2.8 GHz
* Two HyperTransport links at 3.2 GHz (6.40 GT/s)
* HT Assist
* Support for DDR3-1333 memory
*
Socket C32
Socket C32 is a zero insertion force land grid array CPU socket designed by AMD for their single-CPU and dual-CPU Opteron 4000 series server CPUs. It is the successor to Socket AM3 for single-CPU servers and the successor for Socket F for l ...
Opteron (32 nm SOI) – First Generation ''Bulldozer'' Microarchitecture
;Quad-core – ''Zurich'' (3250-3260)
Released March 20, 2012.
* CPU-Steppings: B2
* Single processor
Bulldozer
A bulldozer or dozer (also called a crawler) is a large, motorized machine equipped with a metal blade to the front for pushing material: soil, sand, snow, rubble, or rock during construction work. It travels most commonly on continuous track ...
module
* L2-Cache: 2 × 2 MB
* L3-Cache: 4 MB
* Clockrate: 2.5 GHz (3250) – 2.7 GHz (3260)
* HyperTransport 3 (5.2 GT/s)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support, up to 3.5 GHz (3250), up to 3.7 GHz (3260)
* Supports uniprocessor configurations only
*
Socket AM3+
AM3+ is a modification of the AM3 Socket, released in mid-2011, designed for CPUs which use the AMD Bulldozer microarchitecture and retains compatibility with AM3 processors. The Vishera line of AMD CPUs also all use Socket AM3+. It is the last A ...
; Eight-core – ''Zurich'' (3280)
Released March 20, 2012.
* CPU-Steppings: B2
* Single processor
Bulldozer
A bulldozer or dozer (also called a crawler) is a large, motorized machine equipped with a metal blade to the front for pushing material: soil, sand, snow, rubble, or rock during construction work. It travels most commonly on continuous track ...
module
* L2-Cache: 4 × 2 MB
* L3-Cache: 8MB
* Clockrate: 2.4 GHz
* HyperTransport 3 (5.2 GT/s)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support, up to 3.5 GHz
* Supports uniprocessor configurations only
*
Socket AM3+
AM3+ is a modification of the AM3 Socket, released in mid-2011, designed for CPUs which use the AMD Bulldozer microarchitecture and retains compatibility with AM3 processors. The Vishera line of AMD CPUs also all use Socket AM3+. It is the last A ...
; 6-core – ''Valencia'' (4226-4238)
Released November 14, 2011.
* CPU-Steppings: B2
* Single die consisting of three dual-core Bulldozer modules
* L2-Cache: 6 MB
* L3-Cache: 8 MB, shared
* Clockrate: 2.7-3.3 GHz (up to 3.1-3.7 GHz with Turbo CORE)
* Two HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support
* Supports up to dual-processor configurations
*
Socket C32
Socket C32 is a zero insertion force land grid array CPU socket designed by AMD for their single-CPU and dual-CPU Opteron 4000 series server CPUs. It is the successor to Socket AM3 for single-CPU servers and the successor for Socket F for l ...
; 8-core – ''Valencia'' (4256 HE-4284)
Released November 14, 2011.
* CPU-Steppings: B2
* Single die consisting of four dual-core Bulldozer modules
* L2-Cache: 8 MB
* L3-Cache: 8 MB, shared
* Clockrate: 1.6-3.0 GHz (up to 3.0-3.7 GHz with Turbo CORE)
* Two HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support
* Supports up to dual-processor configurations
*
Socket C32
Socket C32 is a zero insertion force land grid array CPU socket designed by AMD for their single-CPU and dual-CPU Opteron 4000 series server CPUs. It is the successor to Socket AM3 for single-CPU servers and the successor for Socket F for l ...
; Quad-core – ''Interlagos'' MCM (6204)
Released November 14, 2011.
* CPU-Steppings: B2
* Multi-chip module consisting of two dies, each with one dual-core
Bulldozer
A bulldozer or dozer (also called a crawler) is a large, motorized machine equipped with a metal blade to the front for pushing material: soil, sand, snow, rubble, or rock during construction work. It travels most commonly on continuous track ...
module
* L2-Cache: 2 × 2 MB
* L3-Cache: 2 × 8 MB, shared
* Clockrate: 3.3 GHz
* HyperTransport 3 at 3.2 GHz (6.40 GT/s)
* HT Assist
* support for DDR3 1866 MHz memory
* Does not support Turbo CORE
* Supports up to quad-processor configurations
*
Socket G34
Socket G34 is a land grid array CPU socket designed by AMD to support AMD's multi-chip module Opteron 6000-series server processors. G34 was launched on March 29, 2010, alongside the initial grouping of Opteron 6100 processors designed for it. S ...
; 8-core – ''Interlagos'' (6212, 6220)
Released November 14, 2011.
* CPU-Steppings: B2
* Multi-chip module consisting of two dies, each with two dual-core Bulldozer modules
* L2-Cache: 2 × 4 MB
* L3-Cache: 2 × 8 MB, shared
* Clockrate: 2.6, 3.0 GHz (up to 3.2 and 3.6 GHz with Turbo CORE)
* Four HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support
* Supports up to quad-processor configurations
*
Socket G34
Socket G34 is a land grid array CPU socket designed by AMD to support AMD's multi-chip module Opteron 6000-series server processors. G34 was launched on March 29, 2010, alongside the initial grouping of Opteron 6100 processors designed for it. S ...
; 12-core – ''Interlagos'' (6234, 6238)
Released November 14, 2011.
* CPU-Steppings: B2
* Multi-chip module consisting of two dies, each with three dual-core Bulldozer modules
* L2-Cache: 2 × 6 MB
* L3-Cache: 2 × 8 MB, shared
* Clockrate: 2.4, 2.6 GHz (up to 3.1 and 3.3 GHz with Turbo CORE)
* Four HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support
* Supports up to quad-processor configurations
*
Socket G34
Socket G34 is a land grid array CPU socket designed by AMD to support AMD's multi-chip module Opteron 6000-series server processors. G34 was launched on March 29, 2010, alongside the initial grouping of Opteron 6100 processors designed for it. S ...
; 16-core – ''Interlagos'' (6262 HE-6284 SE)
Released November 14, 2011.
* CPU-Steppings: B2
* Multi-chip module consisting of two dies, each with four dual-core Bulldozer modules
* L2-Cache: 2 × 8 MB
* L3-Cache: 2 × 8 MB, shared
* Clockrate: 1.6-2.7 GHz (up to 2.9-3.5 GHz with Turbo CORE)
* Four HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support
* Supports up to quad-processor configurations
*
Socket G34
Socket G34 is a land grid array CPU socket designed by AMD to support AMD's multi-chip module Opteron 6000-series server processors. G34 was launched on March 29, 2010, alongside the initial grouping of Opteron 6100 processors designed for it. S ...
Opteron (32 nm SOI) – ''Piledriver'' microarchitecture
;Quad-core – ''Delhi'' (3320 EE, 3350 HE)
Released December 4, 2012.
* CPU-Steppings: C0
* Single die consisting of two
Piledriver modules
* L2-Cache: 2 × 2 MB
* L3-Cache: 8 MB, shared
* Clockrate: 1.9 GHz (3320 EE) – 2.8 GHz (3350 HE)
* 1 × HyperTransport 3 (5.2 GT/s per link)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support, up to 2.5 GHz (3320 EE), up to 3.8 GHz (3350 HE)
* Supports uniprocessor configurations only
*
Socket AM3+
AM3+ is a modification of the AM3 Socket, released in mid-2011, designed for CPUs which use the AMD Bulldozer microarchitecture and retains compatibility with AM3 processors. The Vishera line of AMD CPUs also all use Socket AM3+. It is the last A ...
;Eight-core – ''Delhi'' (3380)
Released December 4, 2012.
* CPU-Steppings: C0
* Single die consisting of four
Piledriver modules
* L2-Cache: 4 × 2 MB
* L3-Cache: 8 MB, shared
* Clockrate: 2.6 GHz
* 1 × HyperTransport 3 (5.2 GT/s per link)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support, pp to 3.6 GHz
* Supports uniprocessor configurations only
*
Socket AM3+
AM3+ is a modification of the AM3 Socket, released in mid-2011, designed for CPUs which use the AMD Bulldozer microarchitecture and retains compatibility with AM3 processors. The Vishera line of AMD CPUs also all use Socket AM3+. It is the last A ...
; 4-core – ''Seoul'' (4310 EE)
Released December 4, 2012
* CPU-Steppings: C0
* Single die consisting of two
Piledriver modules
* L2-Cache: 2 × 2 MB
* L3-Cache: 8 MB, shared
* Clockrate: 2.2 GHz
* 2 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support, up to 3.0 GHz
* Supports up to dual-processor configurations
*
Socket C32
Socket C32 is a zero insertion force land grid array CPU socket designed by AMD for their single-CPU and dual-CPU Opteron 4000 series server CPUs. It is the successor to Socket AM3 for single-CPU servers and the successor for Socket F for l ...
; 6-core – ''Seoul'' (4332 HE – 4340)
Released December 4, 2012
* CPU-Steppings: C0
* Single die consisting of three
Piledriver modules
* L2-Cache: 3 × 2 MB
* L3-Cache: 8 MB, shared
* Clockrate: 3.0 GHz (4332 HE) – 3.5 GHz (4340)
* 2 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support, from 3.5 GHz (4334) to 3.8 GHz (4340)
* Supports up to dual-processor configurations
*
Socket C32
Socket C32 is a zero insertion force land grid array CPU socket designed by AMD for their single-CPU and dual-CPU Opteron 4000 series server CPUs. It is the successor to Socket AM3 for single-CPU servers and the successor for Socket F for l ...
; 8-core – ''Seoul'' (4376 HE and above)
Released December 4, 2012
* CPU-Steppings: C0
* Single die consisting of four
Piledriver modules
* L2-Cache: 4 × 2 MB
* L3-Cache: 8 MB, shared
* Clockrate: 2.6 GHz (4376 HE) – 3.1 GHz (4386)
* 2 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support, from 3.6 GHz (4376 HE) to 3.8 GHz (4386)
* Supports up to dual-processor configurations
*
Socket C32
Socket C32 is a zero insertion force land grid array CPU socket designed by AMD for their single-CPU and dual-CPU Opteron 4000 series server CPUs. It is the successor to Socket AM3 for single-CPU servers and the successor for Socket F for l ...
; Quad-core – ''Abu Dhabi'' MCM (6308)
Released November 5, 2012.
* CPU-Steppings: C0
* Multi-chip module consisting of two dies, each with one
Piledriver module
* L2-Cache: 2 MB per die (4 MB total)
* L3-Cache: 2 × 8 MB, shared within each die
* Clockrate: 3.5 GHz
* 4 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
* HT Assist
* support for DDR3 1866 MHz memory
* Does not support Turbo CORE
* Supports up to quad-processor configurations
*
Socket G34
Socket G34 is a land grid array CPU socket designed by AMD to support AMD's multi-chip module Opteron 6000-series server processors. G34 was launched on March 29, 2010, alongside the initial grouping of Opteron 6100 processors designed for it. S ...
; Eight-core – ''Abu Dhabi'' MCM (6320, 6328)
Released November 5, 2012.
* CPU-Steppings: C0
* Multi-chip module consisting of two dies, each with two
Piledriver module
* L2-Cache: 2 × 2 MB per die (8 MB total)
* L3-Cache: 2 × 8 MB, shared within each die
* Clockrate: 2.8 GHz (6320) – 3.2 GHz (6328)
* 4 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support, from 3.3 GHz (6320) to 3.8 GHz (6328)
* Supports up to quad-processor configurations
*
Socket G34
Socket G34 is a land grid array CPU socket designed by AMD to support AMD's multi-chip module Opteron 6000-series server processors. G34 was launched on March 29, 2010, alongside the initial grouping of Opteron 6100 processors designed for it. S ...
; 12-core – ''Abu Dhabi'' MCM (6344, 6348)
Released November 5, 2012.
* CPU-Steppings: C0
* Multi-chip module consisting of two dies, each with three
Piledriver module
* L2-Cache: 3 × 2 MB per die (12 MB total)
* L3-Cache: 2 × 8 MB, shared within each die
* Clockrate: 2.6 GHz (6344) – 2.8 GHz (6348)
* 4 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support, from 3.2 GHz (6344) to 3.4 GHz (6348)
* Supports up to quad-processor configurations
*
Socket G34
Socket G34 is a land grid array CPU socket designed by AMD to support AMD's multi-chip module Opteron 6000-series server processors. G34 was launched on March 29, 2010, alongside the initial grouping of Opteron 6100 processors designed for it. S ...
; 16-core – ''Abu Dhabi'' MCM (6366 HE and above)
Released November 5, 2012.
* CPU-Steppings: C0
* Multi-chip module consisting of two dies, each with four
Piledriver module
* L2-Cache: 4 × 2 MB per die (16 MB total)
* L3-Cache: 2 × 8 MB, shared within each die
* Clockrate: 1.8 GHz (6366 HE) – 2.8 GHz (6386 SE)
* 4 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
* HT Assist
* support for DDR3 1866 MHz memory
* Turbo CORE support, from 3.1 GHz (6366 HE) to 3.5 GHz (6386 SE)
* Supports up to quad-processor configurations
*
Socket G34
Socket G34 is a land grid array CPU socket designed by AMD to support AMD's multi-chip module Opteron 6000-series server processors. G34 was launched on March 29, 2010, alongside the initial grouping of Opteron 6100 processors designed for it. S ...
Opteron X (28 nm bulk) – ''Jaguar'' microarchitecture
;Quad-core – ''Kyoto'' (X1150)
Released May 29, 2013
* Single SoC with one
Jaguar (microarchitecture), Jaguar module and integrated I/O
* Configurable CPU frequency and
TDP
* L2 Cache: 2MB shared
* CPU frequency: 1.0–2.0
GHz
The hertz (symbol: Hz) is the unit of frequency in the International System of Units (SI), equivalent to one event (or cycle) per second. The hertz is an SI derived unit whose expression in terms of SI base units is s−1, meaning that one he ...
* Max. TDP: 9–17W
* Support for DDR3-1600 memory
*
Socket FT3
AMD's Socket FT3 or BGA-769 targets mobile devices and was designed for APUs codenamed ''Kabini'' and ''Temash'', ''Beema'' and ''Mullins'' (Socket FT3b).
''"Kabini"''- and ''"Temash"''-branded products combine Jaguar with Islands (GCN), UVD 3 ...
;Quad-core APU – ''Kyoto'' (X2150)
Released May 29, 2013
* Single SoC with one
Jaguar (microarchitecture), Jaguar module, integrated
GCN GPU and I/O
* Configurable CPU/GPU frequency and
TDP
* L2 Cache: 2MB shared
* CPU frequency: 1.1–1.9
GHz
The hertz (symbol: Hz) is the unit of frequency in the International System of Units (SI), equivalent to one event (or cycle) per second. The hertz is an SI derived unit whose expression in terms of SI base units is s−1, meaning that one he ...
* GPU frequency: 266–600
MHz
The hertz (symbol: Hz) is the unit of frequency in the International System of Units (SI), equivalent to one event (or cycle) per second. The hertz is an SI derived unit whose expression in terms of SI base units is s−1, meaning that one he ...
* GPU cores: 128
* Max. TDP: 11–22W
* Support for DDR3-1600 memory
*
Socket FT3
AMD's Socket FT3 or BGA-769 targets mobile devices and was designed for APUs codenamed ''Kabini'' and ''Temash'', ''Beema'' and ''Mullins'' (Socket FT3b).
''"Kabini"''- and ''"Temash"''-branded products combine Jaguar with Islands (GCN), UVD 3 ...
Opteron A (28 nm) – ''ARM Cortex-A57'' ARM microarchitecture
A1100-series
The Opteron A1100-series "Seattle" (28 nm) are SoCs based on
ARM Cortex-A57
The ARM Cortex-A57 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A57 is an out-of-order superscalar pipeline. It is available as SIP core to licensees, and its design makes ...
cores that use the
ARMv8-A
ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer (RISC) instruction set architectures for computer processors, configured ...
instruction set. They were first released in January 2016.
* Cores: 4–8
* Frequency: 1.7–2.0 GHz
* L2 Cache: 2 MB (4 core) or 4 MB (8 core)
* L3 Cache: 8 MB
* Thermal Design Power: 25 W (4 core) or 32 W (8 core)
* Up to 64 GB DDR3L-1600 and up to 128GB DDR4-1866 with ECC
* SoC peripherals include 14 × SATA 3, 2 × integrated 10 GbE LAN, and eight PCI Express lanes in ×8, ×4, and ×2 configurations
Opteron X (28 nm bulk) – ''Excavator'' microarchitecture
Released June, 2017
;Dual-core – ''Toronto'' (X3216)
* L2-Cache: 1 MB
* CPU frequency: 1.6 GHz
* Turbo CORE support, 3.0 GHz
* GPU frequency: 800 MHz
* TDP: 12-15W
* support for DDR4 1600 MHz memory
;Quad-core – ''Toronto'' (X3418 & X3421)
* L2-Cache: 2 × 1 MB
* CPU frequency: 1.8 GHz - 2.1 GHz
* Turbo CORE support, 3.2 GHz - 3.4 GHz
* GPU frequency: 800 MHz
* TDP: 12-35W
* support for DDR4 2400 MHz memory
Supercomputers
Opteron processors first appeared in the top 100 systems of the
fastest supercomputers in the world list in the early 2000s. By the summer of 2006, 21 of the top 100 systems used Opteron processors, and in the November 2010 and June 2011 lists the Opteron reached its maximum representation of 33 of the top 100 systems. The number of Opteron-based systems decreased fairly rapidly after this peak, falling to 3 of the top 100 systems by November 2016, and in November 2017 only one Opteron-based system remained.
Several supercomputers using only Opteron processors were ranked in the top 10 systems between 2003 and 2015, notably:
* Red Storm –
Sandia National Laboratories
Sandia National Laboratories (SNL), also known as Sandia, is one of three research and development laboratories of the United States Department of Energy's National Nuclear Security Administration (NNSA). Headquartered in Kirtland Air Force Ba ...
– system in November 2006.
* Jaguar –
Oak Ridge National Laboratory
Oak Ridge National Laboratory (ORNL) is a U.S. multiprogram science and technology national laboratory sponsored by the U.S. Department of Energy (DOE) and administered, managed, and operated by UT–Battelle as a federally funded research and ...
– various configurations held top 10 positions between 2005 and 2011, including in November 2009 and June 2010.
* Ranger –
Texas Advanced Computing Center
The Texas Advanced Computing Center (TACC) at the University of Texas at Austin, United States, is an advanced computing research center that provides comprehensive advanced computing resources and support services to researchers in Texas and acr ...
– system in June 2008.
* Kraken –
National Institute for Computational Sciences
The National Institute for Computational Sciences (NICS) is funded by the National Science Foundation and managed by the University of Tennessee. NICS was home to Kraken, the most powerful computer in the world managed by academia. The NICS petas ...
– system in November 2009.
* Hopper –
National Energy Research Scientific Computing Center
The National Energy Research Scientific Computing Center (NERSC), is a high-performance computing (supercomputer) National User Facility operated by Lawrence Berkeley National Laboratory for the United States Department of Energy Office of Scien ...
– system in November 2010.
Other top 10 systems using a combination of Opteron processors and
compute accelerators have included:
*
IBM Roadrunner
Roadrunner was a supercomputer built by IBM for the Los Alamos National Laboratory in New Mexico, USA. The US$100-million Roadrunner was designed for a peak performance of 1.7 petaflops. It achieved 1.026 petaflops on May 25, 2008, to become the ...
–
Los Alamos National Laboratory
Los Alamos National Laboratory (often shortened as Los Alamos and LANL) is one of the sixteen research and development laboratories of the United States Department of Energy (DOE), located a short distance northwest of Santa Fe, New Mexico, ...
– system in 2008. Composed of Opteron processors with IBM
PowerXCell 8i
Cell is a multi-core microprocessor microarchitecture that combines a general-purpose PowerPC core of modest performance with streamlined coprocessing elements which greatly accelerate multimedia and vector processing applications, as well as ...
co-processors.
The only system remaining on the list (as of November 2017), also using Opteron processors combined with compute accelerators:
*
Titan (supercomputer)
Titan or OLCF-3 was a supercomputer built by Cray at Oak Ridge National Laboratory for use in a variety of science projects. Titan was an upgrade of Jaguar, a previous supercomputer at Oak Ridge, that uses graphics processing units (GPUs) in a ...
–
Oak Ridge National Laboratory
Oak Ridge National Laboratory (ORNL) is a U.S. multiprogram science and technology national laboratory sponsored by the U.S. Department of Energy (DOE) and administered, managed, and operated by UT–Battelle as a federally funded research and ...
– system in 2012, as of November 2017. Composed of Opteron processors with
Nvidia
Nvidia CorporationOfficially written as NVIDIA and stylized in its logo as VIDIA with the lowercase "n" the same height as the uppercase "VIDIA"; formerly stylized as VIDIA with a large italicized lowercase "n" on products from the mid 1990s to ...
Fermi (microarchitecture)
Fermi is the codename for a graphics processing unit (GPU) microarchitecture developed by Nvidia, first released to retail in April 2010, as the successor to the Tesla microarchitecture. It was the primary microarchitecture used in the GeForce ...
GPU-based accelerators.
Issues
Opteron without Optimized Power Management
AMD released some Opteron processors without Optimized Power Management (OPM) support, which use DDR memory. The following table describes those processors without OPM.
Opteron recall (2006)
AMD recalled some E4 stepping-revision single-core Opteron processors, including ×52 (2.6 GHz) and ×54 (2.8 GHz) models which use DDR memory. The following table describes affected processors, as listed in AMD Opteron ×52 and ×54 Production Notice of 2006.
[
]
The affected processors may produce inconsistent results if three specific conditions occur simultaneously:
* The execution of floating point-intensive code sequences
* Elevated processor temperatures
* Elevated ambient temperatures
A software verification tool for identifying the AMD Opteron processors listed in the above table that may be affected under these specific conditions is available, only to AMD
OEM
An original equipment manufacturer (OEM) is generally perceived as a company that produces non-aftermarket parts and equipment that may be marketed by another manufacturer. It is a common industry term recognized and used by many professional or ...
partners. AMD will replace those processors at no charge.
Recognition
In the February 2010 issue of ''
Custom PC
''Custom PC'' (usually abbreviated to 'CPC') is a UK-based computer magazine created by Mr Freelance Limited, and originally published by Dennis Publishing Ltd. It's aimed at PC hardware enthusiasts, covering topics such as modding, overcloc ...
'' (a UK-based computing magazine focused on PC hardware), the AMD Opteron 144 (released in Summer 2005) appeared in the "Hardware Hall of Fame". It was described as "The best overclocker's CPU ever made" due to its low cost and ability to run at speeds far beyond its stock speed. (According to ''Custom PC'', it could run at "close to 3 GHz on air".)
See also
*
List of AMD Opteron microprocessors
Opteron is the name of a central processing unit (CPU) family within the AMD64 line. Designed by Advanced Micro Devices (AMD) for the server market, Opteron competed with Intel's Xeon. The Opteron family is succeeded by the Zen-based Epyc, and ...
*
TDP power cap
References
External links
Official Opteron homepageAMD Technical DocsAMD K8 Opteron technical specificationsAMD K8 Dual Core Opteron technical specificationsComparison between Xeon and Opteron processor performance
AMD: dual-core Opteron to 3 GHz
{{AMD CPU sockets
AMD x86 microprocessors
64-bit microprocessors