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ARM (stylised in lowercase as arm, previously an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of
reduced instruction set computing In computer engineering Computer engineering (CoE or CpE) is a branch of engineering Engineering is the use of scientific principles to design and build machines, structures, and other items, including bridges, tunnels, roads, v ...
(RISC) architectures for
computer processors
computer processors
, configured for various environments. Arm Ltd. develops the architecture and licenses it to other companies, who design their own products that implement one of those architecturesincluding systems-on-chips (SoC) and systems-on-modules (SoM) that incorporate different components such as memory, interfaces, and
radios Radio is the technology of signaling and telecommunication, communicating using radio waves. Radio waves are electromagnetic waves of frequency between 30 hertz (Hz) and 300 gigahertz (GHz). They are generated by an electronic device ...
. It also designs cores that implement this
instruction set In computer science Computer science deals with the theoretical foundations of information, algorithms and the architectures of its computation as well as practical techniques for their application. Computer science is the study of co ...
and licenses these designs to a number of companies that incorporate those core designs into their own products. There have been several generations of the ARM design. The original ARM1 used a
32-bit 32-bit microcomputer A microcomputer is a small, relatively inexpensive computer with a microprocessor as its central processing unit (CPU). It includes a microprocessor, Computer memory, memory and minimal input/output (I/O) circuitry mount ...
internal structure but had a 26-bit
address space In computing Computing is any goal-oriented activity requiring, benefiting from, or creating computing machinery. It includes the study and experimentation of algorithm of an algorithm (Euclid's algorithm) for calculating the greatest common ...
that limited it to 64 MB of
main memory Computer data storage is a technology consisting of computer A computer is a machine that can be programmed to Execution (computing), carry out sequences of arithmetic or logical operations automatically. Modern computers can perform ...
. This limitation was removed in the ARMv3 series, which has a 32-bit address space, and several additional generations up to ARMv7 remained 32-bit. Released in 2011, the ARMv8-A architecture added support for a
64-bit In computer architecture, 64-bit Integer (computer science), integers, Memory address, memory addresses, or other Data#Uses%20of%20data%20in%20computing, data units are those that are 64 bits (8 Octet (computing), octets) wide. Also, 64-bit cent ...
address space and 64-bit arithmetic with its new 32-bit fixed-length instruction set. Arm Ltd. has also released a series of additional instruction sets for different rules; the "Thumb" extension adds both 32- and 16-bit instructions for improved
code density In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ' ...
, while
Jazelle Jazelle DBX (direct bytecode execution) is an extension that allows some ARM In human anatomy, the arm is the part of the upper limb The upper Limb (anatomy), limbs or upper extremities are the forelimbs of an upright posture, upright-postured te ...
added instructions for directly handling
Java bytecode Java bytecode is the bytecode Bytecode, also termed portable code or p-code, is a form of instruction set In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A dev ...

Java bytecode
s, and more recently,
JavaScript JavaScript (), often abbreviated JS, is a programming language A programming language is a formal language In mathematics Mathematics (from Ancient Greek, Greek: ) includes the study of such topics as quantity (number theory), ma ...

JavaScript
. More recent changes include the addition of
simultaneous multithreading Simultaneous multithreading (SMT) is a technique for improving the overall efficiency of superscalar Processor board of a CRAY T3e supercomputer with four ''superscalar'' Alpha 21164 processors A superscalar processor is a Central processing ...
(SMT) for improved performance or
fault tolerance Fault tolerance is the property that enables a system A system is a group of interacting Interaction is a kind of action that occurs as two or more objects have an effect upon one another. The idea of a two-way effect is essential in the ...
. Due to their low costs, minimal power consumption, and lower heat generation than their competitors, ARM processors are desirable for light, portable, battery-powered devicesincluding
smartphone A smartphone is a portable device A mobile device (or handheld computer) is a computer A computer is a machine that can be programmed to carry out sequences of arithmetic or logical operations automatically. Modern computers can per ...

smartphone
s,
laptop A laptop, laptop computer, or notebook computer is a small, portable personal computer File:Crystal Project computer.png, upright=0.9, An artist's depiction of a 2000s-era desktop-style personal computer, which includes a metal case with ...

laptop
s and
tablet computer A tablet computer, commonly shortened to tablet, is a mobile device A mobile device (or handheld computer) is a computer A computer is a machine that can be programmed to carry out sequences of arithmetic or logical operations aut ...
s, as well as other
embedded system An embedded system is a computer system A computer is a machine that can be programmed to carry out Sequence, sequences of arithmetic or logical operations automatically. Modern computers can perform generic sets of operations known as Co ...
s."Some facts about the Acorn RISC Machine"
posting to comp.arch, 2 November 1988. Retrieved 25 May 2007.
However, ARM processors are also used for
desktops A desktop traditionally refers to: * The surface of a desk (often to distinguish office appliances that fit on a desk, such as photocopiers and printers, from larger equipment covering its own area on the floor) Desktop may refer to various comput ...
and
server Server may refer to: Computing *Server (computing) In computing Computing is any goal-oriented activity requiring, benefiting from, or creating computing machinery. It includes the study and experimentation of algorithmic processes and dev ...
s, including the world's fastest
supercomputer upright=1.5, Computing power of the top 1 supercomputer each year, measured in FLOPS A supercomputer is a computer with a high level of performance as compared to a general-purpose computer. The performance of a supercomputer is commonly mea ...

supercomputer
. With over 180 billion ARM chips produced, , ARM is the most widely used
instruction set architecture In computer science Computer science deals with the theoretical foundations of information, algorithms and the architectures of its computation as well as practical techniques for their application. Computer science is the study of , ...
(ISA) and the ISA produced in the largest quantity. Currently, the widely used Cortex
core Core or cores may refer to: Science and technology * Core (anatomy) In common parlance, the core of the body is broadly considered to be the torso. Functional movements are highly dependent on this part of the body, and lack of core muscular dev ...
s, older "classic" cores, and specialised SecurCore cores variants are available for each of these to include or exclude optional capabilities.


History


BBC Micro

Acorn Computers Acorn Computers Ltd. was a British computer company established in Cambridge, England, in 1978. The company produced a number of computers which were especially popular in the United Kingdom, UK, including the Acorn Electron and the Acorn Archim ...
' first widely successful design was the
BBC Micro The British Broadcasting Corporation Microcomputer System, or BBC Micro, is a series of microcomputer A microcomputer is a small, relatively inexpensive computer A computer is a machine that can be programmed to carry out sequences of ...
, introduced in December 1981. This was a relatively conventional machine based on the
MOS 6502 The MOS Technology 6502 (typically pronounced "sixty-five-oh-two" or "six-five-oh-two") William Mensch and the moderator both pronounce the 6502 microprocessor as ''"sixty-five-oh-two"''. is an 8-bit In computer architecture In computer ...
CPU but ran at roughly double the performance of competing designs like the
Apple II The Apple II (stylized as apple ] '') is an 8-bit home computer">8-bit.html" ;"title="'') is an 8-bit">'') is an 8-bit home computer and one of the world's first highly successful mass-produced microcomputer products. It was designed primari ...

Apple II
due to its use of faster
DRAM Dynamic random-access memory (dynamic RAM or DRAM) is a type of random-access Random access (more precisely and more generally called direct access) is the ability to access an arbitrary element of a sequence in equal time or any datum fr ...

DRAM
. Typical DRAM of the era ran at about 2 MHz; Acorn arranged a deal with
Hitachi () is a Japanese multinational Multinational may refer to: * Multinational corporation, a corporate organization operating in multiple countries * Multinational force, a military body from multiple countries * Multinational state, a sovereign ...

Hitachi
for a supply of faster 4 MHz parts. Machines of the era generally shared memory between the processor and the
framebuffer A framebuffer (frame buffer, or sometimes framestore) is a portion of random-access memory 8GB DDR3 RAM stick with a white Heat sink">heatsink File:Laptop Heatsink.jpg, 330px, Typical heatsink-fan combination found on a consumer laptop. T ...
, which allowed the processor to quickly update the contents of the screen without having to perform separate
input/output In computing, input/output (I/O, or informally io or IO) is the communication between an information processing system, such as a computer, and the outside world, possibly a human or another information processing system. Information, Inputs are ...
(I/O). However, as the timing of the video display is exacting, the video hardware had to have fast access to that memory. Due to a quirk of the 6502's design, the CPU left the memory untouched for of the time. Thus by running the CPU at 1 MHz, the video system could read data during those down times, taking up the total 2 MHz of the RAM. In the BBC Micro, the use of 4 MHz RAM allowed the same technique to be used, but running at twice the speed. This allowed it to outperform any similar machine on the market.


Acorn Business Computer

1981 was also the year that the
IBM PC The IBM Personal Computer (model 5150, commonly known as the IBM PC) is the first computer released in the IBM PC model line and the basis for the IBM PC compatible IBM PC compatible computers are similar to the original IBM PC The IBM ...

IBM PC
was introduced. Using the recently introduced
Intel 8088 The Intel 8088 ("''eighty-eighty-eight''", also called iAPX 88) microprocessor is a variant of the Intel 8086. Introduced on June 1, 1979, the 8088 has an eight-bit external data bus In computer architecture In computer engineering, comput ...
, a
16-bit 16-bit microcomputer A microcomputer is a small, relatively inexpensive computer A computer is a machine that can be programmed to carry out sequences of arithmetic or logical operations automatically. Modern computers can perform gener ...
CPU compared to the 6502's
8-bit In computer architecture, 8-bit integer (computer science), integers or other data#Uses of data in computing, data units are those that are 8 bits wide (1 octet). Also, 8-bit central processing unit, CPU and arithmetic logic unit, ALU arch ...
design, it was able to offer higher overall performance. Its introduction changed the computer market radically; what had been largely a hobby and gaming market emerging over the last five years began to change to a must-have business item where the earlier 8-bit designs simply couldn't compete. Even newer designs running at
32-bit 32-bit microcomputer A microcomputer is a small, relatively inexpensive computer with a microprocessor as its central processing unit (CPU). It includes a microprocessor, Computer memory, memory and minimal input/output (I/O) circuitry mount ...
were coming to market as well, like the
Motorola 68000 The Motorola 68000 (sometimes shortened to Motorola 68k or m68k and usually pronounced "sixty-eight-thousand") is a 16/32-bit complex instruction set computer A complex instruction set computer (CISC ) is a computer in which single instructi ...
and National Semiconductor NS32016. Acorn began considering how to compete in this market and produced a new paper design known as the
Acorn Business Computer The Acorn Business Computer (ABC) was a series of microcomputer A microcomputer is a small, relatively inexpensive computer A computer is a machine that can be programmed to carry out sequences of arithmetic or logical operations automati ...
. They set themselves the goal of producing a machine with ten times the performance of the BBC Micro, but at the same price point. This would outperform and underprice the PC. At the same time, the recent introduction of the
Apple Lisa Lisa is a desktop computer A desktop computer is a personal computer File:Crystal Project computer.png, upright=0.9, An artist's depiction of a 2000s-era desktop-style personal computer, which includes a metal case with the computing co ...

Apple Lisa
brought the
Xerox Star The Xerox Star workstation A workstation is a special computer designed for technical or scientific applications. Intended primarily to be used by one person at a time, they are commonly connected to a local area network A local area net ...
's concept to a wider audience and suggested the future belonged to machines with a
graphical user interface The graphical user interface (GUI "UI" by itself is still usually pronounced . or ) is a form of user interface In the industrial design Industrial design is a process of design A design is a plan or specification for the construction ...
. The Lisa, however, cost $9,995, as it was packed with support chips, large amounts of memory and a
hard drive A hard disk drive (HDD), hard disk, hard drive, or fixed disk is an electro-mechanical data storage device On a reel-to-reel tape recorder (Sony TC-630), the recorder is data storage equipment and the magnetic tape is a data stora ...
, all very expensive at that time. The engineers then began studying all of the CPU designs available. Their conclusion about the existing 16-bit designs was that they were a lot more expensive and were still "a bit crap", offering only slightly higher performance than their BBC Micro design. They also almost always demanded a large number of support chips to operate even at that level, which drove up the cost of the computer as a whole. These systems would simply not hit the design goal. They also considered the new 32-bit designs, but these were even more expensive and had the same issues with support chips. According to
Sophie Wilson Sophie Mary Wilson (born June 1957) is an English , who helped design the and . Wilson first designed a microcomputer during a break from studies at . She subsequently joined and was instrumental in designing the BBC Micro, including the ...

Sophie Wilson
, all the processors tested at that time performed about the same, with about a 4 Mbit/second bandwidth. Two key events led Acorn down the path to ARM. One was the publication of a series of reports from the
University of California, Berkeley The University of California, Berkeley (UC Berkeley, Berkeley, Cal, or California) is a public In public relations Public relations (PR) is the practice of managing and disseminating information from an individual or an organization ...

University of California, Berkeley
, which suggested that a simple chip design could nevertheless have extremely high performance, much higher than the latest 32-bit designs on the market. The second was a visit by
Steve Furber Stephen Byram Furber (born 21 March 1953) is a British computer scientist, mathematician and hardware engineer, currently the International Computers Limited, ICL Professor of Computer Engineering in the Department of Computer Science, Univers ...

Steve Furber
and Sophie Wilson to the
Western Design Center The Western Design Center (WDC), located in Mesa, Arizona Mesa ( ) is a city in Maricopa County Maricopa County is located in the south-central part of the U.S. state In the United States The United States of America (USA), co ...
, a company run by
Bill Mensch William (Bill) David Mensch, Jr. (born February 9, 1945), is an American electrical engineer born in Quakertown, Pennsylvania. He was a major contributor to the design of the Motorola 6800 8-bit microprocessor A microprocessor is a compu ...
and his sister, which had become the logical successor to the MOS team and was offering new versions like the
WDC 65C02 The Western Design Center (WDC) 65C02 microprocessor is an enhanced CMOS version of the popular NMOS logic, nMOS-based 8-bit MOS Technology 6502. The 65C02 fixed several problems in the original 6502 and added some new instructions, but its main ...
. The Acorn team saw high school students producing chip layouts on Apple II machines, which suggested that anyone could do it. In contrast, a visit to another design firm working on modern 32-bit CPU revealed a team with over a dozen members which were already on revision H of their design and yet it still contained bugs. This cemented their late 1983 decision to begin their own CPU design, the Acorn RISC Machine.


Design concepts

The original
Berkeley RISC Berkeley RISC is one of two seminal research projects into reduced instruction set computer In computer engineering Computer engineering (CoE or CpE) is a branch of engineering that integrates several fields of computer science and elec ...
designs were in some sense teaching systems, not designed specifically for outright performance. To its basic register-heavy concept, ARM added a number of the well-received design notes of the 6502. Primary among them was the ability to quickly serve
interrupt In digital computer A computer is a machine A machine is a man-made device that uses power to apply forces and control movement to perform an action. Machines can be driven by animals and people A people is a plurality of pe ...

interrupt
s, which allowed the machines to offer reasonable
input/output In computing, input/output (I/O, or informally io or IO) is the communication between an information processing system, such as a computer, and the outside world, possibly a human or another information processing system. Information, Inputs are ...
performance without any additional external hardware. To offer similar high-performance interrupts as the 6502, the ARM design limited its physical
address space In computing Computing is any goal-oriented activity requiring, benefiting from, or creating computing machinery. It includes the study and experimentation of algorithm of an algorithm (Euclid's algorithm) for calculating the greatest common ...
to 24-bits of 4-byte words, so 26-bits of bytes, or 64 MB. This 24-bit size allowed the
program counter The program counter (PC), commonly called the instruction pointer (IP) in Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, Santa Clara, California. It is the wo ...
(PC) to be stored along with eight processor flags in a single 32-bit register. That meant that on the reception of an interrupt, the entire machine state could be saved in a single operation, whereas had the PC been a full 32-bits it would require separate operations to store it and the status flags. Another change, and among the most important in terms of practical real-world performance, was the modification of the
instruction set In computer science Computer science deals with the theoretical foundations of information, algorithms and the architectures of its computation as well as practical techniques for their application. Computer science is the study of co ...
to take advantage of
page mode DRAM photograph of the Micron Technology Micron Technology, Inc. is an American producer of computer memory and computer data storage including dynamic random-access memory, flash memory Flash memory is an electronic non-volatile ...
. Recently introduced, page mode allowed subsequent accesses of memory to run twice as fast if they were roughly in the same location, or "page". Berkeley's design did not consider page mode, and treated all memory equally. The ARM design added special vector-like memory access instructions, the "S-cycles", that could be used to fill or save multiple registers in a single page using page mode. This doubled memory performance when they could be used and was especially important for graphics performance. The Berkeley RISC designs used
register window In computer engineering Computer engineering (CoE or CpE) is a branch of engineering Engineering is the use of scientific method, scientific principles to design and build machines, structures, and other items, including bridges, tunn ...

register window
s to reduce the number of register saves and restores performed in procedure calls; the ARM design did not adopt this. Wilson developed the instruction set, writing a simulation of the processor in BBC BASIC that ran on a BBC Micro with a second 6502 processor. This convinced Acorn engineers they were on the right track. Wilson approached Acorn's CEO,
Hermann Hauser Hermann Maria Hauser, Order of the British Empire, KBE, Fellow of the Royal Society, FRS, Royal Academy of Engineering, FREng, FInstP, Chartered Physicist, CPhys (born 1948) is an Austrian-born entrepreneur who is primarily associated with the ...

Hermann Hauser
, and requested more resources. Hauser gave his approval and assembled a small team to design the actual processor based on Wilson's ISA. The official Acorn RISC Machine project started in October 1983.


ARM1

Acorn chose
VLSI Technology VLSI Technology, Inc., was a company that designed and manufactured custom and semi-custom integrated circuit An integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a microchip) is a set of electronic ...
as the "silicon partner", as they were a source of ROMs and custom chips for Acorn. Acorn provided the design and VLSI provided the layout and production. The first samples of ARM silicon worked properly when first received and tested on 26 April 1985. Known as ARM1, these versions ran at 6 MHz. The first ARM application was as a second processor for the BBC Micro, where it helped in developing simulation software to finish development of the support chips (VIDC, IOC, MEMC), and sped up the
CAD software Computer-aided design (CAD) is the use of computers (or ) to aid in the creation, modification, analysis, or optimization of a design. CAD software is used to increase the productivity of the designer, improve the quality of design, improve commu ...
used in ARM2 development. Wilson subsequently rewrote
BBC BASIC BBC BASIC is a version of the BASIC programming language released in 1981 as the native programming language for the BBC Micro home/personal computer, providing a standardized language for a UK computer literacy project of the BBC. It was writt ...
in ARM assembly language. The in-depth knowledge gained from designing the instruction set enabled the code to be very dense, making ARM BBC BASIC an extremely good test for any ARM emulator.


ARM2

The result of the simulations on the ARM1 boards led to the late 1986 introduction of the ARM2 design running at 8 MHz, and the early 1987 speed-bumped version at 10 to 12 MHz. A significant change in the underlying architecture was the addition of a Booth multiplier, whereas previously multiplication had to be carried out in software. Additionally, a new Fast Interrupt reQuest mode, FIQ for short, allowed registers 8 through 14 to be replaced as part of the interrupt itself. This meant FIQ requests did not have to save out their registers, further speeding interrupts. The ARM2 was roughly seven times the performance of a typical 7 MHz 68000-based system like the
Commodore Amiga The Amiga is a family of personal computer A personal computer (PC) is a multi-purpose computer whose size, capabilities, and price make it feasible for individual use. Personal computers are intended to be operated directly by an end user ...

Commodore Amiga
or
Macintosh SE The Macintosh SE is a personal computer File:Crystal Project computer.png, upright=0.9, An artist's depiction of a 2000s-era desktop-style personal computer, which includes a metal case with the computing components, a display monitor and a ...

Macintosh SE
. It was twice as fast as a
Intel 80386 The Intel 386, originally released as 80386 and later renamed i386, is a 32-bit microprocessor introduced in 1985. The first versions had 275,000 transistorsVAX-11/784
supermini The B-segment is the 2nd category of the European segments for passenger cars, which is described as "small cars". It is equivalent to the subcompact Subcompact car is a North American Car classification, classification for cars smaller than ...
. The only systems that beat it were the
Sun SPARC SPARC (Scalable Processor Architecture) is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system develop ...
and
MIPS R2000 The R2000 is a 32-bit 32-bit microcomputer A microcomputer is a small, relatively inexpensive computer A computer is a machine that can be programmed to carry out sequences of arithmetic or logical operations automatically. Modern comp ...
RISC-based
workstation A workstation is a special computer designed for technical or computational science, scientific applications. Intended primarily to be used by one person at a time, they are commonly connected to a local area network and run multi-user operating ...

workstation
s. Further, as the CPU was designed for high-speed I/O, it dispensed with many of the support chips seen in these machines, notably, it lacked any dedicated
direct memory access Direct memory access (DMA) is a feature of computer systems that allows certain hardware subsystems to access main system memory Memory is the faculty of the by which or is , stored, and retrieved when needed. It is the retention of inform ...
(DMA) controller which was often found on workstations. The graphics system was also simplified based on the same set of underlying assumptions about memory and timing. The result was a dramatically simplified design, offering performance on par with expensive workstations but at a price point similar to contemporary desktops. The ARM2 featured a
32-bit 32-bit microcomputer A microcomputer is a small, relatively inexpensive computer with a microprocessor as its central processing unit (CPU). It includes a microprocessor, Computer memory, memory and minimal input/output (I/O) circuitry mount ...
data bus In computer architecture In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer A computer is a machine that can be programmed to carry ...
,
26-bit In computer architecture In computer engineering Computer engineering (CoE or CpE) is a branch of engineering Engineering is the use of scientific method, scientific principles to design and build machines, structures, and other i ...
address space and 27 32-bit registers. The ARM2 had a
transistor count upright=1.4, gate File:Kebun Raya Bali Candi Bentar IMG 8794.jpg, Candi bentar, a typical Indonesian gate that is often found on the islands of Java and Bali A gate or gateway is a point of entry to or from a space enclosed by walls. The w ...

transistor count
of just 30,000, compared to Motorola's six-year-older 68000 model with around 40,000. Much of this simplicity came from the lack of
microcode In processor design Processor design is a subfield of computer engineering and electronics engineering (fabrication) that deals with creating a processor (computing), processor, a key component of computer hardware. The design process involves ch ...
(which represents about one-quarter to one-third of the 68000) and from (like most CPUs of the day) not including any
cache Cache, caching, or caché may refer to: Places * Cache (Aosta) Cache is a frazione of the city of Aosta, in the Aosta Valley region of Italy. Frazioni of Aosta Valley Aosta {{Aosta-geo-stub ..., a frazione in Italy * Cache Creek (disambig ...
. This simplicity enabled low power consumption, yet better performance than the
Intel 80286 The Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is the ...

Intel 80286
. A successor, ARM3, was produced with a 4  KB cache, which further improved performance. The address bus was extended to 32 bits in the ARM6, but program code still had to lie within the first 64  MB of memory in 26-bit compatibility mode, due to the reserved bits for the status flags.


Advanced RISC Machines Ltd. – ARM6

In the late 1980s,
Apple Computer Apple Inc. is an American multinational Multinational may refer to: * Multinational corporation, a corporate organization operating in multiple countries * Multinational force, a military body from multiple countries * Multinational state, ...
and
VLSI Technology VLSI Technology, Inc., was a company that designed and manufactured custom and semi-custom integrated circuit An integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a microchip) is a set of electronic ...
started working with Acorn on newer versions of the ARM core. In 1990, Acorn spun off the design team into a new company named Advanced RISC Machines Ltd., which became ARM Ltd. when its parent company,
Arm Holdings Arm Ltd. (stylized as arm) is a Great Britain, British semiconductor and Computer software, software design company based in Cambridge, England. Its primary business is in the design of ARM architecture, ARM Central processing unit, processors ...
plc, floated on the
London Stock Exchange London Stock Exchange (LSE) is a stock exchange A stock exchange, securities exchange, or bourse is an exchange Exchange may refer to: Places United States * Exchange, Indiana Exchange is an Unincorporated area, unincorporated community ...
and
NASDAQ The Nasdaq Stock Market () is an American stock exchange A stock exchange, securities exchange, or bourse is an exchange Exchange may refer to: Places United States * Exchange, Indiana Exchange is an Unincorporated area, unincorpora ...
in 1998. The new Apple-ARM work would eventually evolve into the ARM6, first released in early 1992. Apple used the ARM6-based ARM610 as the basis for their
Apple Newton The Newton is a series of personal digital assistants (PDAs) developed and marketed by Apple Computer, Inc. An early device in the PDA category (the Newton originated the term), it was the first to feature handwriting recognition. Apple starte ...

Apple Newton
PDA.


Early licensees

In 1994, Acorn used the ARM610 as the main
central processing unit A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuit 200px, A circuit built on a printed circuit board (PCB). An electronic circuit is composed of individual electroni ...

central processing unit
(CPU) in their
RiscPC The Risc PC is 's / computer, launched on 15 April 1994, which superseded the . The Acorn PC card and software allows software to be run. Like the Archimedes, the Risc PC continues the practice of having the RISC OS in a module. Risc PC augm ...
computers. DEC licensed the ARMv4 architecture and produced the
StrongARM The StrongARM is a family of computer microprocessor A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit An integrated circuit or monolithic integrated c ...
. At 233 
MHz The hertz (symbol: Hz) is the derived unit of frequency Frequency is the number of occurrences of a repeating event per unit of time. It is also referred to as temporal frequency, which emphasizes the contrast to spatial frequency and an ...

MHz
, this CPU drew only one watt (newer versions draw far less). This work was later passed to Intel as part of a lawsuit settlement, and Intel took the opportunity to supplement their
i960 Intel's i960 (or 80960) was a RISC-based microprocessor design that became popular during the early 1990s as an embedded system, embedded microcontroller. It became a best-selling CPU in that segment, along with the competing AMD 29000. In spite ...
line with the StrongARM. Intel later developed its own high performance implementation named XScale, which it has since sold to Marvell. Transistor count of the ARM core remained essentially the same throughout these changes; ARM2 had 30,000 transistors, while ARM6 grew only to 35,000.


Market share

In 2005, about 98% of all mobile phones sold used at least one ARM processor. In 2010, producers of chips based on ARM architectures reported shipments of 6.1 billion ARM-based processors, representing 95% of
smartphone A smartphone is a portable device A mobile device (or handheld computer) is a computer A computer is a machine that can be programmed to carry out sequences of arithmetic or logical operations automatically. Modern computers can per ...

smartphone
s, 35% of
digital television Digital television (DTV) is the transmission of television audiovisual Audiovisual (AV) is electronic media 200px, Graphical representations of electrical audio data. Electronic media uses either analog (red) or digital (blue) signal pr ...
s and set-top boxes and 10% of mobile computers. In 2011, the 32-bit ARM architecture was the most widely used architecture in mobile devices and the most popular 32-bit one in embedded systems. In 2013, 10 billion were produced and "ARM-based chips are found in nearly 60 percent of the world's mobile devices".


Licensing


Core licence

Arm Ltd.'s primary business is selling IP cores, which licensees use to create microcontrollers (MCUs), CPUs, and system on a chip, systems-on-chips based on those cores. The original design manufacturer combines the ARM core with other parts to produce a complete device, typically one that can be built in existing semiconductor fabrication plants (fabs) at low cost and still deliver substantial performance. The most successful implementation has been the ARM7#ARM7TDMI, ARM7TDMI with hundreds of millions sold. Atmel has been a precursor design center in the ARM7TDMI-based embedded system. The ARM architectures used in smartphones, PDAs and other mobile devices range from ARMv5 to ARMv8-A. In 2009, some manufacturers introduced netbooks based on ARM architecture CPUs, in direct competition with netbooks based on Intel Atom. Arm Ltd. offers a variety of licensing terms, varying in cost and deliverables. Arm Ltd. provides to all licensees an integratable hardware description of the ARM core as well as complete software development toolset (compiler, debugger, software development kit) and the right to sell manufactured Semiconductor device, silicon containing the ARM CPU. SoC packages integrating ARM's core designs include Nvidia Tegra's first three generations, CSR plc's Quatro family, ST-Ericsson's Nova and NovaThor, Silicon Labs's Precision32 MCU, Texas Instruments's OMAP products, Samsung's Hummingbird and Exynos products, Apple's Apple A4, A4, Apple A5, A5, and Apple A5X, A5X, and NXP Semiconductors, NXP's i.MX. Fabless manufacturing, Fabless licensees, who wish to integrate an ARM core into their own chip design, are usually only interested in acquiring a ready-to-manufacture verified semiconductor intellectual property core. For these customers, Arm Ltd. delivers a netlist, gate netlist description of the chosen ARM core, along with an abstracted simulation model and test programs to aid design integration and verification. More ambitious customers, including integrated device manufacturers (IDM) and foundry operators, choose to acquire the processor IP in logic synthesis, synthesizable register-transfer level, RTL (Verilog) form. With the synthesizable RTL, the customer has the ability to perform architectural level optimisations and extensions. This allows the designer to achieve exotic design goals not otherwise possible with an unmodified netlist (Clock rate, high clock speed, very low power consumption, instruction set extensions, etc.). While Arm Ltd. does not grant the licensee the right to resell the ARM architecture itself, licensees may freely sell manufactured product such as chip devices, evaluation boards and complete systems. Foundry model, Merchant foundries can be a special case; not only are they allowed to sell finished silicon containing ARM cores, they generally hold the right to re-manufacture ARM cores for other customers. Arm Ltd. prices its IP based on perceived value. Lower performing ARM cores typically have lower licence costs than higher performing cores. In implementation terms, a synthesisable core costs more than a hard macro (blackbox) core. Complicating price matters, a merchant foundry that holds an ARM licence, such as Samsung or Fujitsu, can offer fab customers reduced licensing costs. In exchange for acquiring the ARM core through the foundry's in-house design services, the customer can reduce or eliminate payment of ARM's upfront licence fee. Compared to dedicated semiconductor foundries (such as TSMC and United Microelectronics Corporation, UMC) without in-house design services, Fujitsu/Samsung charge two- to three-times more per manufactured Wafer (electronics), wafer. For low to mid volume applications, a design service foundry offers lower overall pricing (through subsidisation of the licence fee). For high volume mass-produced parts, the long term cost reduction achievable through lower wafer pricing reduces the impact of ARM's NRE (Non-Recurring Engineering) costs, making the dedicated foundry a better choice. Companies that have developed chips with cores designed by Arm Holdings include Amazon.com's Annapurna Labs subsidiary, Analog Devices, Apple Inc., Apple, AppliedMicro (now: MACOM Technology Solutions), Atmel, Broadcom, Cavium, Cypress Semiconductor, Freescale Semiconductor (now NXP Semiconductors), Huawei, Intel, Maxim Integrated, Nvidia, NXP, Qualcomm, Renesas Electronics, Renesas, Samsung Electronics, ST Microelectronics, Texas Instruments and Xilinx.


Built on ARM Cortex Technology licence

In February 2016, ARM announced the Built on ARM Cortex Technology licence, often shortened to Built on Cortex (BoC) licence. This licence allows companies to partner with ARM and make modifications to ARM Cortex designs. These design modifications will not be shared with other companies. These semi-custom core designs also have brand freedom, for example Kryo#Kryo 280, Kryo 280. Companies that are current licensees of Built on ARM Cortex Technology include Qualcomm.


Architectural licence

Companies can also obtain an ARM ''architectural licence'' for designing their own CPU cores using the ARM instruction sets. These cores must comply fully with the ARM architecture. Companies that have designed cores that implement an ARM architecture include Apple, AppliedMicro (now: Ampere Computing), Broadcom, Cavium (now: Marvell), Digital Equipment Corporation, Intel, Nvidia, Qualcomm, Samsung Electronics, Fujitsu and NUVIA Inc.


ARM Flexible Access

On 16 July 2019, ARM announced ARM Flexible Access. ARM Flexible Access provides unlimited access to included ARM intellectual property (IP) for development. Per product licence fees are required once customers reaches foundry tapeout or prototyping. 75% of ARM's most recent IP over the last two years are included in ARM Flexible Access. As of October 2019: * CPUs: ARM Cortex-A5, Cortex-A5, ARM Cortex-A7, Cortex-A7, ARM Cortex-A32, Cortex-A32, ARM Cortex-A34, Cortex-A34, ARM Cortex-A35, Cortex-A35, ARM Cortex-A53, Cortex-A53, ARM Cortex-R5, Cortex-R5, ARM Cortex-R8, Cortex-R8, ARM Cortex-R52, Cortex-R52, ARM Cortex-M0, Cortex-M0, ARM Cortex-M0+, Cortex-M0+, ARM Cortex-M3, Cortex-M3, ARM Cortex-M4, Cortex-M4, ARM Cortex-M#Cortex-M7, Cortex-M7, ARM Cortex-M#Cortex-M23, Cortex-M23, ARM Cortex-M#Cortex-M33, Cortex-M33 * GPUs: Mali (GPU), Mali-G52, Mali (GPU), Mali-G31. Includes Mali Driver Development Kits (DDK). * Interconnect: CoreLink NIC-400, CoreLink NIC-450, CoreLink CCI-400, CoreLink CCI-500, CoreLink CCI-550, ADB-400 AMBA, XHB-400 AXI-AHB * System Controllers: CoreLink GIC-400, CoreLink GIC-500, PL192 VIC, BP141 TrustZone Memory Wrapper, CoreLink TZC-400, CoreLink L2C-310, CoreLink MMU-500, BP140 Memory Interface * Security IP: CryptoCell-312, CryptoCell-712, TrustZone True Random Number Generator * Peripheral Controllers: PL011 UART, PL022 SPI, PL031 RTC * Debug & Trace: CoreSight SoC-400, CoreSight SDC-600, CoreSight STM-500, CoreSight System Trace Macrocell, CoreSight Trace Memory Controller * Design Kits: Corstone-101, Corstone-201 * Physical IP: Artisan PIK for Cortex-M33 TSMC 22ULL including memory compilers, logic libraries, GPIOs and documentation * Tools & Materials: Socrates IP ToolingARM Design Studio, Virtual System Models * Support: Standard ARM Technical support, ARM online training, maintenance updates, credits towards onsite training and design reviews


Cores

Arm Holdings provides a list of vendors who implement ARM cores in their design (application specific standard products (ASSP), microprocessor and microcontrollers).


Example applications of ARM cores

ARM cores are used in a number of products, particularly PDAs and
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s. Some computing examples are Microsoft's Surface (2012 tablet), first generation Surface, Surface 2 and Pocket PC devices (following Pocket PC 2002, 2002), Apple Inc., Apple's iPads and Asus's Asus Eee Pad Transformer, Eee Pad Transformer
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s, and several Chromebook laptops. Others include Apple's iPhone
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s and iPod portable media players, Canon PowerShot digital cameras, Nintendo Switch hybrid and Nintendo 3DS, 3DS handheld game consoles, and TomTom turn-by-turn GPS navigation device, navigation systems. In 2005, Arm Holdings took part in the development of Manchester University's computer SpiNNaker, which used ARM cores to simulate the human brain. ARM chips are also used in Raspberry Pi, BeagleBoard, BeagleBone, PandaBoard and other single-board computers, because they are very small, inexpensive and consume very little power.


32-bit architecture

The 32-bit ARM architecture, such as ARMv7-A (implementing AArch32; see #ARMv8-A, section on ARMv8-A for more on it), was the most widely used architecture in mobile devices . Since 1995, the ''ARM Architecture Reference Manual'' has been the primary source of documentation on the ARM processor architecture and instruction set, distinguishing interfaces that all ARM processors are required to support (such as instruction semantics) from implementation details that may vary. The architecture has evolved over time, and version seven of the architecture, ARMv7, defines three architecture "profiles": * A-profile, the "Application" profile, implemented by 32-bit cores in the ARM Cortex-A, Cortex-A series and by some non-ARM cores * R-profile, the "Real-time" profile, implemented by cores in the ARM Cortex-R, Cortex-R series * M-profile, the "Microcontroller" profile, implemented by most cores in the ARM Cortex-M, Cortex-M series Although the architecture profiles were first defined for ARMv7, ARM subsequently defined the ARMv6-M architecture (used by the Cortex ARM Cortex-M0, M0/ARM Cortex-M0+, M0+/ARM Cortex-M1, M1) as a subset of the ARMv7-M profile with fewer instructions.


CPU modes

Except in the M-profile, the 32-bit ARM architecture specifies several CPU modes, depending on the implemented architecture features. At any moment in time, the CPU can be in only one mode, but it can switch modes due to external events (interrupts) or programmatically. * ''User mode:'' The only non-privileged mode. * ''FIQ mode:'' A privileged mode that is entered whenever the processor accepts a fast interrupt request. * ''IRQ mode:'' A privileged mode that is entered whenever the processor accepts an interrupt. * ''Supervisor (svc) mode:'' A privileged mode entered whenever the CPU is reset or when an SVC instruction is executed. * ''Abort mode:'' A privileged mode that is entered whenever a prefetch abort or data abort exception occurs. * ''Undefined mode:'' A privileged mode that is entered whenever an undefined instruction exception occurs. * ''System mode (ARMv4 and above):'' The only privileged mode that is not entered by an exception. It can only be entered by executing an instruction that explicitly writes to the mode bits of the Current Program Status Register (CPSR) from another privileged mode (not from user mode). * ''Monitor mode (ARMv6 and ARMv7 Security Extensions, ARMv8 EL3):'' A monitor mode is introduced to support TrustZone extension in ARM cores. * ''Hyp mode (ARMv7 Virtualization Extensions, ARMv8 EL2):'' A hypervisor mode that supports Popek and Goldberg virtualization requirements for the non-secure operation of the CPU. * ''Thread mode (ARMv6-M, ARMv7-M, ARMv8-M):'' A mode which can be specified as either privileged or unprivileged. Whether the Main Stack Pointer (MSP) or Process Stack Pointer (PSP) is used can also be specified in CONTROL register with privileged access. This mode is designed for user tasks in RTOS environment but it's typically used in bare-metal for super-loop. * ''Handler mode (ARMv6-M, ARMv7-M, ARMv8-M):'' A mode dedicated for exception handling (except the RESET which are handled in Thread mode). Handler mode always uses MSP and works in privileged level.


Instruction set

The original (and subsequent) ARM implementation was hardwired without
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, like the much simpler
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MOS Technology 6502, 6502 processor used in prior Acorn microcomputers. The 32-bit ARM architecture (and the 64-bit architecture for the most part) includes the following RISC features: * Load/store architecture. * No support for Data structure alignment, unaligned memory accesses in the original version of the architecture. ARMv6 and later, except some microcontroller versions, support unaligned accesses for half-word and single-word load/store instructions with some limitations, such as no guaranteed Linearizability, atomicity. * Uniform 16 × 32-bit register file (including the program counter, stack pointer and the link register). * Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased
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. Later, the #Thumb, Thumb instruction set added 16-bit instructions and increased code density. * Mostly single clock-cycle execution. To compensate for the simpler design, compared with processors like the Intel 80286 and Motorola 68020, some additional design features were used: * Conditional execution of most instructions reduces branch overhead and compensates for the lack of a branch predictor in early chips. * Arithmetic instructions alter Condition Code Register, condition codes only when desired. * 32-bit barrel shifter can be used without performance penalty with most arithmetic instructions and address calculations. * Has powerful indexed addressing modes. * A link register supports fast leaf function calls. * A simple, but fast, 2-priority-level
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subsystem has switched register banks.


Arithmetic instructions

ARM includes integer arithmetic operations for add, subtract, and multiply; some versions of the architecture also support divide operations. ARM supports 32-bit × 32-bit multiplies with either a 32-bit result or 64-bit result, though Cortex-M0 / M0+ / M1 cores don't support 64-bit results.Cortex-M0 r0p0 Technical Reference Manual; Arm Holdings.
/ref> Some ARM cores also support 16-bit × 16-bit and 32-bit × 16-bit multiplies. The divide instructions are only included in the following ARM architectures: * ARMv7-M and ARMv7E-M architectures always include divide instructions. * ARMv7-R architecture always includes divide instructions in the Thumb instruction set, but optionally in its 32-bit instruction set. * ARMv7-A architecture optionally includes the divide instructions. The instructions might not be implemented, or implemented only in the Thumb instruction set, or implemented in both the Thumb and ARM instruction sets, or implemented if the Virtualization Extensions are included.


Registers

Registers R0 through R7 are the same across all CPU modes; they are never banked. Registers R8 through R12 are the same across all CPU modes except FIQ mode. FIQ mode has its own distinct R8 through R12 registers. R13 and R14 are banked across all privileged CPU modes except system mode. That is, each mode that can be entered because of an exception has its own R13 and R14. These registers generally contain the stack pointer and the return address from function calls, respectively. Aliases: * R13 is also referred to as SP, the Stack register, Stack Pointer. * R14 is also referred to as LR, the Link register, Link Register. * R15 is also referred to as PC, the Program Counter. The Current Program Status Register (CPSR) has the following 32 bits. * M (bits 0–4) is the processor mode bits. * T (bit 5) is the Thumb state bit. * F (bit 6) is the FIQ disable bit. * I (bit 7) is the IRQ disable bit. * A (bit 8) is the imprecise data abort disable bit. * E (bit 9) is the data endianness bit. * IT (bits 10–15 and 25–26) is the if-then state bits. * GE (bits 16–19) is the greater-than-or-equal-to bits. * DNM (bits 20–23) is the do not modify bits. * J (bit 24) is the Java state bit. * Q (bit 27) is the sticky overflow bit. * V (bit 28) is the overflow bit. * C (bit 29) is the carry/borrow/extend bit. * Z (bit 30) is the zero bit. * N (bit 31) is the negative/less than bit.


Conditional execution

Almost every ARM instruction has a conditional execution feature called Branch predication, predication, which is implemented with a 4-bit condition code selector (the predicate). To allow for unconditional execution, one of the four-bit codes causes the instruction to be always executed. Most other CPU architectures only have condition codes on branch instructions. Though the predicate takes up four of the 32 bits in an instruction code, and thus cuts down significantly on the encoding bits available for displacements in memory access instructions, it avoids branch instructions when generating code for small conditional (programming), if statements. Apart from eliminating the branch instructions themselves, this preserves the fetch/decode/execute pipeline at the cost of only one cycle per skipped instruction. An algorithm that provides a good example of conditional execution is the subtraction-based Euclidean algorithm for computing the greatest common divisor. In the C (programming language), C programming language, the algorithm can be written as: int gcd(int a, int b) The same algorithm can be rewritten in a way closer to target ARM Instruction set architecture, instructions as: loop: // Compare a and b GT = a > b; LT = a < b; NE = a != b; // Perform operations based on flag results if(GT) a -= b; // Subtract *only* if greater-than if(LT) b -= a; // Subtract *only* if less-than if(NE) goto loop; // Loop *only* if compared values were not equal return a; and coded in assembly language as: ; assign a to register r0, b to r1 loop: CMP r0, r1 ; set condition "NE" if (a != b), ; "GT" if (a > b), ; or "LT" if (a < b) SUBGT r0, r0, r1 ; if "GT" (Greater Than), a = a-b; SUBLT r1, r1, r0 ; if "LT" (Less Than), b = b-a; BNE loop ; if "NE" (Not Equal), then loop B lr ; if the loop is not entered, we can safely return which avoids the branches around the then and else clauses. If r0 and r1 are equal then neither of the SUB instructions will be executed, eliminating the need for a conditional branch to implement the while check at the top of the loop, for example had SUBLE (less than or equal) been used. One of the ways that Thumb code provides a more dense encoding is to remove the four-bit selector from non-branch instructions.


Other features

Another feature of the
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is the ability to fold shifts and rotates into the "data processing" (arithmetic, logical, and register-register move) instructions, so that, for example, the C statement a += (j << 2); could be rendered as a single-word, single-cycle instruction: ADD Ra, Ra, Rj, LSL #2 This results in the typical ARM program being denser than expected with fewer memory accesses; thus the pipeline is used more efficiently. The ARM processor also has features rarely seen in other RISC architectures, such as Program counter, PC-relative addressing (indeed, on the 32-bit ARM the Program counter, PC is one of its 16 registers) and pre- and post-increment addressing modes. The ARM instruction set has increased over time. Some early ARM processors (before ARM7TDMI), for example, have no instruction to store a two-byte quantity.


Pipelines and other implementation issues

The ARM7 and earlier implementations have a three-stage Pipeline (computing), pipeline; the stages being fetch, decode and execute. Higher-performance designs, such as the ARM9, have deeper pipelines: Cortex-A8 has thirteen stages. Additional implementation changes for higher performance include a faster Adder (electronics), adder and more extensive branch prediction logic. The difference between the ARM7DI and ARM7DMI cores, for example, was an improved multiplier; hence the added "M".


Coprocessors

The ARM architecture (pre-ARMv8) provides a non-intrusive way of extending the instruction set using "coprocessors" that can be addressed using MCR, MRC, MRRC, MCRR and similar instructions. The coprocessor space is divided logically into 16 coprocessors with numbers from 0 to 15, coprocessor 15 (cp15) being reserved for some typical control functions like managing the caches and Memory management unit, MMU operation on processors that have one. In ARM-based machines, peripheral devices are usually attached to the processor by mapping their physical registers into ARM memory space, into the coprocessor space, or by connecting to another device (a bus) that in turn attaches to the processor. Coprocessor accesses have lower latency, so some peripherals—for example, an XScale interrupt controller—are accessible in both ways: through memory and through coprocessors. In other cases, chip designers only integrate hardware using the coprocessor mechanism. For example, an image processing engine might be a small ARM7TDMI core combined with a coprocessor that has specialised operations to support a specific set of HDTV transcoding primitives.


Debugging

All modern ARM processors include hardware debugging facilities, allowing software debuggers to perform operations such as halting, stepping, and breakpointing of code starting from reset. These facilities are built using JTAG support, though some newer cores optionally support ARM's own two-wire "SWD" protocol. In ARM7TDMI cores, the "D" represented JTAG debug support, and the "I" represented presence of an "EmbeddedICE" debug module. For ARM7 and ARM9 core generations, EmbeddedICE over JTAG was a de facto debug standard, though not architecturally guaranteed. The ARMv7 architecture defines basic debug facilities at an architectural level. These include breakpoints, watchpoints and instruction execution in a "Debug Mode"; similar facilities were also available with EmbeddedICE. Both "halt mode" and "monitor" mode debugging are supported. The actual transport mechanism used to access the debug facilities is not architecturally specified, but implementations generally include JTAG support. There is a separate ARM "CoreSight" debug architecture, which is not architecturally required by ARMv7 processors.


Debug Access Port

The Debug Access Port (DAP) is an implementation of an ARM Debug Interface. There are two different supported implementations, the Serial Wire JTAG Debug Port (SWJ-DP) and the Serial Wire Debug Port (SW-DP). CMSIS-DAP is a standard interface that describes how various debugging software on a host PC can communicate over USB to firmware running on a hardware debugger, which in turn talks over SWD or JTAG to a CoreSight-enabled ARM Cortex CPU.


DSP enhancement instructions

To improve the ARM architecture for digital signal processing and multimedia applications, DSP instructions were added to the set. These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ architectures. E-variants also imply T, D, M, and I. The new instructions are common in digital signal processor (DSP) architectures. They include variations on signed multiply–accumulate operation, multiply–accumulate, saturated add and subtract, and count leading zeros.


SIMD extensions for multimedia

Introduced in the ARMv6 architecture, this was a precursor to Advanced SIMD, also known as #Advanced SIMD (Neon), Neon.


Jazelle

Jazelle DBX (Direct Bytecode eXecution) is a technique that allows
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to be executed directly in the ARM architecture as a third execution state (and instruction set) alongside the existing ARM and Thumb-mode. Support for this state is signified by the "J" in the ARMv5TEJ architecture, and in ARM9EJ-S and ARM7EJ-S core names. Support for this state is required starting in ARMv6 (except for the ARMv7-M profile), though newer cores only include a trivial implementation that provides no hardware acceleration.


Thumb

To improve compiled code-density, processors since the ARM7TDMI (released in 1994) have featured the ''Thumb'' instruction set, which have their own state. (The "T" in "TDMI" indicates the Thumb feature.) When in this state, the processor executes the Thumb instruction set, a compact 16-bit encoding for a subset of the ARM instruction set. Most of the Thumb instructions are directly mapped to normal ARM instructions. The space-saving comes from making some of the instruction operands implicit and limiting the number of possibilities compared to the ARM instructions executed in the ARM instruction set state. In Thumb, the 16-bit opcodes have less functionality. For example, only branches can be conditional, and many opcodes are restricted to accessing only half of all of the CPU's general-purpose registers. The shorter opcodes give improved code density overall, even though some operations require extra instructions. In situations where the memory port or bus width is constrained to less than 32 bits, the shorter Thumb opcodes allow increased performance compared with 32-bit ARM code, as less program code may need to be loaded into the processor over the constrained memory bandwidth. Unlike processor architectures with variable length (16- or 32-bit) instructions, such as the Cray-1 and
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SuperH, the ARM and Thumb instruction sets exist independently of each other. Embedded hardware, such as the Game Boy Advance, typically have a small amount of RAM accessible with a full 32-bit datapath; the majority is accessed via a 16-bit or narrower secondary datapath. In this situation, it usually makes sense to compile Thumb code and hand-optimise a few of the most CPU-intensive sections using full 32-bit ARM instructions, placing these wider instructions into the 32-bit bus accessible memory. The first processor with a Thumb instruction decoder was the ARM7TDMI. All ARM9 and later families, including XScale, have included a Thumb instruction decoder. It includes instructions adopted from the Hitachi SuperH (1992), which was licensed by ARM. ARM's smallest processor families (Cortex M0 and M1) implement only the 16-bit Thumb instruction set for maximum performance in lowest cost applications.


Thumb-2

''Thumb-2'' technology was introduced in the ''ARM1156 core'', announced in 2003. Thumb-2 extends the limited 16-bit instruction set of Thumb with additional 32-bit instructions to give the instruction set more breadth, thus producing a variable-length instruction set. A stated aim for Thumb-2 was to achieve code density similar to Thumb with performance similar to the ARM instruction set on 32-bit memory. Thumb-2 extends the Thumb instruction set with bit-field manipulation, table branches and conditional execution. At the same time, the ARM instruction set was extended to maintain equivalent functionality in both instruction sets. A new "Unified Assembly Language" (UAL) supports generation of either Thumb or ARM instructions from the same source code; versions of Thumb seen on ARMv7 processors are essentially as capable as ARM code (including the ability to write interrupt handlers). This requires a bit of care, and use of a new "IT" (if-then) instruction, which permits up to four successive instructions to execute based on a tested condition, or on its inverse. When compiling into ARM code, this is ignored, but when compiling into Thumb it generates an actual instruction. For example: ; if (r0

r1) CMP r0, r1 ITE EQ ; ARM: no code ... Thumb: IT instruction ; then r0 = r2; MOVEQ r0, r2 ; ARM: conditional; Thumb: condition via ITE 'T' (then) ; else r0 = r3; MOVNE r0, r3 ; ARM: conditional; Thumb: condition via ITE 'E' (else) ; recall that the Thumb MOV instruction has no bits to encode "EQ" or "NE".
All ARMv7 chips support the Thumb instruction set. All chips in the Cortex-A series, Cortex-R series, and ARM11 series support both "ARM instruction set state" and "Thumb instruction set state", while chips in the ARM Cortex-M, Cortex-M series support only the Thumb instruction set.


Thumb Execution Environment (ThumbEE)

''ThumbEE'' (erroneously called ''Thumb-2EE'' in some ARM documentation), which was marketed a
Jazelle RCT
(Runtime Compilation Target), was announced in 2005, first appearing in the ''Cortex-A8'' processor. ThumbEE is a fourth instruction set state, making small changes to the Thumb-2 extended instruction set. These changes make the instruction set particularly suited to code generated at runtime (e.g. by Just-in-time compilation, JIT compilation) in managed ''Execution Environments''. ThumbEE is a target for languages such as Java (programming language), Java, C Sharp (programming language), C#, Perl, and Python (programming language), Python, and allows JIT compilers to output smaller compiled code without impacting performance. New features provided by ThumbEE include automatic null pointer checks on every load and store instruction, an instruction to perform an array bounds check, and special instructions that call a handler. In addition, because it utilises Thumb-2 technology, ThumbEE provides access to registers r8-r15 (where the Jazelle/DBX Java VM state is held). Handlers are small sections of frequently called code, commonly used to implement high level languages, such as allocating memory for a new object. These changes come from repurposing a handful of opcodes, and knowing the core is in the new ThumbEE state. On 23 November 2011, Arm Holdings deprecated any use of the ThumbEE instruction set, and ARMv8 removes support for ThumbEE.


Floating-point (VFP)

''VFP'' (Vector Floating Point) technology is an floating-point unit (FPU) coprocessor extension to the ARM architecture (implemented differently in ARMv8 – coprocessors not defined there). It provides low-cost single precision floating-point format, single-precision and double precision floating-point format, double-precision floating-point computation fully compliant with the ''IEEE 754, ANSI/IEEE Std 754-1985 Standard for Binary Floating-Point Arithmetic''. VFP provides floating-point computation suitable for a wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture was intended to support execution of short "vector mode" instructions but these operated on each vector element sequentially and thus did not offer the performance of true SIMD, single instruction, multiple data (SIMD) vector parallelism. This vector mode was therefore removed shortly after its introduction, to be replaced with the much more powerful Advanced SIMD, also known as #Advanced SIMD (Neon), Neon. Some devices such as the ARM Cortex-A8 have a cut-down ''VFPLite'' module instead of a full VFP module, and require roughly ten times more clock cycles per float operation. Pre-ARMv8 architecture implemented floating-point/SIMD with the coprocessor interface. Other floating-point and/or SIMD units found in ARM-based processors using the coprocessor interface include Floating Point Accelerator, FPA, FPE, MMX (instruction set), iwMMXt, some of which were implemented in software by trapping but could have been implemented in hardware. They provide some of the same functionality as VFP but are not opcode-compatible with it. FPA10 also provides extended precision, but implements correct rounding (required by IEEE 754) only in single precision. ; VFPv1: Obsolete ; VFPv2:An optional extension to the ARM instruction set in the ARMv5TE, ARMv5TEJ and ARMv6 architectures. VFPv2 has 16 64-bit FPU registers. ; VFPv3 or VFPv3-D32:Implemented on most Cortex-A8 and A9 ARMv7 processors. It is backwards compatible with VFPv2, except that it cannot trap floating-point exceptions. VFPv3 has 32 64-bit FPU registers as standard, adds VCVT instructions to convert between scalar, float and double, adds immediate mode to VMOV such that constants can be loaded into FPU registers. ; VFPv3-D16: As above, but with only 16 64-bit FPU registers. Implemented on Cortex-R4 and R5 processors and the Tegra, Tegra 2 (Cortex-A9). ; VFPv3-F16: Uncommon; it supports Half-precision floating-point format, IEEE754-2008 half-precision (16-bit) floating point as a storage format. ; VFPv4 or VFPv4-D32:Implemented on Cortex-A12 and A15 ARMv7 processors, Cortex-A7 optionally has VFPv4-D32 in the case of an FPU with Neon. VFPv4 has 32 64-bit FPU registers as standard, adds both half-precision support as a storage format and Fused multiply–add, fused multiply-accumulate instructions to the features of VFPv3. ; VFPv4-D16: As above, but it has only 16 64-bit FPU registers. Implemented on Cortex-A5 and A7 processors in the case of an FPU without Neon. ; VFPv5-D16-M: Implemented on Cortex-M7 when single and double-precision floating-point core option exists. In Debian GNU/Linux, and derivatives such as Ubuntu (operating system), Ubuntu and Linux Mint, armhf (ARM hard float) refers to the ARMv7 architecture including the additional VFP3-D16 floating-point hardware extension (and Thumb-2) above. Software packages and cross-compiler tools use the armhf vs. arm/armel suffixes to differentiate.


Advanced SIMD (Neon)

The ''Advanced SIMD'' extension (aka ''Neon'' or "MPE" Media Processing Engine) is a combined 64- and 128-bit SIMD instruction set that provides standardised acceleration for media and signal processing applications. Neon is included in all Cortex-A8 devices, but is optional in Cortex-A9 devices. Neon can execute MP3 audio decoding on CPUs running at 10 MHz, and can run the GSM adaptive multi-rate compression, adaptive multi-rate (AMR) speech codec at 13 MHz. It features a comprehensive instruction set, separate register files, and independent execution hardware. Neon supports 8-, 16-, 32-, and 64-bit integer and single-precision (32-bit) floating-point data and SIMD operations for handling audio and video processing as well as graphics and gaming processing. In Neon, the SIMD supports up to 16 operations at the same time. The Neon hardware shares the same floating-point registers as used in VFP. Devices such as the ARM Cortex-A8 and Cortex-A9 support 128-bit vectors, but will execute with 64 bits at a time, whereas newer Cortex-A15 devices can execute 128 bits at a time. A quirk of Neon in ARMv7 devices is that it flushes all Denormal number, subnormal numbers to zero, and as a result the GNU Compiler Collection, GCC compiler will not use it unless , which allows losing denormals, is turned on. "Enhanced" Neon defined since ARMv8 does not have this quirk, but as of GCC 8.2 the same flag is still required to enable Neon instructions. On the other hand, GCC does consider Neon safe on AArch64 for ARMv8. ProjectNe10 is ARM's first open-source project (from its inception; while they acquired an older project, now known as Mbed TLS). The Ne10 library is a set of common, useful functions written in both Neon and C (for compatibility). The library was created to allow developers to use Neon optimisations without learning Neon, but it also serves as a set of highly optimised Neon intrinsic and assembly code examples for common DSP, arithmetic, and image processing routines. The source code is available on GitHub.


ARM Helium technology

Helium is the M-Profile Vector Extension (MVE). It adds more than 150 scalar and vector instructions.


Security extensions


TrustZone (for Cortex-A profile)

The Security Extensions, marketed as TrustZone Technology, is in ARMv6KZ and later application profile architectures. It provides a low-cost alternative to adding another dedicated security core to an SoC, by providing two virtual processors backed by hardware based access control. This lets the application core switch between two states, referred to as worlds (to reduce confusion with other names for capability domains), in order to prevent information from leaking from the more trusted world to the less trusted world. This world switch is generally orthogonal to all other capabilities of the processor, thus each world can operate independently of the other while using the same core. Memory and peripherals are then made aware of the operating world of the core and may use this to provide access control to secrets and code on the device. Typically, a rich operating system is run in the less trusted world, with smaller security-specialised code in the more trusted world, aiming to reduce the attack surface. Typical applications include digital rights management, DRM functionality for controlling the use of media on ARM-based devices, and preventing any unapproved use of the device. In practice, since the specific implementation details of proprietary TrustZone implementations have not been publicly disclosed for review, it is unclear what level of assurance is provided for a given threat model, but they are not immune from attack. Open Virtualization is an open source implementation of the trusted world architecture for TrustZone. AMD has licensed and incorporated TrustZone technology into its Secure Processor Technology. Enabled in some but not all products, AMD's AMD APU, APUs include a Cortex-A5 processor for handling secure processing. In fact, the Cortex-A5 TrustZone core had been included in earlier AMD products, but was not enabled due to time constraints. Samsung Knox uses TrustZone for purposes such as detecting modifications to the kernel.


TrustZone for ARMv8-M (for Cortex-M profile)

The Security Extension, marketed as TrustZone for ARMv8-M Technology, was introduced in the ARMv8-M architecture. While containing similar concepts to TrustZone for ARMv8-A, it has a different architectural design, as world switching is performed using branch instructions instead of using exceptions. It also supports safe interleaved interrupt handling from either world regardless of the current security state. Together these features provide low latency calls to the secure world and responsive interrupt handling. ARM provides a reference stack of secure world code in the form of Trusted Firmware for M and PSA Certified.


No-execute page protection

As of ARMv6, the ARM architecture supports NX bit, no-execute page protection, which is referred to as ''XN'', for ''eXecute Never''.


Large Physical Address Extension (LPAE)

The Large Physical Address Extension (LPAE), which extends the physical address size from 32 bits to 40 bits, was added to the ARMv7-A architecture in 2011. Physical address size is larger, 44 bits, in Cortex-A75 and Cortex-A65AE.


ARMv8-R and ARMv8-M

The ARMv8-R and ARMv8-M architectures, announced after the ARMv8-A architecture, share some features with ARMv8-A, but don't include any 64-bit AArch64 instructions.


ARMv8.1-M

The ARMv8.1-M architecture, announced in February 2019, is an enhancement of the ARMv8-M architecture. It brings new features including: * A new vector instruction set extension. The M-Profile Vector Extension (MVE), or Helium, is for signal processing and machine learning applications. * Additional instruction set enhancements for loops and branches (Low Overhead Branch Extension). * Instructions for Half-precision floating-point format, half-precision floating-point support. * Instruction set enhancement for TrustZone management for Floating Point Unit (FPU). * New memory attribute in the Memory Protection Unit (MPU). * Enhancements in debug including Performance Monitoring Unit (PMU), Unprivileged Debug Extension, and additional debug support focus on signal processing application developments. * Reliability, Availability and Serviceability (RAS) extension.


64/32-bit architecture


ARMv8


ARMv8-A

Announced in October 2011, ARMv8-A (often called ARMv8 while the ARMv8-R is also available) represents a fundamental change to the ARM architecture. It adds an optional 64-bit architecture (e.g. Cortex-A32 is a 32-bit ARMv8-A CPU while most ARMv8-A CPUs support 64-bit), named "AArch64", and the associated new "A64" instruction set. AArch64 provides user space, user-space compatibility with ARMv7-A, the 32-bit architecture, therein referred to as "AArch32" and the old 32-bit instruction set, now named "A32". The Thumb instruction set is referred to as "T32" and has no 64-bit counterpart. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit hypervisor. ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012. Apple was the first to release an ARMv8-A compatible core (Apple A7) in a consumer product (iPhone 5S). AppliedMicro, using an FPGA, was the first to demo ARMv8-A. The first ARMv8-A System on a chip, SoC from Samsung Electronics, Samsung is the Exynos 5433 used in the Samsung Galaxy Note 4, Galaxy Note 4, which features two clusters of four Cortex-A57 and Cortex-A53 cores in a big.LITTLE configuration; but it will run only in AArch32 mode. To both AArch32 and AArch64, ARMv8-A makes VFPv3/v4 and advanced SIMD (Neon) standard. It also adds cryptography instructions supporting Advanced Encryption Standard, AES, SHA-1/SHA-256 and finite field arithmetic. AArch64 was introduced in ARMv8-A and its subsequent revision. AArch64 is not included in the 32-bit ARMv8-R and ARMv8-M architectures.


ARMv8-R

Optional AArch64 support was added to the ARMv8-R profile, with the first ARM core implementing it being the Cortex-R82. It adds the A64 instruction set.


ARMv9


ARMv9-A

Announced in March 2021, the updated architecture places a focus on secure execution and compartmentalisation.


Arm SystemReady

Arm SystemReady
previously known as Arm ServerReady, is a certification program that helps land the generic off-the-shelf operating systems and hypervisors on to the Arm-based systems from datacenter servers to industrial edge and IoT devices. The key building blocks of the program are the specifications for minimum hardware and firmware requirements that the operating systems and hypervisors can rely upon. These specifications are:
Base System Architecture (BSA)
and the market segment specific supplements (e.g.
Server BSA supplement

Base Boot Requirements (BBR)
an
Base Boot Security Requirements (BBR)
These specifications are co-developed by
Arm Holdings Arm Ltd. (stylized as arm) is a Great Britain, British semiconductor and Computer software, software design company based in Cambridge, England. Its primary business is in the design of ARM architecture, ARM Central processing unit, processors ...
and its partners in the System Architecture Advisory Committee (SystemArchAC). Architecture Compliance Suite (ACS) is the test tools that help to check the compliance of these specifications. Th
Arm SystemReady Requirements Specification
documents the requirements of the certifications. This program was introduced by
Arm Holdings Arm Ltd. (stylized as arm) is a Great Britain, British semiconductor and Computer software, software design company based in Cambridge, England. Its primary business is in the design of ARM architecture, ARM Central processing unit, processors ...
in 2020 at the first DevSummit event. Its predecessor Arm ServerReady was introduced in 2018 at the Arm TechCon event. This program currently includes four bands: * SystemReady SR: this band is for servers that support operating systems and hypervisors that expect Unified Extensible Firmware Interface, UEFI, Advanced Configuration and Power Interface, ACPI and System Management BIOS, SMBIOS interfaces. Windows Server, Red Hat Enterprise Linux and VMware ESXi-Arm require these interfaces while other Linux and BSD distros can also support. * SystemReady LS: this band is for servers that hyperscalers use to support Linux operating systems that expect LinuxBoot firmware along with the ACPI and SMBIOS interfaces. * SystemReady ES: this band is for the industrial edge and IoT devices that support operating systems and hypervisors that expect UEFI, ACPI and SMBIOS interfaces. Windows IoT Enterprise, Red Hat Enterprise Linux and VMware ESXi-Arm require these interfaces while other Linux and BSD distros can also support. * SystemReady IR: this band is for the industrial edge and IoT devices that support operating systems that expect UEFI and Device tree, devicetree interfaces. Embedded Linux (e.g., Yacto) and some Linux/BSD distros (e.g., Fedora, Ubuntu, Debian and OpenSUSE) can also support.


PSA Certified

PSA Certified, previously known as Platform Security Architecture, is an architecture-agnostic security framework and evaluation scheme. It is intended to help secure Internet of Things (IoT) devices built on system-on-a-chip (SoC) processors. Its introduced was to increase security where a full [trusted execution environment is too large or complex. The architecture was introduced by
Arm Holdings Arm Ltd. (stylized as arm) is a Great Britain, British semiconductor and Computer software, software design company based in Cambridge, England. Its primary business is in the design of ARM architecture, ARM Central processing unit, processors ...
in 2017 at the annual TechCon event. Although the scheme is architecture agnostic, it was first implemented on Arm Cortex-M processor cores intended for microcontroller use. PSA Certified includes freely available threat models and security analyses that demonstrate the process for deciding on security features in common IoT products. It also provides freely downloadable application programming interface (API) packages, architectural specifications, open-source firmware implementations, and related test suites. Following the development of the architecture security framework in 2017, the PSA Certified assurance scheme launched two years later at Embedded World in 2019. PSA Certified offers a multi-level security evaluation scheme for chip vendors, OS providers and IoT device makers. The Embedded World presentation introduced chip vendors to Level 1 Certification. A draft of Level 2 protection was presented at the same time. Level 2 certification became a useable standard in February 2020. The certification was created by PSA Joint Stakeholders to enable a security-by-design approach for a diverse set of IoT products. PSA Certified specifications are implementation and architecture agnostic, as a result they can be applied to any chip, software or device. The certification also removes industry fragmentation for Internet of Things, IoT product manufacturers and developers.


Operating system support


32-bit operating systems


Historical operating systems

The first 32-bit ARM-based personal computer, the Acorn Archimedes, was originally intended to run an ambitious operating system called ARX (operating system), ARX. The machines shipped with RISC OS which was also used on later ARM-based systems from Acorn and other vendors. Some early Acorn machines were also able to run a Unix port called RISC iX. (Neither is to be confused with MIPS RISC/os, RISC/os, a contemporary Unix variant for the MIPS architecture.)


Embedded operating systems

The 32-bit ARM architecture is supported by a large number of embedded operating system, embedded and real-time operating systems, including: * A2 (operating system), A2 * Android (operating system), Android * ChibiOS/RT * Deos * DRYOS * eCos * embOS * FreeRTOS * Integrity (operating system), Integrity * Linux kernel, Linux * Micro-Controller Operating Systems * MINIX 3 * MQX * Nucleus RTOS, Nucleus PLUS * NuttX * Operating System Embedded (OSE) * OS-9 * Pharos * Plan 9 from Bell Labs, Plan 9 * PikeOS * QNX * RIOT (operating system), RIOT * RTEMS * RTXC Quadros * SCIOPTA * ThreadX * TizenRT * T-Kernel * VxWorks * Windows CE, Windows Embedded Compact * Windows 10 IoT Core * Zephyr (operating system), Zephyr


Mobile device operating systems

The 32-bit ARM architecture is the primary hardware environment for most mobile device operating systems such as: * Android (operating system), Android * Bada * BlackBerry OS/BlackBerry 10 * Chrome OS * Firefox OS * MeeGo * Sailfish OS, Sailfish * Symbian * Tizen * Ubuntu Touch * webOS * Windows RT * Windows Mobile * Windows Phone * Windows 10 Mobile Previously, but now discontinued: * iOS 10 and earlier


Desktop/server operating systems

The 32-bit ARM architecture is supported by RISC OS and by multiple Unix-like operating systems including: * FreeBSD * NetBSD * OpenBSD * OpenSolaris * several Linux distributions, such as: ** Debian ** Armbian ** Gentoo Linux, Gentoo ** Ubuntu (operating system), Ubuntu ** Raspberry Pi OS (formerly Raspbian) ** Slackware ARM, Slackware


64-bit operating systems


Embedded operating systems

* Integrity (operating system), Integrity * Operating System Embedded, OSE * SCIOPTA * L4 microkernel family#High assurance: seL4, seL4 * Pharos * FreeRTOS * QNX * Zephyr (operating system), Zephyr


Mobile device operating systems

* iOS supports ARMv8-A in iOS 7 and later on 64-bit Apple-designed processors, Apple SoCs. iOS 11 and later only supports 64-bit ARM processors and applications. * Android (operating system), Android supports ARMv8-A in Android Lollipop (5.0) and later.


Desktop/server operating systems

* Support for ARMv8-A was merged into the Linux kernel version 3.7 in late 2012. ARMv8-A is supported by a number of Linux distributions, such as: ** Debian ** Armbian ** Ubuntu (operating system), Ubuntu ** Fedora (operating system), Fedora ** openSUSE ** SUSE Linux Enterprise ** Red Hat Enterprise Linux, RHEL * Support for ARMv8-A was merged into FreeBSD in late 2014. * OpenBSD has experimental ARMv8 support as of 2017. * NetBSD has ARMv8 support as of early 2018. * Windows 10 – runs 32-bit "x86 and 32-bit ARM applications", as well as native ARM64 desktop apps. Support for 64-bit ARM apps in the Microsoft Store (digital), Microsoft Store has been available since November 2018. * macOS has ARM support starting with macOS Big Sur as of late 2020. Rosetta 2 adds support for x86-64 applications but not virtualization of x86-64 computer platforms.


Porting to 32- or 64-bit ARM operating systems

Windows applications recompiled for ARM and linked with Winelib from the Wine (software), Wine project can run on 32-bit or 64-bit ARM in Linux, FreeBSD or other compatible operating systems. x86 binaries, e.g. when not specially compiled for ARM, have been demonstrated on ARM using QEMU with Wine (on Linux and more), but do not work at full speed or same capability as with Winelib.


Notes


See also

* RISC * RISC-V * Apple-designed processors * ARM big.LITTLE – ARM's heterogeneous computing architecture ** DynamIQ * ARM Accredited Engineer – certification program * ARMulator – an instruction set simulator * Amber (processor core) – an open-source ARM-compatible processor core * AMULET microprocessor – an asynchronous implementation of the ARM architecture * Comparison of ARMv7-A cores * Comparison of ARMv8-A cores * Unicore – a 32-register architecture based heavily on a 32-bit ARM * Meltdown (security vulnerability) * Spectre (security vulnerability)


References


Citations


Bibliography

*


Further reading


External links

* , ARM Ltd.
ARM Virtualization Extensions
;Quick Reference Cards * Instructions
ThumbARM and Thumb-2Vector Floating Point
* Opcodes
ThumbThumbARMARMGNU Assembler Directives
{{Authority control ARM architecture, Acorn Computers Articles with example code Computer-related introductions in 1983 Instruction set architectures