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UCIe
Universal Chiplet Interconnect Express (UCIe) is an open specification for a die-to-die interconnect and serial bus between chiplets. It is co-developed by AMD, Arm, ASE Group, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC. In August 2022, Alibaba Group and NVIDIA joined as board members. Overview A common chiplet interconnect specification enables construction of large System-on-Chip (SoC) packages that exceed maximum reticle size. It allows intermixing components from different silicon vendors within the same package and improves manufacturing yields by using smaller dies. Each chiplet can use different silicon manufacturing process suitable for a specific device type or computing performance and power draw requirements. Specifications The UCIe 1.0 specification was released on March 2, 2022. It defines physical layer, protocol stack and software model, as well as procedures for compliance testing. The physical layer supports up to 32 GT/s with 16 to 64 la ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Chiplet
A chiplet is a tiny integrated circuit (IC) that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an interposer in a single package. A set of chiplets can be implemented in a mix-and-match "LEGO-like" assembly. This provides several advantages over a traditional system on chip (SoC): * Reusable IP (Intellectual Property): the same chiplet can be used in many different devices * Heterogeneous integration: chiplets can be fabricated with different processes, materials, and nodes, each optimized for its particular function * Known good die: chiplets can be tested before assembly, improving the yield of the final device Multiple chiplets working together in a single integrated circuit may be called a multi-chip module (MCM), hybrid IC, 2.5D IC, or an advanced package. Chiplets may be connected with standards such as UCIe, Bunch of Wires (BoW), OpenHBI, and OIF XSR. See also * UCIe Universal Chiplet Interconnect Express (UCIe) ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
PCI Express
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common motherboard interface for personal computers' graphics cards, hard disk drive host adapters, SSDs, Wi-Fi and Ethernet hardware connections. PCIe has numerous improvements over the older standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, a more detailed error detection and reporting mechanism (Advanced Error Reporting, AER), and native hot-swap functionality. More recent revisions of the PCIe standard provide hardware support for I/O virtualization. The PCI Express electrical interface is measured by the number of simultaneous lanes. (A lane is a single send/receive line of data. The analogy is a highway with traffic in both directions. ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Compute Express Link
Compute Express Link (CXL) is an open standard for high-speed central processing unit (CPU)-to-device and CPU-to-memory connections, designed for high performance data center computers. CXL is built on the PCI Express (PCIe) physical and electrical interface and includes PCIe-based block input/output protocol (CXL.io) and new cache-coherent protocols for accessing system memory (CXL.cache) and device memory (CXL.mem). History The CXL technology was primarily developed by Intel. The CXL Consortium was formed in March 2019 by founding members Alibaba Group, Cisco Systems, Dell EMC, Meta, Google, Hewlett Packard Enterprise (HPE), Huawei, Intel Corporation and Microsoft, and officially incorporated in September 2019. As of January 2022, AMD, Nvidia, Samsung Electronics and Xilinx joined the founders on the board of directors, while ARM, Broadcom, Ericsson, IBM, Keysight, Kioxia, Marvell Technology, Mellanox, Microchip Technology, Micron, Oracle Corporation, Qualcomm, Rambus, Ren ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Open Standard
An open standard is a standard that is openly accessible and usable by anyone. It is also a prerequisite to use open license, non-discrimination and extensibility. Typically, anybody can participate in the development. There is no single definition, and interpretations vary with usage. The terms ''open'' and ''standard'' have a wide range of meanings associated with their usage. There are a number of definitions of open standards which emphasize different aspects of openness, including the openness of the resulting specification, the openness of the drafting process, and the ownership of rights in the standard. The term "standard" is sometimes restricted to technologies approved by formalized committees that are open to participation by all interested parties and operate on a consensus basis. The definitions of the term ''open standard'' used by academics, the European Union, and some of its member governments or parliaments such as Denmark, France, and Spain preclude open standard ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
System-on-Chip
A system on a chip or system-on-chip (SoC ; pl. ''SoCs'' ) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory interfaces, on-chip input/output devices, input/output interfaces, and secondary storage interfaces, often alongside other components such as radio modems and a graphics processing unit (GPU) – all on a single substrate or microchip. It may contain digital, analog, mixed-signal, and often radio frequency signal processing functions (otherwise it is considered only an application processor). Higher-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (such as LPDDR and eUFS or eMMC, respectively) chips, that may be layered on top of the SoC in what's known as a package on package (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may use separate wireless mode ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SerDes
{{Use American English, date = March 2019 A Serializer/Deserializer (SerDes) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction. The term "SerDes" generically refers to interfaces used in various technologies and applications. The primary use of a SerDes is to provide data transmission over a single line or a differential pair in order to minimize the number of I/O pins and interconnects. Generic function The basic SerDes function is made up of two functional blocks: the Parallel In Serial Out (PISO) block (aka Parallel-to-Serial converter) and the Serial In Parallel Out (SIPO) block (aka Serial-to-Parallel converter). There are 4 different SerDes architectures: (1) Parallel clock SerDes, (2) Embedded clock SerDes, (3) 8b/10b SerDes, (4) Bit interleaved SerDes. The PISO (Parallel Input, Serial Output) block typically has a paral ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Joule
The joule ( , ; symbol: J) is the unit of energy in the International System of Units (SI). It is equal to the amount of work done when a force of 1 newton displaces a mass through a distance of 1 metre in the direction of the force applied. It is also the energy dissipated as heat when an electric current of one ampere passes through a resistance of one ohm for one second. It is named after the English physicist James Prescott Joule (1818–1889). Definition In terms of SI base units and in terms of SI derived units with special names, the joule is defined as One joule can also be defined by any of the following: * The work required to move an electric charge of one coulomb through an electrical potential difference of one volt, or one coulomb-volt (C⋅V). This relationship can be used to define the volt. * The work required to produce one watt of power for one second, or one watt-second (W⋅s) (compare kilowatt-hour, which is 3.6 megajoules). This relationship can b ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
GitHub
GitHub, Inc. () is an Internet hosting service for software development and version control using Git. It provides the distributed version control of Git plus access control, bug tracking, software feature requests, task management, continuous integration, and wikis for every project. Headquartered in California, it has been a subsidiary of Microsoft since 2018. It is commonly used to host open source software development projects. As of June 2022, GitHub reported having over 83 million developers and more than 200 million repositories, including at least 28 million public repositories. It is the largest source code host . History GitHub.com Development of the GitHub.com platform began on October 19, 2007. The site was launched in April 2008 by Tom Preston-Werner, Chris Wanstrath, P. J. Hyett and Scott Chacon after it had been made available for a few months prior as a beta release. GitHub has an annual keynote called GitHub Universe. Organizational ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Three-dimensional Integrated Circuit
A three-dimensional integrated circuit (3D IC) is a MOSFET, MOS (metal-oxide semiconductor) integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in microelectronics and nanoelectronics. 3D integrated circuits can be classified by their level of interconnect hierarchy at the global (Integrated circuit packaging, package), intermediate (bond pad) and local (transistor) level. In general, 3D integration is a broad term that includes such technologies as 3D wafer-level packaging (3DWLP); 2.5D and 3D interposer-based integration; 3D stacked ICs (3D-SICs); monolithic 3D ICs; ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Interposer
An interposer is an electrical interface routing between one socket or connection to another. The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection to a different connection. Interposer comes from the Latin word "interpōnere", meaning "to put between". They are often used in BGA packages, multi-chip modules and high bandwidth memory. A common example of an interposer is an integrated circuit die to BGA, such as in the Pentium II. This is done through various substrates, both rigid and flexible, most commonly FR4 for rigid, and polyimide for flexible. Silicon and glass are also evaluated as an integration method. Interposer stacks are also a widely accepted, cost-effective alternative to 3D ICs. There are already several products with interposer technology in the market, notably the AMD Fiji/Fury GPU, and the Xilinx Virtex-7 FPGA. In 2016, CEA Leti demonstrated their second generation 3D- NoC technology which combines small ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Flit (computer Networking)
In computer networking, a flit (flow control unit or flow control digit) is a link-level atomic piece that forms a network packet or stream. The first flit, called the header flit holds information about this packet's route (namely the destination address) and sets up the routing behavior for all subsequent flits associated with the packet. The header flit is followed by zero or more body flits, containing the actual payload of data. The final flit, called the tail flit, performs some book keeping to close the connection between the two nodes. A virtual connection holds the state needed to coordinate the handling of the flits of a packet. At a minimum, this state identifies the output port of the current node for the next hop of the route and the state of the virtual connection (idle, waiting for resources, or active). The virtual connection may also include pointers to the flits of the packet that are buffered on the current node and the number of flit buffers available on the ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
GT/s
In computer technology, transfers per second and its more common secondary terms gigatransfers per second (abbreviated as GT/s) and megatransfers per second (MT/s) are informal language that refer to the number of operations transferring data that occur in each second in some given data-transfer channel. It is also known as sample rate, i.e. the number of data samples captured per second, each sample normally occurring at the clock edge. The terms are neutral with respect to the method of physically accomplishing each such data-transfer operation; nevertheless, they are most commonly used in the context of transmission of digital data. 1 MT/s is 106 or one million transfers per second; similarly, 1 GT/s means 109, or equivalently in the US/short scale, one billion transfers per second. Units The choice of the symbol ''T'' for ''transfer'' conflicts with the International System of Units, in which ''T'' stands for the tesla unit of magnetic flux density (so "Megatesla pe ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
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