|
SerDes
{{Use American English, date = March 2019 A Serializer/Deserializer (SerDes) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction. The term "SerDes" generically refers to interfaces used in various technologies and applications. The primary use of a SerDes is to provide data transmission over a single line or a differential pair in order to minimize the number of I/O pins and interconnects. Generic function The basic SerDes function is made up of two functional blocks: the Parallel In Serial Out (PISO) block (aka Parallel-to-Serial converter) and the Serial In Parallel Out (SIPO) block (aka Serial-to-Parallel converter). There are 4 different SerDes architectures: (1) Parallel clock SerDes, (2) Embedded clock SerDes, (3) 8b/10b SerDes, (4) Bit interleaved SerDes. The PISO (Parallel Input, Serial Output) block typically has a paral ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SerDes (Serializer - Deserializer)
{{Use American English, date = March 2019 A Serializer/Deserializer (SerDes) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction. The term "SerDes" generically refers to interfaces used in various technologies and applications. The primary use of a SerDes is to provide data transmission over a single line or a differential pair in order to minimize the number of I/O pins and interconnects. Generic function The basic SerDes function is made up of two functional blocks: the Parallel In Serial Out (PISO) block (aka Parallel-to-Serial converter) and the Serial In Parallel Out (SIPO) block (aka Serial-to-Parallel converter). There are 4 different SerDes architectures: (1) Parallel clock SerDes, (2) Embedded clock SerDes, (3) 8b/10b SerDes, (4) Bit interleaved SerDes. The PISO (Parallel Input, Serial Output) block typically has a paral ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SerDes Framer Interface
SerDes Framer Interface is a standard for telecommunications abbreviated as SFI. Variants include: * SFI-4 or SerDes Framer Interface Level 4, a standardized Electrical Interface by the Optical Internetworking Forum (OIF) for connecting a synchronous optical networking (SONET) framer component to an optical serializer/deserializer (SerDes) for Optical Carrier transmission rate OC-192 interfaces at about 10 Gigabits per second. * SFI-5 or SerDes Framer Interface Level 5, a standardized Electrical Interface by the OIF for connecting a SONET Framer component to an optical SerDes for OC-768, about 40 Gbit/s. Electrically, it consists of 16 pairs of SerDes channels each running at 3.125 Gbit/s which gives an aggregate bandwidth of 50 Gbit/s accommodating up to 25% of Forward Error Correction See also * XFP transceiver * System Packet Interface * Common Electrical I/O The Common Electrical I/O (CEI) refers to a series of influential Interoperability Agreements (IAs) that have bee ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Common Electrical I/O
The Common Electrical I/O (CEI) refers to a series of influential Interoperability Agreements (IAs) that have been published by the Optical Internetworking Forum (OIF). CEI defines the electrical and jitter requirements for 3.125, 6, 11, 25-28, and 56 Gbit/s electrical interfaces. CEI, the Common Electrical I/O The Common Electrical I/O (CEI) Interoperability Agreement published by the OIF defines the electrical and jitter requirements for 3.125, 6, 11, 25-28, and 56 Gbit/s SerDes interfaces. This CEI specification has defined SerDes interfaces for the industry since 2004, and it has been highly influential. The development of electrical interfaces at the OIF began with SPI-3 in 2000, and the first differential interface was published in 2003. The seventh generation electrical interface, CEI-56G, defines five reaches of 56 Gbit/s interfaces. The OIF began work on its eighth generation with its CEI-112G project. CEI has influenced or has been adopted or adapted in many other seri ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Optical Internetworking Forum
The Optical Internetworking Forum (OIF) is a prominent non-profit consortium that was founded in 1998. It promotes the development and deployment of interoperable computer networking products and services through implementation agreements (IAs) for optical networking products and component technologies including SerDes devices. OIF also creates benchmarks, performs worldwide interoperability testing, builds market awareness and promotes education for optical technologies. The Network Processing Forum merged into OIF in June 2006. The OIF has around a hundred member companies and has four face-to-face meetings per year. It is managed by Association Management Solutions and operates using parliamentary debate rules and transparent decision making. The technical content is member-driven. The OIF operates under a RAND licensing framework. It maintains liaison relationships with many other standards-developing organizations including the ITU, IEEE 802.3, the ONF, the InfiniBand ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Multi-gigabit Transceiver
A multi-gigabit transceiver (MGT) is a SerDes capable of operating at serial bit rates above 1 Gigabit/second. MGTs are used increasingly for data communications because they can run over longer distances, use fewer wires, and thus have lower costs than parallel interfaces with equivalent data throughput. Functions Like other SerDes, the primary function of the MGT is to transmit parallel data as stream of serial bits, and convert the serial bits it receives to parallel data. The most basic performance metric of an MGT is its serial bit rate, or line rate, which is the number of serial bits it can transmit or receive per second. Although there is no strict rule, MGTs can typically run at line rates of 1 Gigabit/second or more. MGTs have become the 'data highways' for data processing systems that demand a high in/out raw data input and output (e.g. video processing applications). They are becoming very common on FPGA - such programmable logic devices being especially well fitted fo ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
10 Gigabit Ethernet
10 Gigabit Ethernet (10GE, 10GbE, or 10 GigE) is a group of computer networking technologies for transmitting Ethernet frames at a rate of 10 gigabits per second. It was first defined by the IEEE 802.3ae-2002 standard. Unlike previous Ethernet standards, 10 Gigabit Ethernet defines only full-duplex point-to-point links which are generally connected by network switches; shared-medium CSMA/CD operation has not been carried over from the previous generations Ethernet standards so half-duplex operation and repeater hubs do not exist in 10GbE. The 10 Gigabit Ethernet standard encompasses a number of different physical layer (PHY) standards. A networking device, such as a switch or a network interface controller may have different PHY types through pluggable PHY modules, such as those based on SFP+. Like previous versions of Ethernet, 10GbE can use either copper or fiber cabling. Maximum distance over copper cable is 100 meters but because of its bandwidth requirements, higher ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Shift Register
A shift register is a type of digital circuit using a cascade of flip-flops where the output of one flip-flop is connected to the input of the next. They share a single clock signal, which causes the data stored in the system to shift from one location to the next. By connecting the last flip-flop back to the first, the data can cycle within the shifters for extended periods, and in this form they were used as a form of computer memory. In this role they are very similar to the earlier delay-line memory systems and were widely used in the late 1960s and early 1970s to replace that form of memory. In most cases, several parallel shift registers would be used to build a larger memory pool known as a "bit array". Data was stored into the array and read back out in parallel, often as a computer word, while each bit was stored serially in the shift registers. There is an inherent trade-off in the design of bit arrays; putting more flip-flops in a row allows a single shifter to store mo ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Shift Register
A shift register is a type of digital circuit using a cascade of flip-flops where the output of one flip-flop is connected to the input of the next. They share a single clock signal, which causes the data stored in the system to shift from one location to the next. By connecting the last flip-flop back to the first, the data can cycle within the shifters for extended periods, and in this form they were used as a form of computer memory. In this role they are very similar to the earlier delay-line memory systems and were widely used in the late 1960s and early 1970s to replace that form of memory. In most cases, several parallel shift registers would be used to build a larger memory pool known as a "bit array". Data was stored into the array and read back out in parallel, often as a computer word, while each bit was stored serially in the shift registers. There is an inherent trade-off in the design of bit arrays; putting more flip-flops in a row allows a single shifter to store mo ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
8b/10b
In telecommunications, 8b/10b is a line code that maps 8-bit words to 10-bit symbols to achieve DC balance and bounded disparity, and at the same time provide enough state changes to allow reasonable clock recovery. This means that the difference between the counts of ones and zeros in a string of ''at least'' 20 bits is no more than two, and that there are not more than five ones or zeros in a row. This helps to reduce the demand for the lower bandwidth limit of the channel necessary to transfer the signal. An 8b/10b code can be implemented in various ways, where the design may focus on specific parameters such as hardware requirements, DC-balance, etc. One implementation was designed by K. Odaka for the DAT digital audio recorder. Kees Schouhamer Immink designed an 8b/10b code for the DCC audio recorder. The IBM implementation was described in 1983 by Al Widmer and Peter Franaszek. IBM implementation As the scheme name suggests, eight bits of data are transmitted a ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
International Committee For Information Technology Standards
The InterNational Committee for Information Technology Standards (INCITS), (pronounced "insights"), is an ANSI-accredited standards development organization composed of Information technology developers. It was formerly known as the X3 and NCITS. INCITS is the central U.S. forum dedicated to creating technology standards. INCITS is accredited by the American National Standards Institute (ANSI) and is affiliated with the Information Technology Industry Council, a global policy advocacy organization that represents U.S. and global innovation companies. INCITS coordinates technical standards activity between ANSI in the US and joint ISO/IEC committees worldwide. This provides a mechanism to create standards that will be implemented in many nations. As such, INCITS' Executive Board also serves as ANSI's Technical Advisory Group for ISO/IEC Joint Technical Committee 1. JTC 1 is responsible for International standardization in the field of information technology. INCITS operates thro ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
RapidIO
The RapidIO architecture is a high-performance packet-switched electrical connection technology. RapidIO supports messaging, read/write and cache coherency semantics. Based on industry-standard electrical specifications such as those for Ethernet, RapidIO can be used as a chip-to-chip, board-to-board, and chassis-to-chassis interconnect. History The RapidIO protocol was originally designed by Mercury Computer Systems and Motorola (Freescale) as a replacement for Mercury's RACEway proprietary bus and Freescale's PowerPC bus. The RapidIO Trade Association was formed in February 2000, and included telecommunications and storage OEMs as well as FPGA, processor, and switch companies. Releases The RapidIO specification revision 1.1 (3xN Gen1), released in March 2001, defined a wide, parallel bus. This specification did not achieve extensive commercial adoption. The RapidIO specification revision 1.2, released in June 2002, defined a serial interconnect based on the XAUI physical ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
.svg "Click for more on -> SerDes")
