Generic function
The basic SerDes function is made up of two functional blocks: the Parallel In Serial Out (PISO) block (aka Parallel-to-Serial converter) and the Serial In Parallel Out (SIPO) block (aka Serial-to-Parallel converter). There are 4 different SerDes architectures: (1) Parallel clock SerDes, (2) Embedded clock SerDes, (3) 8b/10b SerDes, (4) Bit interleaved SerDes. The PISO (Parallel Input, Serial Output) block typically has a parallel clock input, a set of data input lines, and input data latches. It may use an internal or external phase-locked loop (PLL) to multiply the incoming parallel clock up to the serial frequency. The simplest form of the PISO has a singleSource Synchronous Clocking
Parallel clock SerDes is normally used to serialize a parallel bus input along with data address & control signals. The serialized stream is sent along with a reference clock. The clockEmbedded Clocking
An embedded clock SerDes serializes data and clock into a single stream. One cycle of clock signal is transmitted first, followed by the data bit stream; this creates a periodic rising edge at the start of the data bit stream. As the clock is explicitly embedded and can be recovered from the bit stream, the serializer (transmitter) clock jitter tolerance is relaxed to 80–120 ps rms, while the reference clock disparity at the deserializer can be ±50,000 ppm (i.e. 5%).Data Encoding
8b/10b SerDes maps each data byte to a 10-bit code before serializing the data. The deserializer uses the reference clock to monitor the recovered clock from the bit stream. As the clock information is synthesized into the data bit stream, rather than explicitly embedding it, the serializer (transmitter) clock jitter tolerance is to 5–10 ps rms and the reference clock disparity at the deserializer is ±100 ppm. A common coding scheme used with SerDes is 8b/10b encoding. This supports DC-balance, provides framing, and guarantees frequent transitions. The guaranteed transitions allow a receiver to extract the embedded clock. The control codes allow framing, typically on the start of a packet. The typical 8b/10b SerDes parallel side interfaces have one clock line, one control line and 8 data lines. Such serializer-plus-8b/10b encoder, and deserializer-plus-decoder blocks are defined in theBit interleaved SerDes
Bit interleaved SerDes multiplexes several slower serial data streams into faster serial streams, and the receiver demultiplexes the faster bit streams back to slower streams.Standardization of SerDes
TheSee also
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