electronics Electronics is a scientific and engineering discipline that studies and applies the principles of physics to design, create, and operate devices that manipulate electrons and other Electric charge, electrically charged particles. It is a subfield ...

and

computer science Computer science is the study of computation, information, and automation. Computer science spans Theoretical computer science, theoretical disciplines (such as algorithms, theory of computation, and information theory) to Applied science, ...

, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a

complex instruction set computer A complex instruction set computer (CISC ) is a computer architecture in which single instructions can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) or are capable of multi-step ...

(CISC), a RISC computer might require more instructions (more code) in order to accomplish a task because the individual instructions perform simpler operations. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an

instruction pipeline In computer engineering, instruction pipelining is a technique for implementing instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming Mac ...

, which may be simpler to achieve given simpler instructions. The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). The RISC computer usually has many (16 or 32) high-speed, general-purpose registers with a load–store architecture in which the code for the register-register instructions (for performing arithmetic and tests) are separate from the instructions that access the main memory of the computer. The design of the CPU allows RISC computers few simple

addressing mode Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions ...

s and predictable instruction times that simplify design of the system as a whole. The conceptual developments of the RISC computer architecture began with the

IBM 801 The 801 was an experimental central processing unit (CPU) design developed by IBM during the 1970s. It is considered to be the first modern RISC design, relying on processor registers for all computations and eliminating the many variant addressi ...

project in the late 1970s, but these were not immediately put into use. Designers in California picked up the 801 concepts in two seminal projects,

Stanford MIPS MIPS, an acronym for Microprocessor without Interlocked Pipeline Stages, was a research project conducted by John L. Hennessy at Stanford University between 1981 and 1984. MIPS investigated a type of instruction set architecture (ISA) now called ...

and Berkeley RISC. These were commercialized in the 1980s as the MIPS and SPARC systems.

IBM International Business Machines Corporation (using the trademark IBM), nicknamed Big Blue, is an American Multinational corporation, multinational technology company headquartered in Armonk, New York, and present in over 175 countries. It is ...

eventually produced RISC designs based on further work on the 801 concept, the IBM POWER architecture,

PowerPC PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple Inc., App ...

, and

Power ISA Power ISA is a reduced instruction set computer (RISC) instruction set architecture (ISA) currently developed by the OpenPOWER Foundation, led by IBM. It was originally developed by IBM and the now-defunct Power.org industry group. Power IS ...

. As the projects matured, many similar designs, produced in the mid-to-late 1980s and early 1990s, such as ARM,

PA-RISC Precision Architecture reduced instruction set computer, RISC (PA-RISC) or Hewlett Packard Precision Architecture (HP/PA or simply HPPA), is a computer, general purpose computer instruction set architecture (ISA) developed by Hewlett-Packard f ...

, and

Alpha Alpha (uppercase , lowercase ) is the first letter of the Greek alphabet. In the system of Greek numerals, it has a value of one. Alpha is derived from the Phoenician letter ''aleph'' , whose name comes from the West Semitic word for ' ...

, created central processing units that increased the commercial utility of the

Unix Unix (, ; trademarked as UNIX) is a family of multitasking, multi-user computer operating systems that derive from the original AT&T Unix, whose development started in 1969 at the Bell Labs research center by Ken Thompson, Dennis Ritchie, a ...

workstation A workstation is a special computer designed for technical or computational science, scientific applications. Intended primarily to be used by a single user, they are commonly connected to a local area network and run multi-user operating syste ...

and of

embedded processor An embedded system is a specialized computer system—a combination of a computer processor, computer memory, and input/output peripheral devices—that has a dedicated function within a larger mechanical or electronic system. It is em ...

s in the

laser printer Laser printing is an electrostatic digital printing process. It produces high-quality text and graphics (and moderate-quality photographs) by repeatedly passing a laser beam back and forth over a Electric charge, negatively charged cylinder call ...

, the router, and similar products. In the

minicomputer A minicomputer, or colloquially mini, is a type of general-purpose computer mostly developed from the mid-1960s, built significantly smaller and sold at a much lower price than mainframe computers . By 21st century-standards however, a mini is ...

market, companies that included

Celerity Computing Celerity Computing, Inc., was a publicly traded vendor of Unix-based minisupercomputers based in San Diego, California. Celerity Computing was founded in May 1983 by Steve Vallender, Nick Aneshansley and Andrew McCroklin. All were former employe ...

Pyramid Technology Pyramid Technology Corporation was a computer company that produced a number of RISC-based minicomputers at the upper end of the performance range. It was based in the San Francisco Bay Area of California They also became the second company to s ...

, and

Ridge Computers Ridge Computers, Inc., was an American computer manufacturer active from 1980 to 1990. The company began as a builder of deskside workstations and workgroup servers and progressed to superminicomputers. They claimed to have produced the first ...

began offering systems designed according to RISC or RISC-like principles in the early 1980s. Few of these designs began by using RISC

microprocessor A microprocessor is a computer processor (computing), processor for which the data processing logic and control is included on a single integrated circuit (IC), or a small number of ICs. The microprocessor contains the arithmetic, logic, a ...

s. The varieties of RISC processor design include the ARC processor, the DEC Alpha, the

AMD Am29000 The AMD Am29000, commonly shortened to 29k, is a family of 32-bit RISC microprocessors and microcontrollers developed and fabricated by Advanced Micro Devices (AMD). Based on the seminal Berkeley RISC, the 29k added a number of significant impr ...

, the ARM architecture, the

Atmel AVR AVR is a family of microcontrollers developed since 1996 by Atmel, acquired by Microchip Technology in 2016. They are 8-bit RISC single-chip microcontrollers based on a modified Harvard architecture. AVR was one of the first microcontroller ...

Blackfin Blackfin is a family of 16-/32-bit microprocessors developed, manufactured and marketed by Analog Devices. The processors have built-in, fixed-point digital signal processor (DSP) functionality performed by 16-bit multiply–accumulates (MA ...

, Intel i860,

Intel i960 Intel's i960 (or 80960) is a RISC-based microprocessor design that became popular during the early 1990s as an embedded system, embedded microcontroller. It became a best-selling CPU in that segment, along with the competing AMD 29000. In spite ...

, LoongArch, Motorola 88000, the MIPS architecture, PA-RISC, Power ISA,

RISC-V RISC-V (pronounced "risk-five") is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project commenced in 2010 at the University of California, Berkeley. It transfer ...

SuperH SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems. At the ...

, and SPARC. RISC processors are used in

supercomputer A supercomputer is a type of computer with a high level of performance as compared to a general-purpose computer. The performance of a supercomputer is commonly measured in floating-point operations per second (FLOPS) instead of million instruc ...

s, such as the Fugaku.

History and development

A number of systems, going back to the 1960s, have been credited as the first RISC architecture, partly based on their use of the load–store approach. The term RISC was coined by David Patterson of the Berkeley RISC project, although somewhat similar concepts had appeared before. The

CDC 6600 The CDC 6600 was the flagship of the 6000 series of mainframe computer systems manufactured by Control Data Corporation. Generally considered to be the first successful supercomputer, it outperformed the industry's prior recordholder, the I ...

Seymour Cray Seymour Roger Cray (September 28, 1925 – October 5, 1996)
– was an American

s (register+register, and register+immediate constant) and 74 operation codes, with the basic clock cycle being 10 times faster than the memory access time. Partly due to the optimized load–store architecture of the CDC 6600, Jack Dongarra says that it can be considered a forerunner of modern RISC systems, although a number of other technical barriers needed to be overcome for the development of a modern RISC system.

IBM 801

Michael J. Flynn views the first RISC system as the

design, begun in 1975 by John Cocke and completed in 1980. The 801 developed out of an effort to build a 24-bit high-speed processor to use as the basis for a digital

telephone switch A telephone exchange, telephone switch, or central office is a central component of a telecommunications system in the public switched telephone network (PSTN) or in large enterprises. It facilitates the establishment of communication circuits ...

. To reach their goal of switching 1 million calls per hour (300 per second) they calculated that the CPU required performance on the order of 12 million

instructions per second Instructions per second (IPS) is a measure of a computer's Central processing unit, processor speed. For complex instruction set computers (CISCs), different Machine code, instructions take different amounts of time, so the value measured depen ...

(MIPS), compared to their fastest mainframe machine of the time, the 370/168, which performed at 3.5 MIPS. The design was based on a study of IBM's extensive collection of statistics gathered from their customers. This demonstrated that code in high-performance settings made extensive use of

processor register A processor register is a quickly accessible location available to a computer's processor. Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-onl ...

s, and that they often ran out of them. This suggested that additional registers would improve performance. Additionally, they noticed that

compiler In computing, a compiler is a computer program that Translator (computing), translates computer code written in one programming language (the ''source'' language) into another language (the ''target'' language). The name "compiler" is primaril ...

s generally ignored the vast majority of the available instructions, especially orthogonal addressing modes. Instead, they selected the fastest version of any given instruction and then constructed small routines using it. This suggested that the majority of instructions could be removed without affecting the resulting code. These two conclusions worked in concert; removing instructions would allow the instruction

opcode In computing, an opcode (abbreviated from operation code) is an enumerated value that specifies the operation to be performed. Opcodes are employed in hardware devices such as arithmetic logic units (ALUs), central processing units (CPUs), and ...

s to be shorter, freeing up bits in the instruction word which could then be used to select among a larger set of registers. The telephone switch program was canceled in 1975, but by then the team had demonstrated that the same design would offer significant performance gains running just about any code. In simulations, they showed that a compiler tuned to use registers instead of operating directly on memory would run code about three times as fast as traditional designs. Somewhat surprisingly, the same code would run about 50% faster even on existing machines due to the improved register use. In practice, their experimental PL/8 compiler, a slightly cut-down version of

PL/I PL/I (Programming Language One, pronounced and sometimes written PL/1) is a procedural, imperative computer programming language initially developed by IBM. It is designed for scientific, engineering, business and system programming. It has b ...

, consistently produced code that ran much faster on their existing mainframes. A 32-bit version of the 801 was eventually produced in a single-chip form as the IBM ROMP in 1981, which stood for 'Research OPD ffice Products DivisionMicro Processor'. This CPU was designed for "mini" tasks, and found use in peripheral interfaces and

channel controller In computing, channel I/O is a high-performance input/output (I/O) architecture that is implemented in various forms on a number of computer architectures, especially on mainframe computers. In the past, channels were generally implemented with cu ...

s on later IBM computers. It was also used as the CPU in the IBM RT PC in 1986, which turned out to be a commercial failure. Although the 801 did not see widespread use in its original form, it inspired many research projects, including ones at IBM that would eventually lead to the IBM POWER architecture.

Berkeley RISC and Stanford MIPS

By the late 1970s, the 801 had become well-known in the industry. This coincided with new fabrication techniques that were allowing more complex chips to come to market. The

Zilog Z80 The Zilog Z80 is an 8-bit computing, 8-bit microprocessor designed by Zilog that played an important role in the evolution of early personal computing. Launched in 1976, it was designed to be Backward compatibility, software-compatible with the ...

of 1976 had 8,000 transistors, whereas the 1979

Motorola 68000 The Motorola 68000 (sometimes shortened to Motorola 68k or m68k and usually pronounced "sixty-eight-thousand") is a 16/32-bit complex instruction set computer (CISC) microprocessor, introduced in 1979 by Motorola Semiconductor Products Sector ...

(68k) had 68,000. These newer designs generally used their newfound complexity to expand the instruction set to make it more orthogonal. Most, like the 68k, used

microcode In processor design, microcode serves as an intermediary layer situated between the central processing unit (CPU) hardware and the programmer-visible instruction set architecture of a computer. It consists of a set of hardware-level instructions ...

to do this, reading instructions and re-implementing them as a sequence of simpler internal instructions. In the 68k, a full of the transistors were used for this microcoding. In 1979, David Patterson was sent on a

sabbatical A sabbatical (from the Hebrew: (i.e., Sabbath); in Latin ; Greek: ) is a rest or break from work; "an extended period of time intentionally spent on something that’s not your routine job." The concept of the sabbatical is based on the Bi ...

from the

University of California, Berkeley The University of California, Berkeley (UC Berkeley, Berkeley, Cal, or California), is a Public university, public Land-grant university, land-grant research university in Berkeley, California, United States. Founded in 1868 and named after t ...

to help DEC's west-coast team improve the VAX microcode. Patterson was struck by the complexity of the coding process and concluded it was untenable. He first wrote a paper on ways to improve microcoding, but later changed his mind and decided microcode itself was the problem. With funding from the DARPA VLSI Program, Patterson started the Berkeley RISC effort. The Program, practically unknown today, led to a huge number of advances in chip design, fabrication, and even computer graphics. Considering a variety of programs from their BSD Unix variant, the Berkeley team found, as had IBM, that most programs made no use of the large variety of instructions in the 68k. Patterson's early work pointed out an important problem with the traditional "more is better" approach; even those instructions that were critical to overall performance were being delayed by their trip through the microcode. If the microcode was removed, the programs would run faster. And since the microcode ultimately took a complex instruction and broke it into steps, there was no reason the compiler could not do this instead. These studies suggested that, even with no other changes, one could make a chip with fewer transistors that would run faster. In the original RISC-I paper they noted:

Skipping this extra level of interpretation appears to enhance performance while reducing chip size.

It was also discovered that, on microcoded implementations of certain architectures, complex operations tended to be ''slower'' than a sequence of simpler operations doing the same thing. This was in part an effect of the fact that many designs were rushed, with little time to optimize or tune every instruction; only those used most often were optimized, and a sequence of those instructions could be faster than a less-tuned instruction performing an equivalent operation as that sequence. One infamous example was the VAX's INDEX instruction. The Berkeley work also turned up a number of additional points. Among these was the fact that programs spent a significant amount of time performing

subroutine In computer programming, a function (also procedure, method, subroutine, routine, or subprogram) is a callable unit of software logic that has a well-defined interface and behavior and can be invoked multiple times. Callable units provide a ...

calls and returns, and it seemed there was the potential to improve overall performance by speeding these calls. This led the Berkeley design to select a method known as register windows, which can significantly improve subroutine performance, although at the cost of some complexity. They also noticed that the majority of mathematical instructions were simple assignments; only of them actually performed an operation like addition or subtraction. But when those operations did occur, they tended to be slow. This led to far more emphasis on the underlying arithmetic data unit, as opposed to previous designs where the majority of the chip was dedicated to control and microcode. The resulting Berkeley RISC was based on gaining performance through the use of pipelining and aggressive use of register windowing. A
PDF
/ref> In a traditional CPU, one has a small number of registers, and a program can use any register at any time. In a CPU with register windows, there are a huge number of registers, e.g., 128, but programs can only use a small number of them, e.g., eight, at any one time. A program that limits itself to eight registers per procedure can make very fast procedure calls: The call simply moves the window "down" by eight, to the set of eight registers used by that procedure, and the return moves the window back. The Berkeley RISC project delivered the RISC-I processor in 1982. Consisting of only 44,420 transistors (compared with averages of about 100,000 in newer CISC designs of the era), RISC-I had only 32 instructions, and yet completely outperformed any other single-chip design, with estimated performance being higher than the VAX. They followed this up with the 40,760-transistor, 39-instruction RISC-II in 1983, which ran over three times as fast as RISC-I. As the RISC project began to become known in

Silicon Valley Silicon Valley is a region in Northern California that is a global center for high technology and innovation. Located in the southern part of the San Francisco Bay Area, it corresponds roughly to the geographical area of the Santa Clara Valley ...

, a similar project began at

Stanford University Leland Stanford Junior University, commonly referred to as Stanford University, is a Private university, private research university in Stanford, California, United States. It was founded in 1885 by railroad magnate Leland Stanford (the eighth ...

in 1981. This MIPS project grew out of a graduate course by John L. Hennessy, produced a functioning system in 1983, and could run simple programs by 1984. The MIPS approach emphasized an aggressive clock cycle and the use of the pipeline, making sure it could be run as "full" as possible. The MIPS system was followed by the MIPS-X, and in 1984 Hennessy and his colleagues formed

MIPS Computer Systems MIPS Tech LLC, formerly MIPS Computer Systems, Inc. and MIPS Technologies, Inc., is an American fabless semiconductor design company that is most widely known for developing the MIPS architecture and a series of RISC CPU chips based on it. MIP ...

to produce the design commercially. The venture resulted in a new architecture that was also called MIPS and the R2000 microprocessor in 1985. The overall philosophy of the RISC concept was widely understood by the second half of the 1980s and led the designers of the

MIPS-X MIPS-X is a reduced instruction set computer (RISC) microprocessor and instruction set architecture (ISA) developed as a follow-on project to the Stanford MIPS, MIPS project at Stanford University by the same team that developed MIPS. The project ...

to put it this way in 1987: Competition between RISC and conventional CISC approaches was also the subject of theoretical analysis in the early 1980s, leading, for example, to the iron law of processor performance. Yunsup Lee holding RISC V prototype chip

Yunsup Lee holding RISC V prototype chip

Since 2010, a new

open standard An open standard is a standard that is openly accessible and usable by anyone. It is also a common prerequisite that open standards use an open license that provides for extensibility. Typically, anybody can participate in their development due to ...

instruction set architecture In computer science, an instruction set architecture (ISA) is an abstract model that generally defines how software controls the CPU in a computer or a family of computers. A device or program that executes instructions described by that ISA, ...

(ISA), Berkeley

, has been under development at the University of California, Berkeley, for research purposes and as a free alternative to proprietary ISAs. As of 2014, version 2 of the

user space A modern computer operating system usually uses virtual memory to provide separate address spaces or regions of a single address space, called user space and kernel space. This separation primarily provides memory protection and hardware prote ...

ISA is fixed. The ISA is designed to be extensible from a barebones core sufficient for a small embedded processor to supercomputer and cloud computing use with standard and chip designer–defined extensions and coprocessors. It has been tested in silicon design with the ROCKET SoC, which is also available as an open-source processor generator in the CHISEL language.

Commercial breakout

In the early 1980s, significant uncertainties surrounded the RISC concept. One concern involved the use of memory; a single instruction from a traditional processor like the Motorola 68k may be written out as perhaps a half dozen of the simpler RISC instructions. In theory, this could slow the system down as it spent more time fetching instructions from memory. But by the mid-1980s, the concepts had matured enough to be seen as commercially viable.''Funding a Revolution: Government Support for Computing Research'' by Committee on Innovations in Computing and Communications 1999 page 239 Acorn-ARM-Evaluation-System

Commercial RISC designs began to emerge in the mid-1980s. The Acorn ARM1 appeared in April 1985, MIPS R2000 appeared in January 1986, followed shortly thereafter by

Hewlett-Packard The Hewlett-Packard Company, commonly shortened to Hewlett-Packard ( ) or HP, was an American multinational information technology company. It was founded by Bill Hewlett and David Packard in 1939 in a one-car garage in Palo Alto, California ...

in some of their computers. In the meantime, the Berkeley effort had become so well known that it eventually became the name for the entire concept. In 1987

Sun Microsystems Sun Microsystems, Inc., often known as Sun for short, was an American technology company that existed from 1982 to 2010 which developed and sold computers, computer components, software, and information technology services. Sun contributed sig ...

began shipping systems with the SPARC processor, directly based on the Berkeley RISC-II system. The US government Committee on Innovations in Computing and Communications credits the acceptance of the viability of the RISC concept to the success of the SPARC system. A benefit of RISC to the industry was much lower prices than the sole sourced

Intel 80386 The Intel 386, originally released as the 80386 and later renamed i386, is the third-generation x86 architecture microprocessor from Intel. It was the first 32-bit computing, 32-bit processor in the line, making it a significant evolution in ...

; by 1989 many RISC CPUs were available, and competition lowered their price to $10 per MIPS in large quantities. The performance of IBM's RISC CPU—only available in the RT PC—was less competitive than others, but the success of SPARC renewed interest within IBM, which released new RISC systems by 1990 and by 1995 RISC processors were the foundation of a $15 billion server industry. Patterson was a consultant for

Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and Delaware General Corporation Law, incorporated in Delaware. Intel designs, manufactures, and sells computer compo ...

during the 1980s. Despite dominating the microprocessor market with the CISC 80386 and its successors, the consensus that RISC was the future of the industry influenced that company's engineers, who worked to improve the performance of their processors to match RISC. By the later 1980s, new RISC designs were easily outperforming all CISC designs by a wide margin. Other vendors began their own RISC efforts. Among these were the

DEC Alpha Alpha (original name Alpha AXP) is a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). Alpha was designed to replace 32-bit VAX complex instruction set computers ( ...

, Intel i860 and i960, Motorola 88000, IBM POWER, and, slightly later, the IBM/Apple/Motorola

. Many of these have since disappeared due to them often offering no competitive advantage over others of the same era. Those that remain are often used only in niche markets or as parts of other systems; of the designs from these traditional vendors, only SPARC and POWER have any significant remaining market. The

ARM architecture ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer, RISC instruction set architectures (ISAs) for central processing unit, com ...

has been the most widely adopted RISC ISA, initially intended to deliver higher-performance desktop computing, at low cost, and in a restricted thermal package, such as in the

Acorn Archimedes The Acorn Archimedes is a family of personal computers designed by Acorn Computers of Cambridge, England. The systems in this family use Acorn's own ARM architecture processors and initially ran the Arthur operating system, with later models ...

, while featuring in the Super Computer League tables, its initial, relatively, lower power and cooling implementation was soon adapted to embedded applications, such as laser printer raster image processing. Acorn, in partnership with Apple Inc, and VLSI, creating ARM Ltd, in 1990, to share R&D costs and find new markets for the ISA, who in partnership with TI, GEC, Sharp, Nokia, Oracle and Digital would develop low-power and embedded RISC designs, and target those market segments, which at the time were niche. With the rise in mobile, automotive, streaming, smart device computing, ARM became the most widely used ISA, the company estimating almost half of all CPUs shipped in history have been ARM.

Characteristics and design philosophy

Confusion around the definition of RISC deriving from the formulation of the term, along with the tendency to opportunistically categorize processor architectures with relatively few instructions (or groups of instructions) as RISC architectures, led to attempts to define RISC as a design philosophy. One attempt to do so was expressed as the following:

Instruction set philosophy

A common misunderstanding of the phrase "reduced instruction set computer" is that instructions are simply eliminated, resulting in a smaller set of instructions. In fact, over the years, RISC instruction sets have grown in size, and today many of them have a larger set of instructions than many CISC CPUs. Some RISC processors such as the PowerPC have instruction sets as large as the CISC

IBM System/370 The IBM System/370 (S/370) is a range of IBM mainframe computers announced as the successors to the IBM System/360, System/360 family on June 30, 1970. The series mostly maintains backward compatibility with the S/360, allowing an easy migrati ...

, for example; conversely, the DEC

PDP-8 The PDP-8 is a family of 12-bit minicomputers that was produced by Digital Equipment Corporation (DEC). It was the first commercially successful minicomputer, with over 50,000 units sold during the model's lifetime. Its basic design follows the pi ...

—clearly a CISC CPU because many of its instructions involve multiple memory accesses—has only 8 basic instructions and a few extended instructions. The term "reduced" in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced—at most a single data memory cycle—compared to the "complex instructions" of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction. The term '' load–store architecture'' is sometimes preferred. Another way of looking at the RISC/CISC debate is to consider what is exposed to the compiler. In a CISC processor, the hardware may internally use registers and flag bit in order to implement a single complex instruction such as , but hide those details from the compiler. The internal operations of a RISC processor are "exposed to the compiler", leading to the

backronym A backronym is an acronym formed from an already existing word by expanding its letters into the words of a phrase. Backronyms may be invented with either serious or humorous intent, or they may be a type of false etymology or folk etymology. The ...

'Relegate Interesting Stuff to the Compiler'.

Instruction format

Most RISC architectures have fixed-length instructions and a simple encoding, which simplifies fetch, decode, and issue logic considerably. This is among the main goals of the RISC approach. Some of this is possible only due to the contemporary move to 32-bit formats. For instance, in a typical program, over 30% of all the numeric constants are either 0 or 1, 95% will fit in one byte, and 99% in a 16-bit value. When computers were based on 8- or 16-bit words, it would be difficult to have an immediate combined with the opcode in a single memory word, although certain instructions like increment and decrement did this implicitly by using a different opcode. In contrast, a 32-bit machine has ample room to encode an immediate value, and doing so avoids the need to do a second memory read to pick up the value. This is why many RISC processors allow a 12- or 13-bit constant to be encoded directly into the instruction word. Assuming a 13-bit constant area, as is the case in the MIPS and RISC designs, another 19 bits are available for the instruction encoding. This leaves ample room to indicate both the opcode and one or two registers. Register-to-register operations, mostly math and logic, require enough bits to encode the two or three registers being used. Most processors use the three-operand format , in which case three register numbers are needed. If the processor has 32 registers, each one requires a 5-bit number for 15 bits total. If one of these registers is replaced by an immediate, there is still room to encode the two remaining registers and the opcode. Common instructions found in multi-word systems, like and , which reduce the number of words that have to be read before performing the instruction, are unnecessary in RISC as they can be accomplished with a single register and the immediate value 1. The original RISC-I format remains a canonical example of the concept. It uses 7 bits for the opcode and a 1-bit flag for conditional codes, the following 5 bits for the destination register, and the next five for the first operand. This leaves 14 bits, the first of which indicates whether the following 13 contain an immediate value or uses only five of them to indicate a register for the second operand. A more complex example is the MIPS encoding, which used only 6 bits for the opcode, followed by two 5-bit registers. The remaining 16 bits could be used in two ways, one as a 16-bit immediate value, or as a 5-bit shift value (used only in shift operations, otherwise zero) and the remaining 6 bits as an extension on the opcode. In the case of register-to-register arithmetic operations, the opcode was 0 and the last 6 bits contained the actual code; those that used an immediate value used the normal opcode field at the front. One drawback of 32-bit instructions is reduced code density, which is more adverse a characteristic in embedded computing than it is in the workstation and server markets RISC architectures were originally designed to serve. To address this problem, several architectures, such as

(1992),

ARM thumb ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of RISC instruction set architectures (ISAs) for computer processors. Arm Holdings develops the ISAs and lice ...

(1994), MIPS16e (2004), Power Variable Length Encoding ISA (2006),

, and the Adapteva Epiphany, have an optional short, feature-reduced compressed instruction set. Generally, these instructions expose a smaller number of registers and fewer bits for immediate values, and often use a two-operand format to eliminate one register number from instructions. A two-operand format in a system with 16 registers requires 8 bits for register numbers, leaving another 8 for an opcode or other uses. The SH5 also follows this pattern, albeit having evolved in the opposite direction, having added longer 32-bit instructions to an original 16-bit encoding.

Hardware utilization

The most characteristic aspect of RISC is executing at least one

instruction per cycle In computer architecture, instructions per cycle (IPC), commonly called instructions per clock, is one aspect of a processor's performance: the average number of instructions executed for each clock cycle. It is the multiplicative inverse of ...

. Single-cycle operation is described as "the rapid execution of simple functions that dominate a computer's instruction stream", thus seeking to deliver an average throughput approaching one instruction per cycle for any single instruction stream. Other features of RISC architectures include: * Far fewer

transistor A transistor is a semiconductor device used to Electronic amplifier, amplify or electronic switch, switch electrical signals and electric power, power. It is one of the basic building blocks of modern electronics. It is composed of semicondu ...

s dedicated to the core logic, which originally allowed designers to increase the size of the register set and increase internal parallelism. * Uniform instruction format, using single word with the opcode in the same bit positions for simpler decoding * All

general-purpose register A processor register is a quickly accessible location available to a computer's processor. Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-onl ...

s can be used equally as source/destination in all instructions, simplifying compiler design (

floating-point In computing, floating-point arithmetic (FP) is arithmetic on subsets of real numbers formed by a ''significand'' (a Sign (mathematics), signed sequence of a fixed number of digits in some Radix, base) multiplied by an integer power of that ba ...

registers are often kept separate) * Simple addressing modes with complex addressing performed by instruction sequences * Few

data type In computer science and computer programming, a data type (or simply type) is a collection or grouping of data values, usually specified by a set of possible values, a set of allowed operations on these values, and/or a representation of these ...

s in hardware (no

byte The byte is a unit of digital information that most commonly consists of eight bits. Historically, the byte was the number of bits used to encode a single character of text in a computer and for this reason it is the smallest addressable un ...

string String or strings may refer to: *String (structure), a long flexible structure made from threads twisted together, which is used to tie, bind, or hang other objects Arts, entertainment, and media Films * ''Strings'' (1991 film), a Canadian anim ...

binary-coded decimal In computing and electronic systems, binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each digit is represented by a fixed number of bits, usually four or eight. Sometimes, special bit patterns are used f ...

CD for example) RISC designs are also more likely to feature a Harvard memory model, where the instruction stream and the data stream are conceptually separated; this means that modifying the memory where code is held might not have any effect on the instructions executed by the processor (because the CPU has a separate instruction and data cache), at least until a special synchronization instruction is issued; CISC processors that have separate instruction and data caches generally keep them synchronized automatically, for backwards compatibility with older processors. Many early RISC designs also shared the characteristic of having a

branch delay slot In computer architecture, a delay slot is an instruction slot being executed without the effects of a preceding instruction. The most common form is a single arbitrary instruction located immediately after a branch instruction on a RISC or DS ...

, an instruction space immediately following a jump or branch. The instruction in this space is executed, whether or not the branch is taken (in other words the effect of the branch is delayed). This instruction keeps the ALU of the CPU busy for the extra time normally needed to perform a branch. Nowadays the branch delay slot is considered an unfortunate side effect of a particular strategy for implementing some RISC designs, and modern RISC designs generally do away with it (such as PowerPC and more recent versions of SPARC and MIPS). Some aspects attributed to the first RISC-''labeled'' designs around 1975 include the observations that the memory-restricted compilers of the time were often unable to take advantage of features intended to facilitate ''manual'' assembly coding, and that complex addressing modes take many cycles to perform due to the required additional memory accesses. It was argued that such functions would be better performed by sequences of simpler instructions if this could yield implementations small enough to leave room for many registers, reducing the number of slow memory accesses. In these simple designs, most instructions are of uniform length and similar structure, arithmetic operations are restricted to CPU registers and only separate ''load'' and ''store'' instructions access memory. These properties enable a better balancing of pipeline stages than before, making RISC pipelines significantly more efficient and allowing higher

clock frequencies Clock rate or clock speed in computing typically refers to the frequency at which the clock generator of a Microprocessor, processor can generate Clock signal, pulses used to Synchronization (computer science), synchronize the operations of it ...

. Yet another impetus of both RISC and other designs came from practical measurements on real-world programs. Andrew Tanenbaum summed up many of these, demonstrating that processors often had oversized immediates. For instance, he showed that 98% of all the constants in a program would fit in 13 bits, yet many CPU designs dedicated 16 or 32 bits to store them. This suggests that, to reduce the number of memory accesses, a fixed length machine could store constants in unused bits of the instruction word itself, so that they would be immediately ready when the CPU needs them (much like immediate addressing in a conventional design). This required small opcodes in order to leave room for a reasonably sized constant in a 32-bit instruction word. Since many real-world programs spend most of their time executing simple operations, some researchers decided to focus on making those operations as fast as possible. The

clock rate Clock rate or clock speed in computing typically refers to the frequency at which the clock generator of a processor can generate pulses used to synchronize the operations of its components. It is used as an indicator of the processor's s ...

of a CPU is limited by the time it takes to execute the slowest ''sub-operation'' of any instruction; decreasing that cycle-time often accelerates the execution of other instructions. The focus on "reduced instructions" led to the resulting machine being called a "reduced instruction set computer" (RISC). The goal was to make instructions so simple that they could ''easily'' be pipelined, in order to achieve a ''single clock'' throughput at ''high frequencies''. This contrasted with CISC designs whose "crucial arithmetic operations and register transfers" were considered difficult to pipeline. Later, it was noted that one of the most significant characteristics of RISC processors was that external memory was only accessible by a ''load'' or ''store'' instruction. All other instructions were limited to internal registers. This simplified many aspects of processor design: allowing instructions to be fixed-length, simplifying pipelines, and isolating the logic for dealing with the delay in completing a memory access (cache miss, etc.) to only two instructions. This led to RISC designs being referred to as ''load–store'' architectures.

Comparison to other architectures

Some CPUs have been specifically designed to have a very small set of instructions—but these designs are very different from classic RISC designs, so they have been given other names such as minimal instruction set computer (MISC) or transport triggered architecture (TTA). RISC architectures have traditionally had few successes in the desktop PC and commodity server markets, where the

x86 x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel, based on the 8086 microprocessor and its 8-bit-external-bus variant, the 8088. Th ...

-based platforms remain the dominant processor architecture. However, this may change, as ARM-based processors are being developed for higher performance systems. Manufacturers including

Cavium Cavium, Inc. was a fabless semiconductor company based in San Jose, California, specializing in ARM-based and MIPS-based network, video and security processors and SoCs. The company was co-founded in 2000 by Syed B. Ali and M. Raghib Hussain, ...

, AMD, and

Qualcomm Qualcomm Incorporated () is an American multinational corporation headquartered in San Diego, California, and Delaware General Corporation Law, incorporated in Delaware. It creates semiconductors, software and services related to wireless techn ...

have released server processors based on the ARM architecture. ARM further partnered with

Cray Cray Inc., a subsidiary of Hewlett Packard Enterprise, is an American supercomputer manufacturer headquartered in Seattle, Washington. It also manufactures systems for data storage and analytics. Several Cray supercomputer systems are listed ...

in 2017 to produce an ARM-based supercomputer. On the desktop, Microsoft announced that it planned to support the PC version of

Windows 10 Windows 10 is a major release of Microsoft's Windows NT operating system. The successor to Windows 8.1, it was Software release cycle#Release to manufacturing (RTM), released to manufacturing on July 15, 2015, and later to retail on July 2 ...

on Qualcomm Snapdragon-based devices in 2017 as part of its partnership with Qualcomm. These devices will support Windows applications compiled for 32-bit x86 via an x86 processor

emulator In computing, an emulator is Computer hardware, hardware or software that enables one computer system (called the ''host'') to behave like another computer system (called the ''guest''). An emulator typically enables the host system to run sof ...

that translates 32-bit x86 code to ARM64 code. Apple announced they will transition their Mac desktop and laptop computers from Intel processors to internally developed ARM64-based

SoCs SOCS (suppressor of cytokine signaling proteins) refers to a family of genes involved in inhibiting the JAK-STAT signaling pathway. Genes * CISH (gene), CISH * SOCS1 * SOCS2 * SOCS3 * SOCS4 * SOCS5 * SOCS6 * SOCS7 Structure All SOCS have certai ...

called

Apple silicon Apple silicon is a series of system on a chip (SoC) and system in a package (SiP) processors designed by Apple Inc., mainly using the ARM architecture family, ARM architecture. They are used in nearly all of the company's devices including Mac ...

; the first such computers, using the

Apple M1 Apple M1 is a series of ARM-based system-on-a-chip (SoC) designed by Apple Inc., launched 2020 to 2022. It is part of the Apple silicon series, as a central processing unit (CPU) and graphics processing unit (GPU) for its Mac desktops and no ...

processor, were released in November 2020. Macs with Apple silicon can run x86-64 binaries with Rosetta 2, an x86-64 to ARM64 translator. Outside of the desktop arena, however, the ARM RISC architecture is in widespread use in smartphones, tablets and many forms of embedded devices. While early RISC designs differed significantly from contemporary CISC designs, by 2000 the highest-performing CPUs in the RISC line were almost indistinguishable from the highest-performing CPUs in the CISC line.

Use of RISC architectures

RISC architectures are now used across a range of platforms, from smartphones and

tablet computer A tablet computer, commonly shortened to tablet, is a mobile device, typically with a mobile operating system and touchscreen display processing circuitry, and a rechargeable battery in a single, thin and flat package. Tablets, being computers ...

s to some of the world's fastest

s such as Fugaku, the fastest on the

TOP500 The TOP500 project ranks and details the 500 most powerful non-distributed computing, distributed computer systems in the world. The project was started in 1993 and publishes an updated list of the supercomputers twice a year. The first of these ...

list , and

Summit A summit is a point on a surface that is higher in elevation than all points immediately adjacent to it. The topographic terms acme, apex, peak (mountain peak), and zenith are synonymous. The term (mountain top) is generally used only for ...

, Sierra, and

Sunway TaihuLight The Sunway TaihuLight ( ''Shénwēi·tàihú zhī guāng'') is a Chinese supercomputer which, , is ranked 11th in the TOP500 list, with a LINPACK benchmark rating of 93 petaflops. The name is translated as ''divine power, the light of Taihu Lake ...

, the next three on that list.

Low-end and mobile systems

By the beginning of the 21st century, the majority of low-end and mobile systems relied on RISC architectures. Examples include: * The

dominates the market for low-power and low-cost embedded systems (typically 200–1800 MHz in 2014). It is used in a number of systems such as most Android-based systems, the Apple

iPhone The iPhone is a line of smartphones developed and marketed by Apple that run iOS, the company's own mobile operating system. The first-generation iPhone was announced by then–Apple CEO and co-founder Steve Jobs on January 9, 2007, at ...

iPod Touch The iPod Touch (stylized as iPod touch) is a discontinued line of iOS-based mobile devices designed and formerly marketed by Apple Inc. with a touchscreen-controlled user interface. As with other iPod models, the iPod Touch can be used as a po ...

iPad The iPad is a brand of tablet computers developed and marketed by Apple Inc., Apple that run the company's mobile operating systems iOS and later iPadOS. The IPad (1st generation), first-generation iPad was introduced on January 27, 2010. ...

Apple Watch The Apple Watch is a brand of smartwatch products developed and marketed by Apple Inc., Apple. It incorporates activity tracker, fitness tracking, Health (Apple), health-oriented capabilities, and wireless telecommunication, and integrates wit ...

, and

Apple TV Apple TV is a digital media player and a microconsole developed and marketed by Apple. It is a small piece of networking hardware that sends received media data such as video and audio to a TV or external display. Its media services include ...

Palm Palm most commonly refers to: * Palm of the hand, the central region of the front of the hand * Palm plants, of family Arecaceae ** List of Arecaceae genera **Palm oil * Several other plants known as "palm" Palm or Palms may also refer to: Music ...

, Microsoft

Windows Phone Windows Phone (WP) is a discontinued mobile operating system developed by Microsoft Mobile for smartphones as the replacement successor to Windows Mobile and Zune. Windows Phone featured a new user interface derived from the Metro design languag ...

(former

Windows Mobile Windows Mobile is a discontinued mobile operating system developed by Microsoft for smartphones and personal digital assistants (PDA). Designed to be the portable equivalent of the Windows desktop OS in the emerging Mobile device, mobile/port ...

/ Windows CE), RIM devices, Nintendo

Game Boy Advance The (GBA) is a 32-bit handheld game console, manufactured by Nintendo, which was released in Japan on March 21, 2001, and to international markets that June. It was later released in mainland China in 2004, under the name iQue Game Boy Advanc ...

, DS, 3DS and

Switch In electrical engineering, a switch is an electrical component that can disconnect or connect the conducting path in an electrical circuit, interrupting the electric current or diverting it from one conductor to another. The most common type o ...

Raspberry Pi Raspberry Pi ( ) is a series of small single-board computers (SBCs) developed in the United Kingdom by the Raspberry Pi Foundation in collaboration with Broadcom Inc., Broadcom. To commercialize the product and support its growing demand, the ...

, etc. * IBM's PowerPC was used in the

GameCube The is a PowerPC-based home video game console developed and marketed by Nintendo. It was released in Japan on September 14, 2001, in North America on November 18, 2001, in Europe on May 3, 2002, and in Australia on May 17, 2002. It is the suc ...

, Wii,

PlayStation 3 The PlayStation 3 (PS3) is a home video game console developed and marketed by Sony Computer Entertainment (SCE). It is the successor to the PlayStation 2, and both are part of the PlayStation brand of consoles. The PS3 was first released on ...

Xbox 360 The Xbox 360 is a home video game console developed by Microsoft. As the successor to the Xbox (console), original Xbox, it is the second console in the Xbox#Consoles, Xbox series. It was officially unveiled on MTV on May 12, 2005, with detail ...

and

Wii U The Wii U ( ) is a home video game console developed by Nintendo as the successor to the Wii. Released in late 2012, it is the first eighth-generation video game console and competed with Microsoft's Xbox One and Sony's PlayStation 4. The W ...

gaming consoles. * The MIPS line (at one point used in many SGI computers) was used in the

PlayStation is a video gaming brand owned and produced by Sony Interactive Entertainment (SIE), a division of Japanese conglomerate Sony. Its flagship products consists of a series of home video game consoles produced under the brand; it also consists ...

PlayStation 2 The PlayStation 2 (PS2) is a home video game console developed and marketed by Sony Interactive Entertainment, Sony Computer Entertainment. It was first released in Japan on 4 March 2000, in North America on 26 October, in Europe on 24 Novembe ...

Nintendo 64 The (N64) is a home video game console developed and marketed by Nintendo. It was released in Japan on June 23, 1996, in North America on September 29, 1996, and in Europe and Australia on March 1, 1997. As the successor to the Super Nintendo E ...

PlayStation Portable The PlayStation Portable (PSP) is a handheld game console developed and marketed by Sony Interactive Entertainment, Sony Computer Entertainment. It was first released in Japan on December 12, 2004, in North America on March 24, 2005, and in PA ...

game consoles, and

residential gateway A residential gateway is a small consumer-grade gateway which bridges network access between connected local area network (LAN) hosts to a wide area network (WAN) (such as the Internet) via a modem, or directly connects to a WAN (as in EttH), ...

s like Linksys WRT54G series. *

Hitachi () is a Japanese Multinational corporation, multinational Conglomerate (company), conglomerate founded in 1910 and headquartered in Chiyoda, Tokyo. The company is active in various industries, including digital systems, power and renewable ener ...

, originally in wide use in the

32X The 32X is an video game accessory, add-on for the Sega Genesis video game console. Codenamed "Project Mars", it was designed to expand the power of the Genesis and serve as a transitional console into the History of video game consoles (fifth ...

Saturn Saturn is the sixth planet from the Sun and the second largest in the Solar System, after Jupiter. It is a gas giant, with an average radius of about 9 times that of Earth. It has an eighth the average density of Earth, but is over 95 tim ...

, and

Dreamcast The is the final home video game console manufactured by Sega. It was released in Japan on November 27, 1998, in North America on September 9, 1999 and in Europe on October 14, 1999. It was the first sixth-generation video game console, prec ...

consoles, now developed and sold by Renesas as the SH4. *

, used in a variety of products ranging from

Xbox Xbox is a video gaming brand that consists of four main home video game console lines, as well as application software, applications (games), the streaming media, streaming service Xbox Cloud Gaming, and online services such as the Xbox networ ...

handheld controllers and the

Arduino Arduino () is an Italian open-source hardware and open-source software, software company, project, and user community that designs and manufactures single-board microcontrollers and microcontroller kits for building digital devices. Its hardwar ...

open-source microcontroller platform to

BMW Bayerische Motoren Werke AG, trading as BMW Group (commonly abbreviated to BMW (), sometimes anglicised as Bavarian Motor Works), is a German multinational manufacturer of vehicles and motorcycles headquartered in Munich, Bavaria, Germany. Th ...

cars. *

, the current iteration of Berkeley's

RISC ISA, with 32- or 64-bit

address space In computing, an address space defines a range of discrete addresses, each of which may correspond to a network host, peripheral device, disk sector, a memory cell or other logical or physical entity. For software programs to save and retrieve ...

s, a small core integer instruction set, and an experimental "Compressed" ISA for code density and designed for standard and special-purpose extensions.

Desktop and laptop computers

* IBM's PowerPC architecture was used in Apple's

Macintosh Mac is a brand of personal computers designed and marketed by Apple Inc., Apple since 1984. The name is short for Macintosh (its official name until 1999), a reference to the McIntosh (apple), McIntosh apple. The current product lineup inclu ...

computers from 1994, when they began a switch from

Motorola 68000 family The Motorola 68000 series (also known as 680x0, m68000, m68k, or 68k) is a family of 32-bit complex instruction set computer (CISC) microprocessors. During the 1980s and early 1990s, they were popular in personal computers and workstations and w ...

processors, to 2005, when they transitioned to Intel x86 processors. * Some

chromebook Chromebook (sometimes stylized in lowercase as chromebook) is a line of laptops, desktops, tablets and all-in-one computers that run ChromeOS, a proprietary operating system developed by Google. Chromebooks are optimised for web access. They al ...

s use ARM-based platforms since 2012. *

Apple An apple is a round, edible fruit produced by an apple tree (''Malus'' spp.). Fruit trees of the orchard or domestic apple (''Malus domestica''), the most widely grown in the genus, are agriculture, cultivated worldwide. The tree originated ...

uses inhouse-designed processors based on the ARM architecture for its lineup of desktop and laptop computers since its transition from

processors, and the first such computers were released in November 2020. *

Microsoft Microsoft Corporation is an American multinational corporation and technology company, technology conglomerate headquartered in Redmond, Washington. Founded in 1975, the company became influential in the History of personal computers#The ear ...

uses Qualcomm ARM-based processors for its

Surface A surface, as the term is most generally used, is the outermost or uppermost layer of a physical object or space. It is the portion or region of the object that can first be perceived by an observer using the senses of sight and touch, and is ...

line.

HP Inc HP Inc. is an American Multinational corporation, multinational information technology, information technology company with its headquarters in Palo Alto, California, that develops personal computers (PCs), printer (computing), printers and re ...

and

Lenovo Lenovo Group Limited, trading as Lenovo ( , zh, c=联想, p=Liánxiǎng), is a Chinese multinational technology company specializing in designing, manufacturing, and marketing consumer electronics, personal computers, software, servers, conv ...

have released

Windows Windows is a Product lining, product line of Proprietary software, proprietary graphical user interface, graphical operating systems developed and marketed by Microsoft. It is grouped into families and subfamilies that cater to particular sec ...

PCs with an ARM-based Qualcomm Snapdragon.

Workstations, servers, and supercomputers

* MIPS, by

Silicon Graphics Silicon Graphics, Inc. (stylized as SiliconGraphics before 1999, later rebranded SGI, historically known as Silicon Graphics Computer Systems or SGCS) was an American high-performance computing manufacturer, producing computer hardware and soft ...

(ceased making MIPS-based systems in 2006). * SPARC, by

Oracle An oracle is a person or thing considered to provide insight, wise counsel or prophetic predictions, most notably including precognition of the future, inspired by deities. If done through occultic means, it is a form of divination. Descript ...

(previously

), and Fujitsu. *

's IBM POWER architecture, PowerPC, and

were and are used in many of IBM's supercomputers, mid-range servers and workstations. *

, also known as HP-PA (discontinued at the end of 2008). *

, used in

single-board computer A single-board computer (SBC) is a complete computer built on a single circuit board, with microprocessor(s), memory, input/output (I/O) and other features required of a functional computer. Single-board computers are commonly made as demonst ...

s, workstations, servers and supercomputers from

Digital Equipment Corporation Digital Equipment Corporation (DEC ), using the trademark Digital, was a major American company in the computer industry from the 1960s to the 1990s. The company was co-founded by Ken Olsen and Harlan Anderson in 1957. Olsen was president until ...

, then

Compaq Compaq Computer Corporation was an American information technology, information technology company founded in 1982 that developed, sold, and supported computers and related products and services. Compaq produced some of the first IBM PC compati ...

and finally

(HP)(discontinued as of 2007). *

, the fifth Berkeley RISC ISA, with 64- or 128-bit address spaces, and the integer core extended with floating point, atomics and

vector processing In computing, a vector processor or array processor is a central processing unit (CPU) that implements an instruction set where its Instruction (computer science), instructions are designed to operate efficiently and effectively on large Array d ...

, and designed to be extended with instructions for networking, I/O, and data processing. A specification for a 64-bit superscalar design, "Rocket", is available for download. It is implemented in the European Processor Initiative processor. * The

currently in use by cloud providers for servers. One example is the AWS Graviton series processor used for various services on the AWS platform. ARM was also used in the Fujitsu A64FX chip to create Fugaku, the world's fastest supercomputer in 2020.

Open source, standard, or use

RISC architectures have become popular in open source processors and

soft microprocessor A soft microprocessor (also called softcore microprocessor or a soft processor) is a microprocessor core that can be wholly implemented using logic synthesis. It can be implemented via different semiconductor devices containing programmable logic ...

s since they are relatively simple to implement, which makes them suitable for

FPGA A field-programmable gate array (FPGA) is a type of configurable integrated circuit that can be repeatedly programmed after manufacturing. FPGAs are a subset of logic devices referred to as programmable logic devices (PLDs). They consist of a ...

implementations and prototyping, for instance. Examples include: *

OpenRISC OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source lic ...

, an open instruction set and micro-architecture first introduced in 2000. * Open

MIPS architecture MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies ...

, for part of 2019 the specifications were free to use, royalty free, for registered MIPS developers. * OpenSPARC, in 2005, Sun released its Ultra Sparc documentation and specifications, under the GPLv2. ** LEON, an open source, radiation-tolerant implementation of the SPARC V8 instruction set (targeting space applications). * Libre-SOC, an open source SoC based on the

with extensions for video and 3D graphics. *

, in 2010, the Berkeley RISC version 5, specification, tool chain, and brand, were made available, free of charge, for non-commercial purposes. * SuperH - J Core, in 2015, a project to offer clean room implementations of the, patent expired, Hitachi SuperH RISC ISA was started. * ARM DesignStart, in 2018 ARM, in partnership with FPGA supplier Xilinx, started to offer free access to some of ARM's IP, including FPGA specification for some older CPU cores.

Awards

In 2022 Steve Furber, John L. Hennessy, David A. Patterson and Sophie M. Wilson were awarded the

Charles Stark Draper Prize The U.S. National Academy of Engineering annually awards the Draper Prize, which is given for the advancement of engineering and the education of the public about engineering. It is one of three prizes that constitute the "Nobel Prizes of Enginee ...

by the United States

National Academy of Engineering The National Academy of Engineering (NAE) is an American Nonprofit organization, nonprofit, NGO, non-governmental organization. It is part of the National Academies of Sciences, Engineering, and Medicine (NASEM), along with the National Academ ...

for their contributions to the invention, development, and implementation of reduced instruction set computer (RISC) chips.

References

External links

* * * * {{DEFAULTSORT:Reduced Instruction Set Computing Classes of computers

History and development

IBM 801

Berkeley RISC and Stanford MIPS

Commercial breakout

Characteristics and design philosophy

Instruction set philosophy

Instruction format

Hardware utilization

Comparison to other architectures

Use of RISC architectures

Low-end and mobile systems

Desktop and laptop computers

Workstations, servers, and supercomputers

Open source, standard, or use

Awards

See also

References

External links