MOS capacitor

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. A metal-insulator-semiconductor field-effect transistor (MISFET) is a term almost synonymous with MOSFET. Another synonym is IGFET for insulated-gate field-effect transistor.

The basic principle of the field-effect transistor was first patented by Julius Edgar Lilienfeld in 1925.Lilienfeld, Julius Edgar (1926-10-08) "Method and apparatus for controlling electric currents"

upright=1.6, Two power MOSFETs in surface-mount packages. Operating as switches, each of these components can sustain a blocking voltage of 120 V in the ''off'' state, and can conduct a con­ti­nuous current of 30  A in the ''on'' state, dissipating up to about 100 watt">W and controlling a load of over 2000 W. A matchstick">watt.html" ;"title="amperes">A in the ''on'' state, dissipating up to about 100 watt">W and controlling a load of over 2000 W. A matchstick is pictured for scale.

The main advantage of a MOSFET is that it requires almost no input current to control the load current, when compared with bipolar transistors (bipolar junction transistors/BJTs). In an ''enhancement mode'' MOSFET, voltage applied to the gate terminal increases the conductivity of the device. In ''depletion mode'' transistors, voltage applied at the gate reduces the conductivity.

The "metal" in the name MOSFET is sometimes a misnomer, because the gate material can be a layer of polysilicon (polycrystalline silicon). Similarly, "oxide" in the name can also be a misnomer, as different dielectric materials are used with the aim of obtaining strong channels with smaller applied voltages.

The MOSFET is by far the most common transistor in digital circuits, as billions may be included in a memory chip or microprocessor. Since MOSFETs can be made with either p-type or n-type semiconductors, complementary pairs of MOS transistors can be used to make switching circuits with very low power consumption, in the form of CMOS logic.

file:MOSFET functioning body.svg, upright=1.6, A cross-section through an nMOSFET when the gate voltage ''V''_GS is below the threshold for making a conductive channel; there is little or no conduction between the terminals drain and source; the switch is off. When the gate is more positive, it attracts electrons, inducing an ''n''-type conductive channel in the substrate below the oxide, which allows electrons to flow between the ''n''-doped terminals; the switch is on.

file:Threshold formation nowatermark.gif, upright=1.6, Simulation of formation of inversion channel (electron density) and attainment of threshold vol­tage (IV) in a nanowire MOSFET. Note: threshold voltage for this device lies around 0.45 V

History

The basic principle of this kind of transistor was first patented by Julius Edgar Lilienfeld in 1925.

The structure resembling the MOS transistor was proposed by Bell scientists William Shockley, John Bardeen and Walter Houser Brattain, during their investigation that led to discovery of the transistor effect. The structure failed to show the anticipated effects, due to the problem of surface state: traps on the semiconductor surface that hold electrons immobile. In 1955 Carl Frosch and L. Derick accidentally grew a layer of silicon dioxide over the silicon wafer. Further research showed that silicon dioxide could prevent dopants from diffusing into the silicon wafer. Building on this work Mohamed M. Atalla showed that silicon dioxide is very effective in solving the problem of one important class of surface states.

Following this Atalla and Dawon Kahng demonstrated a device that had the structure of a modern MOS transistor. The principles behind the device were the same as the ones that were tried by Bardeen, Shockley and Brattain in their unsuccessful attempt to build a surface field-effect device.

The device was about 100 times slower than contemporary bipolar transistors and was initially seen as inferior. Nevertheless Kahng pointed out several advantages of the device, notably ease of fabrication and its application in integrated circuits.

Composition

upright=1.2, Photomicrograph of two metal-gate MOSFETs in a test pattern. Probe pads for two gates and three source/drain nodes are labeled.

Usually the semiconductor of choice is silicon. Recently, some chip manufacturers, most notably IBM and Intel, have started using an alloy of silicon and germanium ( SiGe) in MOSFET channels. Unfortunately, many semiconductors with better electrical properties than silicon, such as gallium arsenide, do not form good semiconductor-to-insulator interfaces, and thus are not suitable for MOSFETs. Research continues on creating insulators with acceptable electrical characteristics on other semiconductor materials.

To overcome the increase in power consumption due to gate current leakage, a high-κ dielectric is used instead of silicon dioxide for the gate insulator, while polysilicon is replaced by metal gates (e.g. Intel, 2009)

The gate is separated from the channel by a thin insulating layer, traditionally of silicon dioxide and later of silicon oxynitride. Some companies have started to introduce a high-κ dielectric and metal gate combination in the 45 nanometer node.

When a voltage is applied between the gate and body terminals, the electric field generated penetrates through the oxide and creates an ''inversion layer'' or ''channel'' at the semiconductor-insulator interface. The inversion layer provides a channel through which current can pass between source and drain terminals. Varying the voltage between the gate and body modulates the conductivity of this layer and thereby controls the current flow between drain and source. This is known as enhancement mode.

Operation

upright=1.2, Metal-oxide-semiconductor structure on p-type silicon

Metal-oxide-semiconductor structure

The traditional metal-oxide-semiconductor (MOS) structure is obtained by growing a layer of silicon dioxide () on top of a silicon substrate, commonly by thermal oxidation and depositing a layer of metal or polycrystalline silicon (the latter is commonly used). As the silicon dioxide is a dielectric material, its structure is equivalent to a planar capacitor, with one of the electrodes replaced by a semiconductor.

When a voltage is applied across a MOS structure, it modifies the distribution of charges in the semiconductor. If we consider a p-type semiconductor (with $N_\text$ the density of acceptors, ''p'' the density of holes; ''p = N''_A in neutral bulk), a positive voltage, $V_\text$, from gate to body (see figure) creates a depletion layer by forcing the positively charged holes away from the gate-insulator/semiconductor interface, leaving exposed a carrier-free region of immobile, negatively charged acceptor ions (see doping (semiconductor)). If $V_\text$ is high enough, a high concentration of negative charge carriers forms in an ''inversion layer'' located in a thin layer next to the interface between the semiconductor and the insulator.

Conventionally, the gate voltage at which the volume density of electrons in the inversion layer is the same as the volume density of holes in the body is called the threshold voltage. When the voltage between transistor gate and source (''V''_GS) exceeds the threshold voltage (''V''_th), the difference is known as overdrive voltage.

This structure with p-type body is the basis of the n-type MOSFET, which requires the addition of n-type source and drain regions.

MOS capacitors and band diagrams

The MOS capacitor structure is the heart of the MOSFET. Consider a MOS capacitor where the silicon base is of p-type. If a positive voltage is applied at the gate, holes which are at the surface of the p-type substrate will be repelled by the electric field generated by the voltage applied. At first, the holes will simply be repelled and what will remain on the surface will be immobile (negative) atoms of the acceptor type, which creates a depletion region on the surface. Remember that a hole is created by an acceptor atom, e.g. Boron, which has one less electron than Silicon. One might ask how can holes be repelled if they are actually non-entities? The answer is that what really happens is not that a hole is repelled, but electrons are attracted by the positive field, and fill these holes, creating a depletion region where no charge carriers exist because the electron is now fixed onto the atom and immobile.

As the voltage at the gate increases, there will be a point at which the surface above the depletion region will be converted from p-type into n-type, as electrons from the bulk area will start to get attracted by the larger electric field. This is known as ''inversion''. The threshold voltage at which this conversion happens is one of the most important parameters in a MOSFET.

In the case of a p-type bulk, inversion happens when the intrinsic energy level at the surface becomes smaller than the Fermi level at the surface. One can see this from a band diagram. Remember that the Fermi level defines the type of semiconductor in discussion. If the Fermi level is equal to the Intrinsic level, the semiconductor is of intrinsic, or pure type. If the Fermi level lies closer to the conduction band (valence band) then the semiconductor type will be of n-type (p-type). Therefore, when the gate voltage is increased in a positive sense (for the given example), this will "bend" the intrinsic energy level band so that it will curve downwards towards the valence band. If the Fermi level lies closer to the valence band (for p-type), there will be a point when the Intrinsic level will start to cross the Fermi level and when the voltage reaches the threshold voltage, the intrinsic level does cross the Fermi level, and that is what is known as inversion. At that point, the surface of the semiconductor is inverted from p-type into n-type. Remember that as said above, if the Fermi level lies above the Intrinsic level, the semiconductor is of n-type, therefore at Inversion, when the Intrinsic level reaches and crosses the Fermi level (which lies closer to the valence band), the semiconductor type changes at the surface as dictated by the relative positions of the Fermi and Intrinsic energy levels.

Structure and channel formation

upright=1.5, ''Channel formation in nMOS MOSFET shown as band diagram'': Top panels: An applied gate voltage bends bands, depleting holes from surface (left). The charge inducing the bending is balanced by a layer of negative acceptor-ion charge (right). Bottom panel: A larger applied voltage further depletes holes but conduction band lowers enough in energy to populate a conducting channel
file:Illustration of C-V measurement.gif, upright=1.5, C–V profile for a bulk MOSFET with different oxide thickness. The leftmost part of the curve corresponds to accumulation. The valley in the middle corresponds to depletion. The curve on the right corresponds to inversion

A MOSFET is based on the modulation of charge concentration by a MOS capacitance between a ''body'' electrode and a ''gate'' electrode located above the body and insulated from all other device regions by a gate dielectric layer. If dielectrics other than an oxide are employed, the device may be referred to as a metal-insulator-semiconductor FET (MISFET). Compared to the MOS capacitor, the MOSFET includes two additional terminals (''source'' and ''drain''), each connected to individual highly doped regions that are separated by the body region. These regions can be either p or n type, but they must both be of the same type, and of opposite type to the body region. The source and drain (unlike the body) are highly doped as signified by a "+" sign after the type of doping.

If the MOSFET is an n-channel or nMOS FET, then the source and drain are ''n+'' regions and the body is a ''p'' region. If the MOSFET is a p-channel or pMOS FET, then the source and drain are ''p+'' regions and the body is a ''n'' region. The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

The occupancy of the energy bands in a semiconductor is set by the position of the Fermi level relative to the semiconductor energy-band edges.

With sufficient gate voltage, the valence band edge is driven far from the Fermi level, and holes from the body are driven away from the gate.

At larger gate bias still, near the semiconductor surface the conduction band edge is brought close to the Fermi level, populating the surface with electrons in an ''inversion layer'' or ''n-channel'' at the interface between the p region and the oxide. This conducting channel extends between the source and the drain, and current is conducted through it when a voltage is applied between the two electrodes. Increasing the voltage on the gate leads to a higher electron density in the inversion layer and therefore increases the current flow between the source and drain. For gate voltages below the threshold value, the channel is lightly populated, and only a very small subthreshold conduction, subthreshold leakage current can flow between the source and the drain.

When a negative gate-source voltage (positive source-gate) is applied, it creates a ''p-channel'' at the surface of the n region, analogous to the n-channel case, but with opposite polarities of charges and voltages. When a voltage less negative than the threshold value (a negative voltage for the p-channel) is applied between gate and source, the channel disappears and only a very small subthreshold current can flow between the source and the drain. The device may comprise a silicon on insulator device in which a buried oxide is formed below a thin semiconductor layer. If the channel region between the gate dielectric and the buried oxide region is very thin, the channel is referred to as an ultrathin channel region with the source and drain regions formed on either side in or above the thin semiconductor layer. Other semiconductor materials may be employed. When the source and drain regions are formed above the channel in whole or in part, they are referred to as raised source/drain regions.

Modes of operation

file:MOSFET functioning.svg, upright=2, Source tied to the body to ensure no body bias:
top left: Subthreshold, top right: Ohmic mode, bottom left: Active mode at onset of pinch-off, bottom right: Active mode well into pinch-off – channel length modulation evident
file:mosfet n-ch circuit.svg, upright=1.2, Example application of an n-channel MOSFET. When the switch is pushed, the LED lights up. 090507 brunningsoftware.co.uk

The operation of a MOSFET can be separated into three different modes, depending on the voltages at the terminals. In the following discussion, a simplified algebraic model is used. Modern MOSFET characteristics are more complex than the algebraic model presented here.For example, see . The most recent version of the BSIM model is described in

For an ''enhancement-mode, n-channel MOSFET'', the three operational modes are:

; Cutoff, subthreshold, and weak-inversion mode

When ''V''_GS < ''V''_th:

where $V_\text$ is gate-to-source bias and $V_\text$ is the threshold voltage of the device.

According to the basic threshold model, the transistor is turned off, and there is no conduction between drain and source. A more accurate model considers the effect of thermal energy on the Fermi–Dirac distribution of electron energies which allow some of the more energetic electrons at the source to enter the channel and flow to the drain. This results in a subthreshold current that is an exponential function of gate-source voltage. While the current between drain and source should ideally be zero when the transistor is being used as a turned-off switch, there is a weak-inversion current, sometimes called subthreshold leakage.

In weak inversion where the source is tied to bulk, the current varies exponentially with $V_\text$ as given approximately by:

: $I_\text \approx I_\text e^\frac,$

where $I_\text$ = current at $V_\text = V_\text$, the thermal voltage $V_\text = kT/q$ and the slope factor ''n'' is given by:

: $n = 1 + \frac, \,$

with $C_\text$ = capacitance of the depletion layer and $C_\text$ = capacitance of the oxide layer. This equation is generally used, but is only an adequate approximation for the source tied to the bulk. For the source not tied to the bulk, the subthreshold equation for drain current in saturation is

: $I_\text \approx I_\text e^\frac e^,$

In a long-channel device, there is no drain voltage dependence of the current once $V_\text \gg V_\text$, but as channel length is reduced drain-induced barrier lowering introduces drain voltage dependence that depends in a complex way upon the device geometry (for example, the channel doping, the junction doping and so on). Frequently, threshold voltage ''V''_th for this mode is defined as the gate voltage at which a selected value of current ''I''_D0 occurs, for example, ''I''_D0 = 1μA, which may not be the same ''V''_th-value used in the equations for the following modes.

Some micropower analog circuits are designed to take advantage of subthreshold conduction. By working in the weak-inversion region, the MOSFETs in these circuits deliver the highest possible transconductance-to-current ratio, namely: $g_m/I_\text = 1/\left(nV_\text\right)$, almost that of a bipolar transistor.

The subthreshold '' I–V curve'' depends exponentially upon threshold voltage, introducing a strong dependence on any manufacturing variation that affects threshold voltage; for example: variations in oxide thickness, junction depth, or body doping that change the degree of drain-induced barrier lowering. The resulting sensitivity to fabricational variations complicates optimization for leakage and performance.

file:IvsV mosfet.svg, upright=1.2, MOSFET drain current vs. drain-to-source voltage for several values of $V_\text - V_\text$; the boundary between ''linear'' (''Ohmic'') and ''saturation'' (''active'') modes is indicated by the upward curving parabola
file:Mosfet linear.svg, upright=1.2, Cross section of a MOSFET operating in the linear (Ohmic) region; strong inversion region present even near drain
file:Mosfet saturation.svg, upright=1.2, Cross section of a MOSFET operating in the saturation (active) region; channel exhibits channel pinching near drain

; Triode mode or linear region (also known as the ohmic mode)

When ''V''_GS > ''V''_th and ''V''_DS < ''V''_GS − ''V''_th:

The transistor is turned on, and a channel has been created which allows current between the drain and the source. The MOSFET operates like a resistor, controlled by the gate voltage relative to both the source and drain voltages. The current from drain to source is modeled as:

: $I_\text = \mu_n C_\text\frac \left( \left(V_\text - V_\right)V_\text - \frac \right)$

where $\mu_n$ is the charge-carrier effective mobility, $W$ is the gate width, $L$ is the gate length and $C_\text$ is the gate oxide capacitance per unit area. The transition from the exponential subthreshold region to the triode region is not as sharp as the equations suggest.

; Saturation or active mode

When ''V_GS > V''_th and ''V_DS'' ≥ (V''_GS – V''_th):

The switch is turned on, and a channel has been created, which allows current between the drain and source. Since the drain voltage is higher than the source voltage, the electrons spread out, and conduction is not through a narrow channel but through a broader, two- or three-dimensional current distribution extending away from the interface and deeper in the substrate. The onset of this region is also known as channel length modulation, pinch-off to indicate the lack of channel region near the drain. Although the channel does not extend the full length of the device, the electric field between the drain and the channel is very high, and conduction continues. The drain current is now weakly dependent upon drain voltage and controlled primarily by the gate-source voltage, and modeled approximately as:

: I_\text = \frac\frac\left _\text - V_\text\right2 \left + \lambda (V_\text - V_\text)\right

The additional factor involving λ, the channel-length modulation parameter, models current dependence on drain voltage due to the Early effect, or channel length modulation. According to this equation, a key design parameter, the MOSFET transconductance is:

: $g_m = \frac = \frac = \frac ,$

where the combination ''V''_ov = ''V''_GS − ''V''_th is called the overdrive voltage, and where ''V''_DSsat = ''V''_GS − ''V''_th accounts for a small discontinuity in $I_\text$ which would otherwise appear at the transition between the triode and saturation regions.

Another key design parameter is the MOSFET output resistance ''r_out'' given by:

: $r_\text = \frac$.

''r''_out is the inverse of ''g''_DS where $g_\text = \frac$. ''I''_D is the expression in saturation region.

If λ is taken as zero, an infinite output resistance of the device results that leads to unrealistic circuit predictions, particularly in analog circuits.

As the channel length becomes very short, these equations become quite inaccurate. New physical effects arise. For example, carrier transport in the active mode may become limited by velocity saturation. When velocity saturation dominates, the saturation drain current is more nearly linear than quadratic in ''V''_GS. At even shorter lengths, carriers transport with near zero scattering, known as quasi- ballistic transport. In the ballistic regime, the carriers travel at an injection velocity that may exceed the saturation velocity and approaches the Fermi velocity at high inversion charge density. In addition, drain-induced barrier lowering increases off-state (cutoff) current and requires an increase in threshold voltage to compensate, which in turn reduces the saturation current.

Body effect

upright=1.2, Band diagram showing body effect. ''V''_SB splits Fermi levels F_n for electrons and F_p for holes, requiring larger ''V''_GB to populate the conduction band in an nMOS MOSFET

The occupancy of the energy bands in a semiconductor is set by the position of the Fermi level#"Fermi level" in semiconductor physics, Fermi level relative to the semiconductor energy-band edges. Application of a source-to-substrate reverse bias of the source-body pn-junction introduces a split between the Fermi levels for electrons and holes, moving the Fermi level for the channel further from the band edge, lowering the occupancy of the channel. The effect is to increase the gate voltage necessary to establish the channel, as seen in the figure. This change in channel strength by application of reverse bias is called the 'body effect'.

Simply put, using an nMOS example, the gate-to-body bias ''V''_GB positions the conduction-band energy levels, while the source-to-body bias V_SB positions the electron Fermi level near the interface, deciding occupancy of these levels near the interface, and hence the strength of the inversion layer or channel.

The body effect upon the channel can be described using a modification of the threshold voltage, approximated by the following equation:

: $V_\text = V_ + \gamma \left( \sqrt - \sqrt \right),$

where ''V''_TB is the threshold voltage with substrate bias present, and ''V''_T0 is the zero-''V''_SB value of threshold voltage, $\gamma$ is the body effect parameter, and 2''φ''_B is the approximate potential drop between surface and bulk across the depletion layer when and gate bias is sufficient to ensure that a channel is present.

For a uniformly doped p-type substrate with bulk acceptor doping of ''N_A'' per unit volume,
: $\varphi_B = \frac \ln \left(\frac\right) \ ,$

with ''n_i'' the intrinsic mobile carrier density per unit volume in the bulk. See, for example, As this equation shows, a reverse bias causes an increase in threshold voltage ''V''_TB and therefore demands a larger gate voltage before the channel populates.

The body can be operated as a second gate, and is sometimes referred to as the "back gate"; the body effect is sometimes called the "back-gate effect".

Circuit symbols

A variety of symbols are used for the MOSFET. The basic design is generally a line for the channel with the source and drain leaving it at right angles and then bending back at right angles into the same direction as the channel. Sometimes three line segments are used for enhancement mode and a solid line for depletion mode (see depletion and enhancement modes). Another line is drawn parallel to the channel for the gate.

The ''bulk'' or ''body'' connection, if shown, is shown connected to the back of the channel with an arrow indicating pMOS or nMOS. Arrows always point from P to N, so an NMOS (N-channel in P-well or P-substrate) has the arrow pointing in (from the bulk to the channel). If the bulk is connected to the source (as is generally the case with discrete devices) it is sometimes angled to meet up with the source leaving the transistor. If the bulk is not shown (as is often the case in IC design as they are generally common bulk) an inversion symbol is sometimes used to indicate PMOS, alternatively an arrow on the source may be used in the same way as for bipolar transistors (out for nMOS, in for pMOS).

Comparison of enhancement-mode and depletion-mode MOSFET symbols, along with JFET symbols. The orientation of the symbols, (most significantly the position of source relative to drain) is such that more positive voltages appear higher on the page than less positive voltages, implying conventional current flowing "down" the page:

In schematics whe