DDR SDRAM is a double data rate synchronous dynamic random-access
memory class of memory integrated circuits used in computers. DDR
SDRAM, also called DDR1 SDRAM, has been superseded by DDR2 SDRAM, DDR3
SDRAM and DDR4 SDRAM. None of its successors are forward or backward
compatible with DDR1 SDRAM, meaning DDR2, DDR3, and DDR4 memory
modules will not work in DDR1-equipped motherboards, and vice versa.
Compared to single data rate (SDR) SDRAM, the
DDR SDRAM interface
makes higher transfer rates possible by more strict control of the
timing of the electrical data and clock signals. Implementations often
have to use schemes such as phase-locked loops and self-calibration to
reach the required timing accuracy. The interface uses double
pumping (transferring data on both the rising and falling edges of the
clock signal) to double data bus bandwidth without a corresponding
increase in clock frequency. One advantage of keeping the clock
frequency down is that it reduces the signal integrity requirements on
the circuit board connecting the memory to the controller. The name
"double data rate" refers to the fact that a
DDR SDRAM with a certain
clock frequency achieves nearly twice the bandwidth of a SDR SDRAM
running at the same clock frequency, due to this double pumping.
With data being transferred 64 bits at a time,
DDR SDRAM gives a
transfer rate (in bytes/s) of (memory bus clock rate) × 2 (for dual
rate) × 64 (number of bits transferred) / 8 (number of bits/byte).
Thus, with a bus frequency of 100 MHz,
DDR SDRAM gives a maximum
transfer rate of 1600 MB/s.
"Beginning in 1996 and concluding in June 2000,
JEDEC developed the
DDR (Double Data Rate) SDRAM specification (JESD79)."
JEDEC has set
standards for data rates of DDR SDRAM, divided into two parts. The
first specification is for memory chips, and the second is for memory
1 Specification standards
1.1 Chips and modules
1.2 Chip characteristics
1.3 Module characteristics
Double data rate
Double data rate (DDR) SDRAM specification
1.6 High-density RAM
4 See also
6 External links
Comparison of memory modules for desktop PCs (DIMM).
Physical DDR layout
Comparison of memory modules for portable/mobile PCs (SO-DIMM).
Chips and modules
DRAM cell array clock
I/O bus clock
Peak transfer rate
Note: All above listed are specified by
JEDEC as JESD79F. All RAM
data rates in-between or above these listed specifications are not
standardized by JEDEC—often they are simply manufacturer
optimizations using tighter-tolerance or overvolted chips.
The package sizes in which
DDR SDRAM is manufactured are also
standardized by JEDEC.
There is no architectural difference between
DDR SDRAM designed for
different clock frequencies, for example, PC-1600, designed to run at
100 MHz, and PC-2100, designed to run at 133 MHz. The number
simply designates the data rate at which the chip is guaranteed to
DDR SDRAM is guaranteed to run at lower (underclocking)
and can possibly run at higher (overclocking) clock rates than those
for which it was made.
DDR SDRAM modules for desktop computers, dual in-line memory modules
(DIMMs), have 184 pins (as opposed to 168 pins on SDRAM, or 240 pins
on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the
number of notches (
DDR SDRAM has one, SDRAM has two).
DDR SDRAM for
notebook computers, SO-DIMMs, have 200 pins, which is the same number
of pins as DDR2 SO-DIMMs. These two specifications are notched very
similarly and care must be taken during insertion if unsure of a
correct match. Most
DDR SDRAM operates at a voltage of 2.5 V,
compared to 3.3 V for SDRAM. This can significantly reduce power
consumption. Chips and modules with DDR-400/PC-3200 standard have a
nominal voltage of 2.6 V.
JEDEC Standard No. 21–C defines three possible operating voltages
for 184 pin DDR, as identified by the key notch position relative to
its centreline. Page 4.5.10-7 defines 2.5V (left), 1.8V (centre), TBD
(right), while page 4.20.5–40 nominates 3.3V for the right notch
position. The orientation of the module for determining the key notch
position is with 52 contact positions to the left and 40 contact
positions to the right.
Increasing operating voltage slightly can increase maximum speed, at
the cost of higher power dissipation and heating, and at the risk of
malfunctioning or damage.
Many new chipsets use these memory types in multi-channel
Size of the chip is measured in megabits. Most motherboards recognize
only 1 GB modules if they contain 64M×8 chips (low density). If
128M×4 (high density) 1 GB modules are used, they most likely
will not work. The
JEDEC standard allows 128M×4 only for slower
buffered/registered modules designed specifically for some servers,
but some generic manufacturers do not comply.[verification needed]
The notation like 64M×4 means that the memory matrix has 64 million
(the product of banks x rows x columns) 4-bit storage locations. There
are ×4, ×8, and ×16 DDR chips. The ×4 chips allow the use of
advanced error correction features like Chipkill, memory scrubbing and
Intel SDDC in server environments, while the ×8 and ×16 chips are
somewhat less expensive. x8 chips are mainly used in
desktops/notebooks but are making entry into the server market. There
are normally 4 banks and only one row can be active in each bank.
To increase memory capacity and bandwidth, chips are combined on a
module. For instance, the 64-bit data bus for
DIMM requires eight
8-bit chips, addressed in parallel. Multiple chips with the common
address lines are called a memory rank. The term was introduced to
avoid confusion with chip internal rows and banks. A memory module may
bear more than one rank. The term sides would also be confusing
because it incorrectly suggests the physical placement of chips on the
All ranks are connected to the same memory bus (address + data). The
Chip Select signal is used to issue commands to specific rank.
Adding modules to the single memory bus creates additional electrical
load on its drivers. To mitigate the resulting bus signaling rate drop
and overcome the memory bottleneck, new chipsets employ the
Number of DRAM devices
The number of chips is a multiple of 8 for non-ECC modules and a
multiple of 9 for ECC modules. Chips can occupy one side (single
sided) or both sides (dual sided) of the module. The maximal number of
chips per DDR module is 36 (9×4) for ECC and 32 (8x4) for non-ECC.
ECC vs non-ECC
Modules that have error-correcting code are labeled as ECC. Modules
without error correcting code are labeled non-ECC.
CAS latency (CL), clock cycle time (tCK), row cycle time (tRC),
refresh row cycle time (tRFC), row active time (tRAS).
registered (or buffered) vs unbuffered.
DIMM or SO-DIMM.
A test with DDR and DDR2 RAM in 2005 found that average power
consumption appeared to be of the order of 1–3 W per
512 MB module; this increases with clock rate and when in use
rather than idling. A manufacturer has produced calculators to
estimate the power used by various types of RAM.
Module and chip characteristics are inherently linked.
Total module capacity is a product of one chip's capacity and the
number of chips. ECC modules multiply it by 8/9 because they use
1 bit per byte (8 bits) for error correction. A module of
any particular size can therefore be assembled either from 32 small
chips (36 for ECC memory), or 16(18) or 8(9) bigger ones.
DDR memory bus width per channel is 64 bits (72 for ECC memory). Total
module bit width is a product of bits per chip and number of chips. It
also equals number of ranks (rows) multiplied by DDR memory bus width.
Consequently, a module with a greater number of chips or using ×8
chips instead of ×4 will have more ranks.
Example: Variations of 1 GB PC2100 registered
DDR SDRAM module
Module size (GB)
Number of chips
Chip size (Mbit)
Number of ranks
This example compares different real-world server memory modules with
a common size of 1 GB. One should definitely be careful buying
1 GB memory modules, because all these variations can be sold
under one price position without stating whether they are ×4 or ×8,
single- or dual-ranked.
There is a common belief that number of module ranks equals number of
sides. As above data shows, this is not true. One can also find
2-side/1-rank modules. One can even think of a 1-side/2-rank memory
module having 16(18) chips on single side ×8 each, but it's unlikely
such a module was ever produced.
Double data rate
Double data rate (DDR) SDRAM specification
From Ballot JCB-99-70, and modified by numerous other Board Ballots,
formulated under the cognizance of Committee JC-42.3 on DRAM
Standard No. 79 Revision Log:
Release 1, June 2000
Release 2, May 2002
Release C, March 2003 –
JEDEC Standard No. 79C.
"This comprehensive standard defines all required aspects of 64Mb
through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including
features, functionality, ac and dc parametrics, packages and pin
assignments. This scope will subsequently be expanded to formally
apply to x32 devices, and higher density devices as well."
DDR SDRAM designed to operate at 200 MHz using DDR-400
chips with a bandwidth of 3,200 MB/s. Because PC3200 memory
transfers data on both the rising and falling clock edges, its
effective clock rate is 400 MHz.
1 GB PC3200 non-ECC modules are usually made with 16
512 Mbit chips, 8 on each side (512 Mbits × 16 chips)
/ (8 bits (per byte)) = 1,024 MB. The individual chips making up
a 1 GB memory module are usually organized as 226 8-bit words,
commonly expressed as 64M×8. Memory manufactured in this way is
low-density RAM and is usually compatible with any motherboard
specifying PC3200 DDR-400 memory.
In the context of the 1 GB non-ECC PC3200 SDRAM module, there is
very little visually to differentiate low-density from high-density
RAM. High-density DDR RAM modules will, like their low-density
counterparts, usually be double-sided with eight 512 Mbit chips
per side. The difference is that each chip, instead of being organized
as 64M×8, is organized as 227 4-bit words, or 128M×4.
High-density memory modules are assembled using chips from multiple
manufacturers. These chips come in both the familiar 22 × 10 mm
(approx.) TSOP2 and smaller squarer 12 × 9 mm (approx.) FBGA
package sizes. High-density chips can be identified by the numbers on
High-density RAM devices were designed to be used in registered memory
modules for servers.
JEDEC standards do not apply to high-density DDR
RAM in desktop implementations. JEDEC's technical
documentation, however, supports 128M×4 semiconductors as such that
contradicts 128×4 being classified as high-density[clarify]. As such,
high density is a relative term, which can be used to describe memory
that is not supported by a particular motherboard's memory
Internal memory clock
DDR (DDR1) was superseded by DDR2 SDRAM, which had modifications for
higher clock frequency and again doubled throughput, but operates on
the same principle as DDR. Competing with DDR2 was
Rambus XDR DRAM.
DDR2 dominated due to cost and support factors. DDR2 was in turn
superseded by DDR3 SDRAM, which offered higher performance for
increased bus speeds and new features. DDR3 has been superseded by
DDR4 SDRAM, which was first produced in 2011 and whose standards were
still in flux (2012) with significant architectural changes.
DDR's prefetch buffer depth is 2 (bits), while DDR2 uses 4. Although
the effective clock rates of DDR2 are higher than DDR, the overall
performance was not greater in the early implementations, primarily
due to the high latencies of the first DDR2 modules. DDR2 started to
be effective by the end of 2004, as modules with lower latencies
Memory manufacturers stated that it was impractical to mass-produce
DDR1 memory with effective transfer rates in excess of 400 MHz
(i.e. 400 MT/s and 200 MHz external clock) due to internal
speed limitations. DDR2 picks up where DDR1 leaves off, utilizing
internal clock rates similar to DDR1, but is available at effective
transfer rates of 400 MHz and higher. DDR3 advances extended the
ability to preserve internal clock rates while providing higher
effective transfer rates by again doubling the prefetch depth.
DDR4 SDRAM is a high-speed dynamic random-access memory internally
configured as 16 banks, 4 bank groups with 4 banks for each bank group
for x4/x8 and 8 banks, 2 bank groups with 4 banks for each bank group
for x16 DRAM. The
DDR4 SDRAM uses a 8n prefetch architecture to
achieve high-speed operation. The 8n prefetch architecture is combined
with an interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write operation for the DDR4 SDRAM
consists of a single 8n-bit-wide 4-clock data transfer at the internal
DRAM core and 8 corresponding n-bit-wide half-clock-cycle data
transfers at the I/O pins.
RDRAM was a particularly expensive alternative to DDR SDRAM, and most
manufacturers dropped its support from their chipsets. DDR1 memory's
prices substantially increased since Q2 2008, while DDR2 prices
declined. In January 2009, 1 GB DDR1 was 2–3 times more
expensive than 1 GB DDR2. High-density DDR RAM suit about 10% of
PC motherboards on the market, while low-density suit almost all
motherboards on the PC Desktop market.
MDDR is an acronym that some enterprises use for
Mobile DDR SDRAM, a
type of memory used in some portable electronic devices, like mobile
phones, handhelds, and digital audio players. Through techniques
including reduced voltage supply and advanced refresh options, Mobile
DDR can achieve greater power efficiency.
Serial presence detect
Fully buffered DIMM
List of device bandwidths
^ Northwest Logic DDR Phy datasheet Archived 2008-08-21 at the Wayback
^ Memory Interfaces Data Capture Using Direct Clocking Technique
(Xilinx application note)
^ "The Love/Hate Relationship with
DDR SDRAM Controllers".
^ Cycle time is the inverse of the I/O bus clock frequency; e.g.,
1/(100 MHz) = 10 ns per clock cycle.
^ DOUBLE DATA RATE (DDR) SDRAM STANDARD
^ "What is the difference between PC-2100 (DDR-266), PC-2700
(DDR-333), and PC-3200 (DDR-400)?". Micron Technology, Inc.
^ Low Density vs High Density memory modules
^ Mike Chin: Power Distribution within Six PCs.
^ Micron: System Power Calculators Archived 2016-01-26 at the Wayback
^ http://www.jedec.org/download/search/JESD79F.pdf DOUBLE DATA RATE
(DDR) SDRAM SPECIFICATION (Release F)
^ DDR2 vs. DDR: Revenge Gained Archived 2006-11-21 at the Wayback
DDR4 SDRAM Standard JESD79-4B".
Dynamic random-access memory
Dynamic random-access memory (DRAM)
Fast Cycle DRAM (FCRAM)
Mobile DDR (LPDDR)
High Bandwidth Memory
Hybrid Memory Cube