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The Apollo Guidance Computer
Apollo Guidance Computer
(AGC) was a digital computer produced for the Apollo program
Apollo program
that was installed on board each Apollo Command Module (CM) and Lunar Module
Lunar Module
(LM). The AGC provided computation and electronic interfaces for guidance, navigation, and control of the spacecraft.[2] The AGC has a 16-bit word length, with 15 data bits and one parity bit. Most of the software on the AGC is stored in a special read-only memory known as core rope memory, fashioned by weaving wires through magnetic cores, though a small amount of read-write core memory is available. Astronauts communicated with the AGC using a numeric display and keyboard called the DSKY (DiSplay&KeYboard, pronounced 'DISS-key'). The AGC and its DSKY user interface were developed in the early 1960s for the Apollo program
Apollo program
by the MIT Instrumentation Laboratory and first flew in 1966.[3] The AGC was one of the first integrated circuit-based computers. The computer's performance was comparable to the first generation of home computers from the late 1970s, such as the Apple II, TRS-80, and Commodore PET.[4]

Contents

1 Operation 2 Design

2.1 DSKY interface 2.2 Timing 2.3 Central registers 2.4 Other registers 2.5 Instruction set 2.6 Memory 2.7 Interrupts and involuntary counters 2.8 Standby mode 2.9 Data buses 2.10 Software

3 Block II 4 PGNCS trouble 5 Applications outside Apollo 6 See also 7 Notes 8 References 9 External links

Operation[edit] Each Moon flight carried two AGCs, one each in the Command Module
Command Module
and the Lunar Module, with the exception of Apollo 8
Apollo 8
which did not need a Lunar Module
Lunar Module
for its lunar orbit mission. The AGC in the Command Module was the center of its guidance, navigation and control (GNC) system. The AGC in the Lunar Module
Lunar Module
ran its Apollo PGNCS
Apollo PGNCS
(Primary Guidance, Navigation and Control System), with the acronym pronounced as pings.

The display and keyboard (DSKY) interface of the Apollo Guidance Computer mounted on the control panel of the Command Module, with the Flight Director Attitude Indicator (FDAI) above

Partial list of numeric codes for verbs and nouns in the Apollo Guidance Computer, printed for quick reference on a side panel

Each lunar mission had two additional computers:

The Launch Vehicle Digital Computer
Launch Vehicle Digital Computer
(LVDC) on the Saturn V
Saturn V
booster instrumentation ring the Abort Guidance System (AGS, pronounced ags) of the Lunar Module, to be used in the event of failure of the LM PGNCS. The AGS could be used to take off from the Moon, and to rendezvous with the Command Module, but not to land.

Design[edit]

Flatpack integrated circuits in the Apollo guidance computer

The AGC was designed at the MIT Instrumentation Laboratory
MIT Instrumentation Laboratory
under Charles Stark Draper, with hardware design led by Eldon C. Hall.[1] Early architectural work came from J.H. Laning Jr., Albert Hopkins, Richard Battin, Ramon Alonso,[5] [6] and Hugh Blair-Smith.[7] The flight hardware was fabricated by Raytheon, whose Herb Thaler[8] was also on the architectural team. The Apollo flight computer was the first computer to use integrated circuits (ICs). While the Block I version used 4,100 ICs, each containing a single three-input NOR gate, the later Block II version (used in the crewed flights) used 2,800 ICs, each with dual three-input NOR gates.[1]:34 The ICs, from Fairchild Semiconductor, were implemented using resistor–transistor logic (RTL) in a flat-pack. They were connected via wire wrap, and the wiring was then embedded in cast epoxy plastic.[citation needed] The use of a single type of IC (the dual NOR3) throughout the AGC avoided problems that plagued another early IC computer design, the Minuteman II guidance computer, which used a mix of diode–transistor logic and diode logic gates.[citation needed] The computer had 2048 words of erasable magnetic-core memory and 36 kilowords of read-only core rope memory. Both had cycle times of 11.72 microseconds. The memory word length was 16 bits: 15 bits of data and one odd-parity bit. The CPU-internal 16-bit word format was 14 bits of data, one overflow bit, and one sign bit (ones' complement representation).[citation needed] DSKY interface[edit]

Apollo computer DSKY user interface unit

LM DSKY interface diagram

The user interface to the AGC was the DSKY, standing for display and keyboard and usually pronounced dis-key. It had an array of indicator lights, numeric displays and a calculator-style keyboard. Commands were entered numerically, as two-digit numbers: Verb, and Noun. Verb described the type of action to be performed and Noun specified which data was affected by the action specified by the Verb
Verb
command. The numerals were displayed via green high-voltage electroluminescent seven-segment displays. The segments were driven by electromechanical relays, which limited the display update rate. Three five-digit signed numbers could also be displayed in octal or decimal, and were typically used to display vectors such as space craft attitude or a required velocity change (delta-V). Although data was stored internally in metric units, they were displayed as United States customary units. This calculator-style interface[nb 1] was the first of its kind, the prototype for all similar digital control panel interfaces. The Command Module
Command Module
had two DSKYs connected to its AGC: one located on the main instrument panel and a second located in the lower equipment bay near a sextant used for aligning the inertial guidance platform. The Lunar Module
Lunar Module
had a single DSKY for its AGC. A flight director attitude indicator (FDAI), controlled by the AGC, was located above the DSKY on the commander's console and on the LM. In 2009, a DSKY was sold in a public auction held by Heritage Auctions for $50,788.[9] Timing[edit] The AGC timing reference came from a 2.048 MHz crystal clock. The clock was divided by two to produce a four-phase 1.024 MHz clock which the AGC used to perform internal operations. The 1.024 MHz clock was also divided by two to produce a 512 kHz signal called the master frequency; this signal was used to synchronize external Apollo spacecraft systems. The master frequency was further divided through a scaler, first by five using a ring counter to produce a 102.4 kHz signal. This was then divided by two through 17 successive stages called F1 (51.2 kHz) through F17 (0.78125 Hz). The F10 stage (100 Hz) was fed back into the AGC to increment the real-time clock and other involuntary counters using Pinc (discussed below). The F17 stage was used to intermittently run the AGC when it was operating in the standby mode. Central registers[edit] The AGC had four 16-bit registers for general computational use, called the central registers:

A: The accumulator, for general computation

Z: The program counter – the address of the next instruction to be executed

Q: The remainder from the DV instruction, and the return address after TC instructions

LP: The lower product after MP instructions

There were also four locations in core memory, at addresses 20-23, dubbed editing locations because whatever was stored there would emerge shifted or rotated by one bit position, except for one that shifted right seven bit positions, to extract one of the seven-bit interpretive op. codes that were packed two to a word. This was common to Block I and Block II AGCs. Other registers[edit]

DSKY and AGC on display at the Computer History Museum. The AGC is opened up showing its logic modules.

Prototype logic module from Block I AGC

Block II logic module, with flat-pack ICs

AGC dual 3-input NOR gate

AGC dual 3-input NOR gate
NOR gate
schematic

The AGC had additional registers that were used internally in the course of operation:

S : 12-bit memory address register, the lower portion of the memory address

Bank/Fbank : 4-bit
4-bit
ROM bank register, to select the 1 kiloword ROM bank when addressing in the fixed-switchable mode

Ebank : 3-bit RAM bank register, to select the 256-word RAM bank when addressing in the erasable-switchable mode

Sbank (super-bank) : 1-bit extension to Fbank, required because the last 4 kilowords of the 36-kiloword ROM was not reachable using Fbank alone

SQ : 4-bit
4-bit
sequence register; the current instruction

G : 16-bit memory buffer register, to hold data words moving to and from memory

X : The 'x' input to the adder (the adder was used to perform all 1's complement arithmetic) or the increment to the program counter (Z register)

Y : The other ('y') input to the adder

U : Not really a register, but the output of the adder (the 1's complement sum of the contents of registers X and Y)

B : General-purpose buffer register, also used to pre-fetch the next instruction. At the start of the next instruction, the upper bits of B (containing the next op. code) were copied to SQ, and the lower bits (the address) were copied to S.

C : Not a separate register, but the 1's complement of the B register

IN : Four 16-bit input registers

OUT : Five 16-bit output registers

Instruction set[edit] The instruction format used 3 bits for opcode, and 12 bits for address. Block I had 11 instructions: TC, CCS, INDEX, XCH, CS, TS, AD, and MASK (basic), and SU, MP, and DV (extra). The first eight, called basic instructions, were directly accessed by the 3-bit op. code. The final three were denoted as extracode instructions because they were accessed by performing a special type of TC instruction (called EXTEND) immediately before the instruction. The Block I AGC instructions consisted of the following:

TC (transfer control) An unconditional branch to the address specified by the instruction. The return address was automatically stored in the Q register, so the TC instruction could be used for subroutine calls. CCS (count, compare, and skip) A complex conditional branch instruction. The A register was loaded with data retrieved from the address specified by the instruction. (Because the AGC uses ones' complement notation, there are two representations of zero. When all bits are set to zero, this is called plus zero. If all bits are set to one, this is called minus zero.) The diminished absolute value (DABS) of the data was then computed and stored in the A register. If the number was greater than zero, the DABS decrements the value by 1; if the number was negative, it is complemented before the decrement is applied—this is the absolute value. Diminished means "decremented but not below zero". Therefore, when the AGC performs the DABS function, positive numbers will head toward plus zero, and so will negative numbers but first revealing their negativity via the four-way skip below. The final step in CCS is a four-way skip, depending upon the data in register A before the DABS. If register A was greater than 0, CCS skips to the first instruction immediately after CCS. If register A contained plus zero, CCS skips to the second instruction after CCS. Less than zero causes a skip to the third instruction after CCS, and minus zero skips to the fourth instruction after CCS. The primary purpose of the count was to allow an ordinary loop, controlled by a positive counter, to end in a CCS and a TC to the beginning of the loop, equivalent to an IBM 360's BCT. The absolute value function was deemed important enough to be built into this instruction; when used for only this purpose, the sequence after the CCS was TC *+2, TC *+2, AD ONE. A curious side effect was the creation and use of CCS-holes when the value being tested was known to be never positive, which occurred more often than one might suppose. That left two whole words unoccupied, and a special committee was responsible for assigning data constants to these holes. INDEX Add the data retrieved at the address specified by the instruction to the next instruction. INDEX can be used to add or subtract an index value to the base address specified by the operand of the instruction that follows INDEX. This method is used to implement arrays and table look-ups; since the addition was done on both whole words, it was also used to modify the op. code in a following (extracode) instruction, and on rare occasions both functions at once. RESUME A special instance of INDEX (INDEX 25). This is the instruction used to return from interrupts. It causes execution to resume at the interrupted location. XCH (exchange) Exchange the contents of memory with the contents of the A register. If the specified memory address is in fixed (read-only) memory, the memory contents are not affected, and this instruction simply loads register A. If it is in erasable memory, overflow "correction" is achieved by storing the leftmost of the 16 bits in A as the sign bit in memory, but there is no exceptional behavior like that of TS. CS (clear and subtract) Load register A with the one's complement of the data referenced by the specified memory address. TS (transfer to storage) Store register A at the specified memory address. TS also detects, and corrects for, overflows in such a way as to propagate a carry for multi-precision add/subtract. If the result has no overflow (leftmost 2 bits of A the same), nothing special happens; if there is overflow (those 2 bits differ), the leftmost one goes the memory as the sign bit, register A is changed to +1 or −1 accordingly, and control skips to the second instruction following the TS. Whenever overflow is a possible but abnormal event, the TS was followed by a TC to the no-overflow logic; when it is a normal possibility (as in multi-precision add/subtract), the TS is followed by CAF ZERO (CAF = XCH to fixed memory) to complete the formation of the carry (+1, 0, or −1) into the next higher-precision word. Angles were kept in single precision, distances and velocities in double precision, and elapsed time in triple precision. AD (add) Add the contents of memory to register A and store the result in A. The 2 leftmost bits of A may be different (overflow state) before and/or after the AD. The fact that overflow is a state rather than an event forgives limited extents of overflow when adding more than two numbers, as long as none of the intermediate totals exceed twice the capacity of a word. MASK Perform a bit-wise (boolean) and of memory with register A and store the result in register A. MP (multiply) Multiply the contents of register A by the data at the referenced memory address and store the high-order product in register A and the low-order product in register LP. The parts of the product agree in sign. DV (divide) Divide the contents of register A by the data at the referenced memory address. Store the quotient in register A and the absolute value of the remainder in register Q. Unlike modern machines, fixed-point numbers were treated as fractions (notional decimal point just to right of the sign bit), so you could produce garbage if the divisor was not larger than the dividend; there was no protection against that situation. In the Block II AGC, a double-precision dividend started in A and L (the Block II LP), and the correctly signed remainder was delivered in L. That considerably simplified the subroutine for double precision division. SU (subtract) Subtract (one's complement) the data at the referenced memory address from the contents of register A and store the result in A.

Instructions were implemented in groups of 12 steps, called timing pulses. The timing pulses were named TP1 through TP12. Each set of 12 timing pulses was called an instruction subsequence. Simple instructions, such as TC, executed in a single subsequence of 12 pulses. More complex instructions required several subsequences. The multiply instruction (MP) used 8 subsequences: an initial one called MP0, followed by an MP1 subsequence which was repeated 6 times, and then terminated by an MP3 subsequence. This was reduced to 3 subsequences in Block II. Each timing pulse in a subsequence could trigger up to 5 control pulses. The control pulses were the signals which did the actual work of the instruction, such as reading the contents of a register onto the bus, or writing data from the bus into a register. Memory[edit]

AGC core rope memory (ROM)

Apollo AGC 102 4-bit
4-bit
erasable core memory module (front and back)

Block I AGC memory was organized into 1 kiloword banks. The lowest bank (bank 0) was erasable memory (RAM). All banks above bank 0 were fixed memory (ROM). Each AGC instruction had a 12-bit address field. The lower bits (1-10) addressed the memory inside each bank. Bits 11 and 12 selected the bank: 00 selected the erasable memory bank; 01 selected the lowest bank (bank 1) of fixed memory; 10 selected the next one (bank 2); and 11 selected the Bank register that could be used to select any bank above 2. Banks 1 and 2 were called fixed-fixed memory, because they were always available, regardless of the contents of the Bank register. Banks 3 and above were called fixed-switchable because the selected bank was determined by the bank register. The Block I AGC initially had 12 kilowords of fixed memory, but this was later increased to 24 kilowords. Block II had 32 kilowords of fixed memory and 4 kilowords of erasable memory. The AGC transferred data to and from memory through the G register in a process called the memory cycle. The memory cycle took 12 timing pulses (11.72 μs). The cycle began at timing pulse 1 (TP1) when the AGC loaded the memory address to be fetched into the S register. The memory hardware retrieved the data word from memory at the address specified by the S register. Words from erasable memory were deposited into the G register by timing pulse 6 (TP6); words from fixed memory were available by timing pulse 7. The retrieved memory word was then available in the G register for AGC access during timing pulses 7 through 10. After timing pulse 10, the data in the G register was written back to memory. The AGC memory cycle occurred continuously during AGC operation. Instructions needing memory data had to access it during timing pulses 7-10. If the AGC changed the memory word in the G register, the changed word was written back to memory after timing pulse 10. In this way, data words cycled continuously from memory to the G register and then back again to memory. The lower 15 bits of each memory word held AGC instructions or data, with each word being protected by a 16th odd parity bit. This bit was set to 1 or 0 by a parity generator circuit so a count of the 1s in each memory word would always produce an odd number. A parity checking circuit tested the parity bit during each memory cycle; if the bit didn't match the expected value, the memory word was assumed to be corrupted and a parity alarm panel light was illuminated. Interrupts and involuntary counters[edit] The AGC had five vectored interrupts:

Dsrupt was triggered at regular intervals to update the user display (DSKY). Erupt was generated by various hardware failures or alarms. Keyrupt signaled a key press from the user's keyboard. T3Rrupt was generated at regular intervals from a hardware timer to update the AGC's real-time clock. Uprupt was generated each time a 16-bit word of uplink data was loaded into the AGC.

The AGC responded to each interrupt by temporarily suspending the current program, executing a short interrupt service routine, and then resuming the interrupted program. The AGC also had 20 involuntary counters. These were memory locations which functioned as up/down counters, or shift registers. The counters would increment, decrement, or shift in response to internal inputs. The increment (Pinc), decrement (Minc), or shift (Shinc) was handled by one subsequence of microinstructions inserted between any two regular instructions. Interrupts could be triggered when the counters overflowed. The T3rupt and Dsrupt interrupts were produced when their counters, driven by a 100 Hz hardware clock, overflowed after executing many Pinc subsequences. The Uprupt interrupt was triggered after its counter, executing the Shinc subsequence, had shifted 16 bits of uplink data into the AGC. Standby mode[edit] The AGC had a power-saving mode controlled by a standby allowed switch. This mode turned off the AGC power, except for the 2.048 MHz clock and the scaler. The F17 signal from the scaler turned the AGC power and the AGC back on at 1.28 second intervals. In this mode, the AGC performed essential functions, checked the standby allowed switch, and, if still enabled, turned off the power and went back to sleep until the next F17 signal. In the standby mode, the AGC slept most of the time; therefore it was not awake to perform the Pinc instruction needed to update the AGC's real time clock at 10 ms intervals. To compensate, one of the functions performed by the AGC each time it awoke in the standby mode was to update the real time clock by 1.28 seconds. The standby mode was designed to reduce power by 5 to 10 W (from 70 W) during midcourse flight when the AGC was not needed. However, in practice, the AGC was left on during all phases of the mission and this feature was never used. Data buses[edit] The AGC had a 16-bit read bus and a 16-bit write bus. Data from central registers (A, Q, Z, or LP), or other internal registers could be gated onto the read bus with a control signal. The read bus connected to the write bus through a non-inverting buffer, so any data appearing on the read bus also appeared on the write bus. Other control signals could copy write bus data back into the registers. Data transfers worked like this: To move the address of the next instruction from the B register to the S register, an RB (read B) control signal was issued; this caused the address to move from register B to the read bus, and then to the write bus. A WS (write S) control signal moved the address from the write bus into the S register. Several registers could be read onto the read bus simultaneously. When this occurred, data from each register was inclusive-ORed onto the bus. This inclusive-OR feature was used to implement the Mask instruction, which was a logical AND operation. Because the AGC had no native ability to do a logical AND, but could do a logical OR through the bus and could complement (invert) data through the C register, De Morgan's theorem was used to implement the equivalent of a logical AND. This was accomplished by inverting both operands, performing a logical OR through the bus, and then inverting the result. Software[edit] AGC software was written in AGC assembly language and stored on rope memory. The bulk of the software was on read-only rope memory and thus couldn't be changed in operation, but some key parts of the software were stored in standard read-write magnetic-core memory and could be overwritten by the astronauts using the DSKY interface, as was done on Apollo 14. The design principles developed for the AGC by MIT Instrumentation Laboratory, directed in late 1960s by Charles Draper, became foundational to software engineering—particularly for the design of more reliable systems that relied on asynchronous software, priority scheduling, testing, and human-in-the-loop decision capability.[10] When the design requirements for the AGC were defined, necessary software and programming techniques did not exist so it had to be designed from scratch. There was a simple real-time operating system designed by J. Halcombe Laning,[11] consisting of the Exec, a batch job-scheduling using cooperative multi-tasking and an interrupt-driven pre-emptive scheduler called the Waitlist which could schedule multiple timer-driven 'tasks'. The tasks were short threads of execution which could reschedule themselves for re-execution on the Waitlist, or could kick off a longer operation by starting a 'job' with the Exec. The AGC also had a sophisticated software interpreter, developed by the MIT Instrumentation Laboratory, that implemented a virtual machine with more complex and capable pseudo-instructions than the native AGC. These instructions simplified the navigational programs. Interpreted code, which featured double precision trigonometric, scalar and vector arithmetic (16 and 24-bit), even an MXV (matrix × vector) instruction, could be mixed with native AGC code. While the execution time of the pseudo-instructions was increased (due to the need to interpret these instructions at runtime) the interpreter provided many more instructions than AGC natively supported and the memory requirements were much lower than in the case of adding these instructions to the AGC native language which would require additional memory built into the computer (at that time the memory capacity was very expensive). The average pseudo-instruction required about 24 ms to execute. The assembler and version control system, named YUL for an early prototype Christmas Computer,[12] enforced proper transitions between native and interpreted code. A set of interrupt-driven user interface routines called Pinball provided keyboard and display services for the jobs and tasks running on the AGC. A rich set of user-accessible routines were provided to let the operator (astronaut) display the contents of various memory locations in octal or decimal in groups of 1, 2, or 3 registers at a time. Monitor routines were provided so the operator could initiate a task to periodically redisplay the contents of certain memory locations. Jobs could be initiated. The Pinball routines performed the (very rough) equivalent of the UNIX shell. Many of the trajectory and guidance algorithms used were based on earlier work by Richard Battin.[11] The first command module flight was controlled by a software package called CORONA whose development was led by Alex Kosmala. Software for lunar missions consisted of COLOSSUS for the command module, whose development was led by Frederic Martin, and LUMINARY on the lunar module led by George Cherry. Details of these programs were implemented by a team under the direction of Margaret Hamilton. In total, software development on the project comprised 1400 person-years of effort, with a peak workforce of 350 people.[11] In 2016, Hamilton received the Presidential Medal of Freedom for her role in creating the flight software. The Apollo Guidance Computer
Apollo Guidance Computer
software influenced the design of Skylab, Space Shuttle
Space Shuttle
and early fly-by-wire fighter aircraft systems.[13][14] The AGC code was uploaded to the internet in 2003, and the software itself was uploaded by a former NASA
NASA
intern to GitHub
GitHub
on July 7, 2016.[15][16][17] Block II[edit] A Block II version of the AGC was designed in 1966. It retained the basic Block I architecture, but increased erasable memory from 1 to 2 kilowords. Fixed memory was expanded from 24 to 36 kilowords. Instructions were expanded from 11 to 34 and I/O channels were implemented to replace the I/O registers on Block I. The Block II version is the one that actually flew to the moon. Block I was used during the unmanned Apollo 4
Apollo 4
and 6 flights, and was on board the ill-fated Apollo 1. The decision to expand the memory and instruction set for Block II, but to retain the Block I's restrictive three-bit op. code and 12-bit address had interesting design consequences. Various tricks were employed to squeeze in additional instructions, such as having special memory addresses which, when referenced, would implement a certain function. For instance, an INDEX to address 25 triggered the RESUME instruction to return from an interrupt. Likewise, INDEX 17 performed an INHINT instruction (inhibit interrupts), while INDEX 16 reenabled them (RELINT). Other instructions were implemented by preceding them with a special version of TC called EXTEND. The address spaces were extended by employing the Bank (fixed) and Ebank (erasable) registers, so the only memory of either type that could be addressed at any given time was the current bank, plus the small amount of fixed-fixed memory and the erasable memory. In addition, the bank register could address a maximum of 32 kilowords, so an Sbank (super-bank) register was required to access the last 4 kilowords. All across-bank subroutine calls had to be initiated from fixed-fixed memory through special functions to restore the original bank during the return: essentially a system of far pointers. The Block II AGC also has the mysterious and poorly documented EDRUPT instruction (the name may be a contraction of Ed's Interrupt, after Ed Smally, the programmer who requested it) which is used a total of once in the Apollo software: in the Digital Autopilot of the Lunar Module. At this time, while the general operation of the instruction is understood, the precise details are still hazy, and it is believed to be responsible for problems emulating the LEM AGC Luminary software.[citation needed] PGNCS trouble[edit] PGNCS generated unanticipated warnings during Apollo 11's lunar descent, with the AGC showing a 1201 alarm ("Executive overflow - no vacant areas[18][citation needed]") and a 1202 alarm ("Executive overflow - no core sets").[19] The cause was a rapid, steady stream of spurious cycle steals from the rendezvous radar (tracking the orbiting Command Module), intentionally left on standby during the descent in case it was needed for an abort.[20][21] During this part of the approach, the processor would normally be almost 85% loaded. The extra 6,400 cycle steals per second added the equivalent of 13% load, leaving just enough time for all scheduled tasks to run to completion. Five minutes into the descent, Buzz Aldrin gave the computer the command 1668 which instructed it to calculate and display DELTAH (the difference between altitude sensed by the radar and the computed altitude). This added an additional 10% to the processor workload, causing executive overflow and a 1202 alarm. After being given the "GO" from Houston, Aldrin entered 1668 again and another 1202 alarm occurred. When reporting the second alarm, Aldrin added the comment "It appears to come up when we have a 1668 up". The AGC software had been designed with priority scheduling, and automatically recovered, deleting lower priority tasks including the 1668 display task, to complete its critical guidance and control tasks. Guidance controller Steve Bales and his support team that included Jack Garman
Jack Garman
issued several "GO" calls and the landing was successful. For his role, Bales received the US Presidential Medal of Freedom on behalf of the entire control center team and the three Apollo astronauts.[22] The problem was not a programming error in the AGC, nor was it pilot error. It was a peripheral hardware design bug that had already been known and documented by Apollo 5 engineers.[23] However, because the problem had only occurred once during testing, they concluded that it was safer to fly with the existing hardware that they had already tested, than to fly with a newer but largely untested radar system. In the actual hardware, the position of the rendezvous radar was encoded with synchros excited by a different source of 800 Hz AC than the one used by the computer as a timing reference. The two 800 Hz sources were frequency locked but not phase locked, and the small random phase variations made it appear as though the antenna was rapidly "dithering" in position, even though it was completely stationary. These phantom movements generated the rapid series of cycle steals. J. Halcombe Laning's software and computer design saved the Apollo 11 landing mission. Had it not been for Laning's design, the landing would have been aborted for lack of a stable guidance computer.[24] Applications outside Apollo[edit]

Fly By Wire testbed aircraft. The AGC DSKY is visible in the avionics bay

The AGC formed the basis of an experimental fly-by-wire (FBW) system installed into an F-8 Crusader
F-8 Crusader
to demonstrate the practicality of computer driven FBW. The AGC used in the first phase of the program was replaced with another machine in the second phase, and research done on the program led to the development of fly-by-wire systems for the Space Shuttle. The AGC also led, albeit indirectly, to the development of fly-by-wire systems for the generation of fighters that were being developed at the time.[25] The AGC was also used for the United States Navy's Deep Submergence Rescue Vehicle.[26] See also[edit]

Apollo PGNCS
Apollo PGNCS
- the Apollo Primary Guidance and Navigation System AP-101
AP-101
(IBM S/360-derived) computers used in the Space Shuttle History of computer hardware

Notes[edit]

^ The first advanced desktop calculators hit the market in roughly the same time frame, with scientific and then programmable pocket calculators appearing during the following decade. The first programmable handheld calculator, the HP-65, was tried on backup computations aboard the Apollo Command/Service Module
Apollo Command/Service Module
in the Apollo–Soyuz Test Project
Apollo–Soyuz Test Project
in 1975.

References[edit]

^ a b c Hall, Eldon C. (1996), Journey to the Moon: The History of the Apollo Guidance Computer, Reston, Virginia, USA: AIAA, p. 196, ISBN 1-56347-185-X  ^ https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/20090016290_2009014409.pdf Apollo Guidance, Navigation and Control Hardware Overview ^ https://history.nasa.gov/computers/Ch2-5.html ^ "How did the Apollo flight computers get men to the moon and back ?".  ^ "Ramon Alonso's introduction", AGC History Project (Caltech archive, original site closed), MIT, July 27, 2001, retrieved 2009-08-30  ^ "Ramon Alonso's interview (Spanish)", Ramón Alonso, el argentino que llevó a la Apollo 11 a la Luna, Diario La Nacion, March 7, 2010  ^ "Hugh Blair-Smith biography", AGC History Project (Caltech archive, original site closed), MIT, January 2002, retrieved 2009-08-30  ^ "Herb Thaler introduction", AGC History Project (Caltech archive, original site closed), MIT, 14 September 2001, retrieved 2009-08-30  ^ "Lot 41178 – Apollo Guidance Computer: Original Display and Keyboard (DSKY) Unit". October 8, 2009.  ^ NASA
NASA
Press Release " NASA
NASA
Honors Apollo Engineer" (September 03, 2003) ^ a b c Hoag, David (September 1976). "The History of Apollo On-board Guidance, Navigation, and Control" (PDF). Charles Stark Draper Laboratory.  ^ "Hugh Blair-Smith's Introduction", AGC History Project (Caltech archive, original site closed), MIT, 30 November 2001, retrieved 2010-03-21  ^ NASA
NASA
Office of Logic Design "About Margaret Hamilton" (Last Revised: February 03, 2010) ^ By A.J.S. Rayl " NASA
NASA
Engineers and Scientists-Transforming Dreams Into Reality" ^ Collins, Keith. "The code that took America to the moon was just published to GitHub, and it's like a 1960s time capsule". Quartz. Retrieved 19 August 2016.  ^ Garry, Chris. "Original Apollo 11 Guidance Computer (AGC) source code for the command and lunar modules". GitHub. Retrieved 19 August 2016.  ^ "Earlier (7 April 2015), more complete upload on Github, maintained by iBiblio". Retrieved 24 November 2017.  ^ "chrislgarry/Apollo-11". GitHub. Retrieved 2016-07-17.  ^ Collins, Michael; Aldrin, Edwin (1975), Cortright, Edgar M., ed., "A Yellow Caution Light", NASA
NASA
SP-350, Apollo Expeditions to the Moon, Washington, DC: NASA, pp. Chapter 11.4, ISBN 978-0486471754, retrieved 2009-08-30  ^ Adler, Peter (1998), Jones, Eric M., ed., "Apollo 11 Program Alarms", Apollo 11 Lunar Surface Journal, NASA, retrieved 2009-09-01  ^ Martin, Fred H. (July 1994), Jones, Eric M., ed., "Apollo 11 : 25 Years Later", Apollo 11 Lunar Surface Journal, NASA, retrieved 2009-09-01  ^ Cortright, Edgar M., ed. (1975), "The Lunar Module
Lunar Module
Computer", Apollo 11 Lunar Surface Journal, NASA, retrieved 2010-02-04  ^ Eyles, Don (February 6, 2004), "Tales From The Lunar Module
Lunar Module
Guidance Computer", 27th annual Guidance and Control Conference, Breckenridge, Colorado: American Astronautical Society  ^ Tales From The Lunar Module
Lunar Module
Guidance Computer ^ Tomayko, James E. (2000), " NASA
NASA
SP-2000-4224 — Computers Take Flight: A History of NASA's Pioneering Digital Fly-By-Wire Project" (PDF), The NASA
NASA
History Series, Washington, D.C.: NASA, retrieved 2009-09-01  ^ Craven, John Pina (2002). The Silent War: The Cold War Battle Beneath the Sea. New York: Simon and Schuster. p. 120. ISBN 0-684-87213-7. 

External links[edit]

Wikimedia Commons has media related to Apollo Guidance Computer.

Documentation on the AGC and its development

AGC4 Memo #9, Block II Instructions – The infamous memo that served as de facto official documentation of the instruction set Computers in Spaceflight: The NASA
NASA
Experience – By James Tomayko (Chapter 2, Part 5, The Apollo guidance computer: Hardware) Computers Take Flight – By James Tomayko The Apollo Guidance Computer
Apollo Guidance Computer
- A Users View (PDF) – By David Scott, Apollo mission astronaut Lunar Module
Lunar Module
Attitude Controller Assembly Input Processing (PDF) – By José Portillo Lugo, History of Technology The MIT AGC Project – With comprehensive document archive

Luminary software source code listing, for Lunar Module
Lunar Module
guidance computer. (nb. 622 Mb) Colossus software source code listing, for Command Module
Command Module
guidance computer. (nb. 83 Mb)

National Air and Space Museum's AGC Block I[dead link] and Dsky[dead link] Annotations to Eldon Hall's Journey to the Moon – An AGC system programmer discusses some obscure details of the development of AGC, including specifics of Ed's Interrupt

Documentation of AGC hardware design, and particularly the use of the new integrated circuits in place of transistors

AGC Integrated Circuit Packages Integrated Circuits in the Apollo Guidance Computer

Documentation of AGC software operation

Delco Electronics, Apollo 15 - Manual for CSM and LEM AGC software used on the Apollo 15 mission, including detailed user interface procedures, explanation of many underlying algorithms and limited hardware information. Note that this document has over 500 pages and is over 150 megabytes in size. Stengel, R., Manual Attitude Control of the Lunar Module, J. Spacecraft and Rockets, Vol. 7, No. 8, August 1970, pp. 941–948. Source code for Command Module
Command Module
code (Comanche054) and Lunar Module code (Luminary099) as text. GitHub
GitHub
Complete Source Code Original Apollo 11 Guidance Computer (AGC) source code for the command and lunar modules.

Some AGC-based projects and simulators

AGC Replica – John Pultorak's successful project to build a hardware replica of the Block I AGC in his basement. Mirror site: AGC Replica. Virtual AGC Home Page – Ronald Burkey's AGC simulator, plus source and binary code recovery for the Colossus (CSM) and Luminary (LEM) SW. Moonjs – A web-based AGC simulator based on Virtual AGC. Project Apollo for Orbiter – Addon for Orbiter spaceflight simulator, working towards a full simulation of the CSM and LEM including the Virtual AGC. Eagle Lander 3D Shareware Lunar Lander Simulator with a working AGC and DSKY (Windows only).

Feature Stories

Weaving the way to the Moon (BBC News) Computer for Apollo video

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Apollo program
Apollo program
hardware

Vehicles

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Vehicle components

Apollo Abort Guidance System Apollo Docking Mechanism Apollo Guidance Computer Primary Guidance, Navigation and Control System Apollo Telescope Mount Apollo TV camera Saturn Launch Vehicle Digital Computer Descent Propulsion System Ascent Propulsion System

Lunar surface

Apollo Lunar Surface Experiments Package Apollo/ Skylab
Skylab
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Earth-based

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Guidance computers

On crewed spacecraft

Apollo Abort Guidance System Apollo Guidance Computer Gemini Guidance Computer IBM TC-1 IBM AP-101

On launch vehicles

ATHENA computer ASC-15 Universal Space Guidance System Saturn Launch Vehicle Digital Computer

Category:Guidance computers

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CPU technologies

Architecture

Turing machine Post–Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite-state machine Queue automaton Von Neumann Harvard (modified) Dataflow TTA Cellular Artificial neural network

Machine learning Deep learning Neural processing unit (NPU)

Convolutional neural network Load/store architecture Register memory architecture Endianness FIFO Zero-copy NUMA HUMA HSA Mobile computing Surface computing Wearable computing Heterogeneous computing Parallel computing Concurrent computing Distributed computing Cloud computing Amorphous computing Ubiquitous computing Fabric computing Cognitive computing Unconventional computing Hypercomputation Quantum computing Adiabatic quantum computing Linear optical quantum computing Reversible computing Reverse computation Reconfigurable computing Optical computing Ternary computer Analogous computing Mechanical computing Hybrid computing Digital computing DNA computing Peptide computing Chemical computing Organic computing Wetware computing Neuromorphic computing Symmetric multiprocessing
Symmetric multiprocessing
(SMP) Asymmetric multiprocessing
Asymmetric multiprocessing
(AMP) Cache hierarchy Memory hierarchy

ISA types

ASIP CISC RISC EDGE (TRIPS) VLIW (EPIC) MISC OISC NISC ZISC Comparison

ISAs

x86 z/Architecture ARM MIPS Power Architecture
Power Architecture
(PowerPC) SPARC Mill Itanium
Itanium
(IA-64) Alpha Prism SuperH V850 Clipper VAX Unicore PA-RISC MicroBlaze RISC-V

Word size

1-bit 2-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit Variable

Execution

Instruction pipelining

Bubble Operand forwarding

Out-of-order execution

Register renaming

Speculative execution

Branch predictor Memory dependence prediction

Hazards

Parallel level

Bit

Bit-serial Word

Instruction Pipelining

Scalar Superscalar

Task

Thread Process

Data

Vector

Memory

Multithreading

Temporal Simultaneous (SMT) (Hyper-threading) Speculative (SpMT) Preemptive Cooperative Clustered Multi-Thread (CMT) Hardware scout

Flynn's taxonomy

SISD SIMD
SIMD
(SWAR) SIMT MISD MIMD

SPMD

Addressing mode

CPU performance

Instructions per second (IPS) Instructions per clock (IPC) Cycles per instruction (CPI) Floating-point operations per second (FLOPS) Transactions per second (TPS) Synaptic Updates Per Second (SUPS) Performance per watt Orders of magnitude (computing) Cache performance measurement and metric

Core count

Single-core processor Multi-core processor Manycore processor

Types

Central processing unit
Central processing unit
(CPU) GPGPU AI accelerator Vision processing unit (VPU) Vector processor Barrel processor Stream processor Digital signal processor
Digital signal processor
(DSP) I/O processor/DMA controller Network processor Baseband processor Physics processing unit
Physics processing unit
(PPU) Coprocessor Secure cryptoprocessor ASIC FPGA FPOA CPLD Microcontroller Microprocessor Mobile processor Notebook processor Ultra-low-voltage processor Multi-core processor Manycore processor Tile processor Multi-chip module
Multi-chip module
(MCM) Chip stack multi-chip modules System on a chip
System on a chip
(SoC) Multiprocessor system-on-chip (MPSoC) Programmable System-on-Chip
System-on-Chip
(PSoC) Network on a chip (NoC)

Components

Execution unit (EU) Arithmetic logic unit
Arithmetic logic unit
(ALU) Address generation unit
Address generation unit
(AGU) Floating-point unit
Floating-point unit
(FPU) Load-store unit (LSU) Branch predictor Unified Reservation Station Barrel shifter Uncore Sum addressed decoder (SAD) Front-side bus Back-side bus Northbridge (computing) Southbridge (computing) Adder (electronics) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory management unit
Memory management unit
(MMU) Input–output memory management unit
Input–output memory management unit
(IOMMU) Integrated Memory Controller (IMC) Power Management Unit (PMU) Translation lookaside buffer
Translation lookaside buffer
(TLB) Stack engine Register file Processor register Hardware register Memory buffer register (MBR) Program counter Microcode
Microcode
ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three-dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed-signal integrated circuit Power management integrated circuit Quantum circuit Logic gate

Combinational logic Sequential logic Emitter-coupled logic
Emitter-coupled logic
(ECL) Transistor–transistor logic
Transistor–transistor logic
(TTL) Glue logic

Quantum gate Gate array Counter (digital) Bus (computing) Semiconductor device Clock rate CPU multiplier Vision chip Memristor

Power management

APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating

Hardware security

Non-executable memory (NX bit) Memory Protection Extensions (Intel MPX) Intel Secure Key Hardware restriction (firmware) Software Guard Extensions (Intel SGX) Trusted Execution Technology Trusted Platform Module
Trusted Platform Module
(TPM) Secure cryptoprocessor Hardware security module Hengzhi chip

Related

History of ge

.