Static random access memory

Static random-access memory (static RAM or SRAM) is a type of random-access memory (RAM) that uses latching circuitry (flip-flop) to store each bit. SRAM is volatile memory; data is lost when power is removed.

The term ''static'' differentiates SRAM from DRAM (''dynamic'' random-access memory) — SRAM will hold its data permanently in the presence of power, while data in DRAM decays in seconds and thus must be periodically refreshed. SRAM is faster than DRAM but it is more expensive in terms of silicon area and cost; it is typically used for the cache and internal registers of a CPU while DRAM is used for a computer's main memory.

History

Semiconductor bipolar SRAM was invented in 1963 by Robert Norman at Fairchild Semiconductor. MOS SRAM was invented in 1964 by John Schmidt at Fairchild Semiconductor. It was a 64-bit MOS p-channel SRAM.

The SRAM was the main driver behind any new CMOS-based technology fabrication process since 1959 when CMOS was invented. In 1965, Arnold Farber and Eugene Schlig, working for IBM, created a hard-wired memory cell, using a transistor gate and tunnel diode latch. They replaced the latch with two transistors and two resistors, a configuration that became known as the Farber-Schlig cell. In 1965, Benjamin Agusta and his team at IBM created a 16-bit silicon memory chip based on the Farber-Schlig cell, with 80 transistors, 64 resistors, and 4 diodes.

Characteristics

Though it can be characterized as volatile memory, SRAM exhibits data remanence.

SRAM offers a simple data access model and does not require a refresh circuit. Performance and reliability are good and power consumption is low when idle.

Since SRAM requires more transistors per bit to implement, it is less dense and more expensive than DRAM and also has a higher power consumption during read or write access. The power consumption of SRAM varies widely depending on how frequently it is accessed.

Applications and uses

Embedded use

Many categories of industrial and scientific subsystems, automotive electronics, and similar embedded systems, contain SRAM which, in this context, may be referred to as ESRAM. Some amount (kilobytes or less) is also embedded in practically all modern appliances, toys, etc. that implement an electronic user interface.

SRAM in its dual-ported form is sometimes used for real-time digital signal processing circuits.

In computers

SRAM is also used in personal computers, workstations, routers and peripheral equipment: CPU register files, internal CPU caches and external burst mode SRAM caches, hard disk buffers, router buffers, etc. LCD screens and printers also normally employ SRAM to hold the image displayed (or to be printed). SRAM was used for the main memory of most early personal computers such as the ZX80, TRS-80 Model 100, and VIC-20.

Hobbyists

Hobbyists, specifically home-built processor enthusiasts, often prefer SRAM due to the ease of interfacing. It is much easier to work with than DRAM as there are no refresh cycles and the address and data buses are often directly accessible. In addition to buses and power connections, SRAM usually requires only three controls: Chip Enable (CE), Write Enable (WE) and Output Enable (OE). In synchronous SRAM, Clock (CLK) is also included.

Types of SRAM

Non-volatile SRAM

Non-volatile SRAM (nvSRAM) has standard SRAM functionality, but they save the data when the power supply is lost, ensuring preservation of critical information. nvSRAMs are used in a wide range of situationsnetworking, aerospace, and medical, among many otherswhere the preservation of data is critical and where batteries are impractical.

Pseudostatic RAM

Pseudostatic RAM (PSRAM) is DRAM combined with a self-refresh circuit. It appears externally as slower SRAM, albeit with a density/cost advantage over true SRAM, and without the access complexity of DRAM.

By transistor type

* Bipolar junction transistor (used in TTL and ECL) very fast but with high power consumption
* MOSFET (used in CMOS) low power and very common today

By flip-flop type

* Binary SRAM
* Ternary SRAM

By function

* Asynchronous independent of clock frequency; data in and data out are controlled by address transition. Examples include the ubiquitous 28-pin 8K × 8 and 32K × 8 chips (often but not always named something along the lines of 6264 and 62C256 respectively), as well as similar products up to 16 Mbit per chip.
* Synchronous all timings are initiated by the clock edges. Address, data in and other control signals are associated with the clock signals.
In the 1990s, asynchronous SRAM used to be employed for fast access time. Asynchronous SRAM was used as main memory for small cache-less embedded processors used in everything from industrial electronics and measurement systems to hard disks and networking equipment, among many other applications. Nowadays, synchronous SRAM (e.g. DDR SRAM) is rather employed similarly to synchronous DRAM DDR SDRAM memory is rather used than asynchronous DRAM. Synchronous memory interface is much faster as access time can be significantly reduced by employing pipeline architecture. Furthermore, as DRAM is much cheaper than SRAM, SRAM is often replaced by DRAM, especially in the case when a large volume of data is required. SRAM memory is, however, much faster for random (not block / burst) access. Therefore, SRAM memory is mainly used for CPU cache, small on-chip memory, FIFOs or other small buffers.

By feature

* Zero bus turnaround (ZBT) the turnaround is the number of clock cycles it takes to change access to the SRAM from ''write'' to ''read'' and vice versa. The turnaround for ZBT SRAMs or the latency between read and write cycle is zero.
* syncBurst (syncBurst SRAM or synchronous-burst SRAM) features synchronous burst write access to the SRAM to increase write operation to the SRAM.
* DDR SRAM synchronous, single read/write port, double data rate I/O.
* Quad Data Rate SRAM synchronous, separate read and write ports, quadruple data rate I/O.

Integrated on chip

SRAM may be integrated as RAM or cache memory in micro-controllers (usually from around 32 bytes up to 128 kilobytes), as the primary caches in powerful microprocessors, such as the x86 family, and many others (from 8  KB, up to many megabytes), to store the registers and parts of the state-machines used in some microprocessors (see register file), on application-specific integrated circuits (ASICs) (usually in the order of kilobytes) and in field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs).

Design

A typical SRAM cell is made up of six MOSFETs, and is often called a SRAM cell. Each bit in the cell is stored on four transistors (M1, M2, M3, M4) that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional ''access'' transistors serve to control the access to a storage cell during read and write operations. In addition to 6T SRAM, oth