In
semiconductor manufacturing
Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuit (IC) chips such as modern computer processors, microcontrollers, and memory chips such as NAND flash and DRAM that are pres ...
, silicon on insulator (SOI) technology is fabrication of
silicon
Silicon is a chemical element with the symbol Si and atomic number 14. It is a hard, brittle crystalline solid with a blue-grey metallic luster, and is a tetravalent metalloid and semiconductor. It is a member of group 14 in the periodic ...
semiconductor devices
A semiconductor device is an electronic component that relies on the electronic properties of a semiconductor material (primarily silicon, germanium, and gallium arsenide, as well as organic semiconductors) for its function. Its conductivity l ...
in a layered silicon–insulator–silicon
substrate, to reduce
parasitic capacitance
Parasitic capacitance is an unavoidable and usually unwanted capacitance that exists between the parts of an electronic component or circuit simply because of their proximity to each other. When two electrical conductors at different voltages ...
within the device, thereby improving performance.
SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an
electrical insulator
An electrical insulator is a material in which electric current does not flow freely. The atoms of the insulator have tightly bound electrons which cannot readily move. Other materials—semiconductors and conductors—conduct electric current ...
, typically
silicon dioxide
Silicon dioxide, also known as silica, is an oxide of silicon with the chemical formula , most commonly found in nature as quartz and in various living organisms. In many parts of the world, silica is the major constituent of sand. Silica is one ...
or
sapphire
Sapphire is a precious gemstone, a variety of the mineral corundum, consisting of aluminium oxide () with trace amounts of elements such as iron, titanium, chromium, vanadium, or magnesium. The name sapphire is derived via the Latin "sa ...
(these types of devices are called
silicon on sapphire
Silicon on sapphire (SOS) is a hetero-epitaxial process for metal-oxide-semiconductor (MOS) integrated circuit (IC) manufacturing that consists of a thin layer (typically thinner than 0.6 µm) of silicon grown on a sapphire (Al2O3) wafer. ...
, or SOS). The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application.
Industry need
SOI technology is one of several manufacturing strategies to allow the continued miniaturization of
microelectronic devices, colloquially referred to as "extending
Moore's Law
Moore's law is the observation that the number of transistors in a dense integrated circuit (IC) doubles about every two years. Moore's law is an observation and projection of a historical trend. Rather than a law of physics, it is an empi ...
" (or "More Moore", abbreviated "MM"). Reported benefits of SOI relative to conventional silicon (bulk
CMOS
Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", ) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSF ...
) processing include:
*''Lower parasitic capacitance'' due to isolation from the bulk silicon, which improves power consumption at matched performance
*''Resistance to
latchup'' due to complete isolation of the n- and p-well structures
*Higher performance at equivalent
VDD. Can work at low VDD's
*Reduced temperature dependency due to no doping
*Better yield due to high density, better wafer utilization
*Reduced antenna issues
*No body or well taps are needed
*Lower leakage currents due to isolation thus higher power efficiency
*Inherently
radiation hardened
Radiation hardening is the process of making electronic components and circuits resistant to damage or malfunction caused by high levels of ionizing radiation (particle radiation and high-energy electromagnetic radiation), especially for environ ...
(resistant to soft errors), reducing the need for redundancy
From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel
metrology
Metrology is the scientific study of measurement. It establishes a common understanding of units, crucial in linking human activities. Modern metrology has its roots in the French Revolution's political motivation to standardise units in Fran ...
requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The threshold voltage of the transistor depends on the history of operation and applied voltage to it, thus making modeling harder.
The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10–15% increase to total manufacturing costs.
SOI transistors
An SOI MOSFET is a
metal-oxide-semiconductor field-effect transistor (MOSFET) device in which a
semiconductor
A semiconductor is a material which has an electrical conductivity value falling between that of a conductor, such as copper, and an insulator, such as glass. Its resistivity falls as its temperature rises; metals behave in the opposite way ...
layer such as silicon or
germanium
Germanium is a chemical element with the symbol Ge and atomic number 32. It is lustrous, hard-brittle, grayish-white and similar in appearance to silicon. It is a metalloid in the carbon group that is chemically similar to its group neighbors ...
is formed on an insulator layer which may be a buried oxide (BOX) layer formed in a semiconductor substrate. SOI MOSFET devices are adapted for use by the computer industry. The buried oxide layer can be used in
SRAM designs. There are two types of SOI devices: PDSOI (partially depleted SOI) and FDSOI (fully depleted SOI) MOSFETs. For an n-type PDSOI MOSFET the sandwiched n-type film between the gate oxide (GOX) and buried oxide (BOX) is large, so the depletion region can't cover the whole n region. So to some extent PDSOI behaves like bulk MOSFET. Obviously there are some advantages over the bulk MOSFETs. The film is very thin in FDSOI devices so that the depletion region covers the whole channel region. In FDSOI the front gate (GOX) supports fewer depletion charges than the bulk so an increase in inversion charges occurs resulting in higher switching speeds. The limitation of the depletion charge by the BOX induces a suppression of the depletion capacitance and therefore a substantial reduction of the subthreshold swing allowing FD SOI MOSFETs to work at lower gate bias resulting in lower power operation. The
subthreshold swing can reach the minimum theoretical value for MOSFET at 300K, which is 60mV/decade. This ideal value was first demonstrated using numerical simulation. Other drawbacks in bulk MOSFETs, like threshold voltage roll off, etc. are reduced in FDSOI since the source and drain electric fields can't interfere due to the BOX. The main problem in PDSOI is the "
floating body effect (FBE)" since the film is not connected to any of the supplies.
Manufacture of SOI wafers
![Smart Cut SOI Wafer Manufacturing Schema](https://upload.wikimedia.org/wikipedia/commons/5/52/Smart_Cut_SOI_Wafer_Manufacturing_Schema.svg)
SiO
2-based SOI wafers can be produced by several methods:
*''
SIMOX
Ion implantation is a low-temperature process by which ions of one element are accelerated into a solid target, thereby changing the physical, chemical, or electrical properties of the target. Ion implantation is used in semiconductor device fa ...
'' - Separation by IMplantation of OXygen – uses an oxygen
ion beam implantation process followed by high temperature annealing to create a buried SiO
2 layer.
*
Wafer bonding
Wafer bonding is a packaging technology on wafer-level for the fabrication of microelectromechanical systems (MEMS), nanoelectromechanical systems (NEMS), microelectronics and optoelectronics, ensuring a mechanically stable and hermetically seal ...
– the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.
**One prominent example of a wafer bonding process is the ''
Smart Cut'' method developed by the French firm
Soitec
Soitec is an international company, based in France, that manufactures high performance substrates used in the manufacture of semiconductors.
Soitec's semiconductor materials are used to manufacture chips which equip smartphones, tablets, ...
which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer.
**''NanoCleave'' is a technology developed by Silicon Genesis Corporation that separates the silicon via stress at the interface of silicon and
silicon-germanium alloy.
**''ELTRAN'' is a technology developed by Canon which is based on porous silicon and water cut.
*Seed methods - wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.
An exhaustive review of these various manufacturing processes may be found in reference
Microelectronics industry
Research
The silicon-on-insulator concept dates back to 1964, when it was proposed by C.W. Miller and P.H. Robinson. In 1979, a
Texas Instruments
Texas Instruments Incorporated (TI) is an American technology company headquartered in Dallas, Texas, that designs and manufactures semiconductors and various integrated circuits, which it sells to electronics designers and manufacturers globa ...
research team including Al F. Tasch, T.C. Holloway, Kai Fong Lee and
James F. Gibbons fabricated a silicon-on-insulator
MOSFET
The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which d ...
(metal-oxide-semiconductor field-effect transistor). In 1983, a
Fujitsu
is a Japanese multinational information and communications technology equipment and services corporation, established in 1935 and headquartered in Tokyo. Fujitsu is the world's sixth-largest IT services provider by annual revenue, and the la ...
research team led by S. Kawamura fabricated a
three-dimensional integrated circuit
A three-dimensional integrated circuit (3D IC) is a MOS (metal-oxide semiconductor) integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or ...
with SOI
CMOS
Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", ) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSF ...
(complementary metal-oxide-semiconductor) structure. In 1984, the same Fujitsu research team fabricated a 3D
gate array
A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICs) using a prefabricated chip with components that are later interconnected into logic devices (e.g. NAND gates, flip-flops, etc.) according ...
with vertically stacked dual SOI/CMOS structure using beam recrystallization. The same year,
Electrotechnical Laboratory researchers Toshihiro Sekigawa and Yutaka Hayashi fabricated a
double-gate MOSFET, demonstrating that
short-channel effect In electronics, short-channel effects occur in MOSFETs in which the channel length is comparable to the depletion layer widths of the source and drain junctions. These effects include, in particular, drain-induced barrier lowering, velocity saturat ...
s can be significantly reduced by sandwiching a fully depleted SOI device between two gate electrodes connected together.
In 1986, Jean-Pierre Colinge at
HP Labs
HP Labs is the exploratory and advanced research group for HP Inc. HP Labs' headquarters is in Palo Alto, California and the group has research and development facilities in Bristol, UK. The development of programmable desktop calculators, in ...
fabricated SOI
NMOS devices using
90 nm
The 90 nm process refers to the level of MOSFET (CMOS) fabrication process technology that was commercialized by the 2003–2005 timeframe, by leading semiconductor companies like Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpid ...
thin
silicon
Silicon is a chemical element with the symbol Si and atomic number 14. It is a hard, brittle crystalline solid with a blue-grey metallic luster, and is a tetravalent metalloid and semiconductor. It is a member of group 14 in the periodic ...
films.
In 1989,
Ghavam G. Shahidi
Ghavam G. Shahidi (born 1959) is an Iranian-American electrical engineer and IBM Fellow. He is the director of Silicon Technology at the IBM Thomas J Watson Research Center. He is best known for his pioneering work in silicon-on-insulator (SOI) ...
initiated the SOI Research Program at the
IBM Thomas J Watson Research Center.
He was the chief architect of SOI technology at
IBM Microelectronics, where he made fundamental contributions, from materials research to the development of the first commercially viable devices, with the support of his boss
Bijan Davari.
Shahidi was a key figure in making SOI CMOS technology a manufacturable reality. In the early 1990s, he demonstrated a novel technique of combining silicon
epitaxial
Epitaxy refers to a type of crystal growth or material deposition in which new crystalline layers are formed with one or more well-defined orientations with respect to the crystalline seed layer. The deposited crystalline film is called an epit ...
overgrowth and chemical mechanical polishing to prepare device-quality SOI material for fabricating devices and simple circuits, which led to
IBM expanding its research program to include SOI substrates. He was also the first to demonstrate the power-delay advantage of SOI CMOS technology over traditional bulk CMOS in
microprocessor
A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circu ...
applications. He overcame barriers preventing the
semiconductor industry
The semiconductor industry is the aggregate of companies engaged in the design and fabrication of semiconductors and semiconductor devices, such as transistors and integrated circuits. It formed around 1960, once the fabrication of semiconduct ...
's adoption of SOI, and was instrumental in driving SOI substrate development to the quality and cost levels suitable for mass-production.
In 1994, an IBM research team led by Shahidi,
Bijan Davari and
Robert H. Dennard
Robert Heath Dennard (born September 5, 1932) is an American electrical engineer and inventor.
Biography
Dennard was born in Terrell, Texas, U.S. He received his B.S. and M.S. degrees in Electrical Engineering from Southern Methodist University, ...
fabricated the first
sub-100 nanometer SOI CMOS devices. In 1998, a team of
Hitachi
() is a Japanese multinational corporation, multinational Conglomerate (company), conglomerate corporation headquartered in Chiyoda, Tokyo, Japan. It is the parent company of the Hitachi Group (''Hitachi Gurūpu'') and had formed part of the Ni ...
,
TSMC
Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational corporation, multinational semiconductor contract manufacturing and design company. It is the world's most valuable semicon ...
and
UC Berkeley
The University of California, Berkeley (UC Berkeley, Berkeley, Cal, or California) is a public university, public land-grant university, land-grant research university in Berkeley, California. Established in 1868 as the University of Californi ...
researchers demonstrated the
FinFET
A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, f ...
(fin
field-effect transistor
The field-effect transistor (FET) is a type of transistor that uses an electric field to control the flow of current in a semiconductor. FETs (JFETs or MOSFETs) are devices with three terminals: ''source'', ''gate'', and ''drain''. FETs contro ...
),
which is a non-planar, double-gate MOSFET built on an SOI substrate. In early 2001, Shahidi used SOI to developed a low-power
RF CMOS
RF CMOS is a metal–oxide–semiconductor (MOS) integrated circuit (IC) technology that integrates radio-frequency (RF), analog and digital electronics on a mixed-signal CMOS (complementary MOS) RF circuit chip. It is widely used in modern wire ...
device, resulting in increased radio frequency, at IBM.
Commercialization
Shahidi's research at IBM led to the first commercial use of SOI in mainstream CMOS technology.
SOI was first commercialized in 1995, when Shahidi's work on SOI convinced John Kelly, who ran IBM's server division, to adopt SOI in the
AS/400
The IBM AS/400 (Application System/400) is a family of midrange computers from IBM announced in June 1988 and released in August 1988. It was the successor to the System/36 and System/38 platforms, and ran the OS/400 operating system. Lower-cos ...
line of server products, which used
220 nm CMOS with copper metallization SOI devices.
IBM began to use SOI in the high-end
RS64-IV "Istar" PowerPC-AS
microprocessor
A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circu ...
in 2000. Other examples of microprocessors built on SOI technology include
AMD
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactur ...
's 130 nm, 90 nm, 65 nm, 45 nm and 32 nm single, dual, quad, six and eight core processors since 2001.
In late 2001, IBM was set to introduce
130 nanometer
The 130 nanometer (130 nm) process refers to the level of semiconductor process technology that was reached in the 2000–2001 timeframe, by most leading semiconductor companies, like Intel, Texas Instruments, IBM, and TSMC.
The origin of the 1 ...
CMOS SOI devices with copper and
low-κ dielectric In semiconductor manufacturing, a low-κ is a material with a small relative dielectric constant (κ, kappa) relative to silicon dioxide. Low-κ dielectric material implementation is one of several strategies used to allow continued scaling of micr ...
for the back end, based on Shahidi's work.
Freescale
Freescale Semiconductor, Inc. was an American semiconductor manufacturer. It was created by the divestiture of the Semiconductor Products Sector of Motorola in 2004. Freescale focused their integrated circuit products on the automotive, embed ...
adopted SOI in their
PowerPC
PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple Inc., App ...
7455 CPU in late 2001. Currently, Freescale is shipping SOI products in
180 nm
The 180 nm process refers to the level of MOSFET ( CMOS) semiconductor process technology that was commercialized around the 1998–2000 timeframe by leading semiconductor companies, starting with TSMC and Fujitsu, then followed by Sony, T ...
,
130 nm,
90 nm
The 90 nm process refers to the level of MOSFET (CMOS) fabrication process technology that was commercialized by the 2003–2005 timeframe, by leading semiconductor companies like Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpid ...
and
45 nm lines. The 90 nm
PowerPC
PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple Inc., App ...
- and
Power ISA
Power ISA is a reduced instruction set computer (RISC) instruction set architecture (ISA) currently developed by the OpenPOWER Foundation, led by IBM. It was originally developed by IBM and the now-defunct Power.org industry group. Power IS ...
-based processors used in the
Xbox 360
The Xbox 360 is a home video game console developed by Microsoft. As the successor to the original Xbox, it is the second console in the Xbox series. It competed with Sony's PlayStation 3 and Nintendo's Wii as part of the seventh generation ...
,
PlayStation 3
The PlayStation 3 (PS3) is a home video game console developed by Sony Interactive Entertainment, Sony Computer Entertainment. The successor to the PlayStation 2, it is part of the PlayStation brand of consoles. It was first released on Novemb ...
, and
Wii
The Wii ( ) is a home video game console developed and marketed by Nintendo. It was released on November 19, 2006, in North America and in December 2006 for most other Regional lockout, regions of the world. It is Nintendo's fifth major ho ...
use SOI technology as well. Competitive offerings from
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...
however continue to use conventional bulk
CMOS
Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", ) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSF ...
technology for each process node, instead focusing on other venues such as
HKMG and
tri-gate transistor
The 22 nm node is the process step following 32 nm process, 32 nm in CMOS MOSFET semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is arou ...
s to improve transistor performance. In January 2005, Intel researchers reported on an experimental single-chip silicon rib waveguide Raman laser built using SOI.
As for the traditional foundries, in July 2006
TSMC
Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational corporation, multinational semiconductor contract manufacturing and design company. It is the world's most valuable semicon ...
claimed no customer wanted SOI, but
Chartered Semiconductor
Chartered Semiconductor was created in 1987, as a venture that included Singapore Technologies Engineering Ltd. Yet, it was not until 2000, that ST Engineering (Singapore Technologies Semiconductors), a wholly owned subsidiary of Temasek Holding ...
devoted a whole fab to SOI.
Use in high-performance radio frequency (RF) applications
In 1990,
Peregrine Semiconductor
Peregrine Semiconductor, known as pSemi, is a San Diego-based manufacturer of high-performance RF (radio frequency) CMOS integrated circuits. A Murata Manufacturing company since December 2014, the company's products are used in aerospace and defe ...
began development of an SOI process technology utilizing a standard 0.5 μm CMOS node and an enhanced sapphire substrate. Its patented
silicon on sapphire
Silicon on sapphire (SOS) is a hetero-epitaxial process for metal-oxide-semiconductor (MOS) integrated circuit (IC) manufacturing that consists of a thin layer (typically thinner than 0.6 µm) of silicon grown on a sapphire (Al2O3) wafer. ...
(SOS) process is widely used in high-performance RF applications. The intrinsic benefits of the insulating sapphire substrate allow for high isolation, high linearity and electro-static discharge (ESD) tolerance. Multiple other companies have also applied SOI technology to successful RF applications in smartphones and cellular radios.
Use in photonics
SOI wafers are widely used in
silicon photonics
Silicon photonics is the study and application of photonic systems which use silicon as an optical medium. The silicon is usually patterned with sub-micrometre precision, into microphotonic components. These operate in the infrared, most comm ...
. The crystalline silicon layer on insulator can be used to fabricate optical waveguides and other optical devices, either passive or active (e.g. through suitable implantations). The buried insulator enables propagation of infrared light in the silicon layer on the basis of total internal reflection. The top surface of the waveguides can be either left uncovered and exposed to air (e.g. for sensing applications), or covered with a cladding, typically made of silica.
Disadvantages
The major disadvantage of SOI technology when compared to conventional semiconductor industry is increased cost of manufacturing.
As of 2012 only IBM and AMD used SOI as basis for high-performance processors and the other manufacturers (Intel, TSMC, Global Foundries etc.) used conventional silicon wafers to build their
CMOS
Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", ) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSF ...
chips.
SOI market
As of 2020 the market utilizing the SOI process was projected to grow up by ~15% for the next 5 years according to Market Research Future group.
See also
*
Intel TeraHertz Intel TeraHertz was Intel's new design for transistors. It uses new materials such as zirconium dioxide which is a superior insulator reducing current leakages. Using zirconium dioxide instead of silicon dioxide, this transistor can reduce the curre ...
- similar technology from Intel
*
Strain engineering
*
Wafer (electronics)
In electronics, a wafer (also called a slice or substrate) is a thin slice of semiconductor, such as a crystalline silicon
Crystalline silicon or (c-Si) Is the crystalline forms of silicon, either polycrystalline silicon (poly-Si, consisting o ...
*
Wafer bonding
Wafer bonding is a packaging technology on wafer-level for the fabrication of microelectromechanical systems (MEMS), nanoelectromechanical systems (NEMS), microelectronics and optoelectronics, ensuring a mechanically stable and hermetically seal ...
References
{{Reflist, 30em
External links
SOI Industry Consortium- a site with extensive information and education for SOI technology
SOI IP portal- A search engine for SOI IP
- a site with extensive information regarding SOI technology
Advanced Substrate News- a newsletter about the SOI industry, produced by Soitec
MIGAS '04- The 7th session of MIGAS International Summer School on Advanced Microelectronics, devoted to SOI technology and devices
MIGAS '09- 12th session of the International Summer School on Advanced Microelectronics: "Silicon on Insulator (SOI) Nanodevices"
Semiconductor structures
Semiconductor technology
Microtechnology
MOSFETs
Nanoelectronics
Semiconductor device fabrication
Silicon