Zen is the codename for the first iteration in a family of computer processor
microarchitecture
In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular processor. A given ISA may be impl ...
s of the same name from
AMD
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactur ...
. It was first used with their
Ryzen
Ryzen ( ) is a brand of multi-core x86-64 microprocessors designed and marketed by AMD for desktop, mobile, server, and embedded platforms based on the Zen microarchitecture. It consists of central processing units (CPUs) marketed for mainst ...
series of CPUs in February 2017.
The first Zen-based preview system was demonstrated at
E3 2016
The Electronic Entertainment Expo 2016 (E3 2016) was the 22nd E3, during which several hardware manufacturers and software developers and publishers from the video game industry presented new and upcoming products to the attendees, primarily re ...
, and first substantially detailed at an event hosted a block away from the
Intel Developer Forum
The Intel Developer Forum (IDF) was a biannual gathering of technologists to discuss Intel products and products based on Intel products. The first IDF was held in 1997.
To emphasize the importance of China, the Spring 2007 IDF was held in Beiji ...
2016. The first Zen-based CPUs, codenamed "Summit Ridge", reached the market in early March 2017, Zen-derived
Epyc
Epyc is a brand of multi-core x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets. Epyc processors share t ...
server processors launched in June 2017 and Zen-based
APUs
Apus is a small constellation in the Southern Celestial Hemisphere, southern sky. It represents a bird-of-paradise, and its name means "without feet" in Greek language, Greek because the bird-of-paradise was once wrongly believed to lack feet. ...
arrived in November 2017.
Zen is a clean sheet design that differs from AMD's previous long-standing
Bulldozer architecture. Zen-based processors use a
14 nm FinFET
A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, f ...
process, are reportedly more energy efficient, and can execute significantly more
instructions per cycle
In computer architecture, instructions per cycle (IPC), commonly called instructions per clock is one aspect of a processor's performance: the average number of instructions executed for each clock cycle. It is the multiplicative inverse of cycl ...
.
SMT has been introduced, allowing each core to run two threads. The cache system has also been redesigned, making the L1 cache
write-back
In computing, a cache ( ) is a hardware or software component that stores data so that future requests for that data can be served faster; the data stored in a cache might be the result of an earlier computation or a copy of data stored elsewher ...
. Zen processors use three different sockets: desktop and mobile Ryzen chips use the
AM4 socket, bringing
DDR4
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth ("double data rate") interface.
Released to the market in 2014, it is a variant of dynamic rando ...
support; the high-end desktop Zen-based Threadripper chips support quad-channel DDR4 RAM and offer 64 PCIe 3.0 lanes (vs 24 lanes), using the
TR4 socket; and Epyc server processors offer 128 PCI 3.0 lanes and octa-channel DDR4 using the
SP3 socket.
Zen is based on a
SoC design. The memory, PCIe, SATA, and USB controllers are incorporated into the same
chip(s) as the processor cores. This has advantages in bandwidth and power, at the expense of chip complexity and die area. This SoC design allows the Zen microarchitecture to scale from laptops and small-form factor mini PCs to high-end desktops and servers.
By 2020, 260 million Zen cores have already been shipped by AMD.
Design
![AMD EPYC die](https://upload.wikimedia.org/wikipedia/commons/7/7f/AMD_EPYC_die.jpg)
According to
AMD
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactur ...
, the main focus of Zen is on increasing per-core performance.
New or improved features include:
* The L1 cache has been changed from
write-through
In computing, a cache ( ) is a hardware or software component that stores data so that future requests for that data can be served faster; the data stored in a cache might be the result of an earlier computation or a copy of data stored elsewher ...
to write-back, allowing for lower latency and higher bandwidth.
*
SMT (simultaneous multithreading) architecture allows for two threads per core, a departure from the CMT (clustered multi-thread) design used in the previous
Bulldozer architecture. This is a feature previously offered in some
IBM,
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...
and
Oracle
An oracle is a person or agency considered to provide wise and insightful counsel or prophetic predictions, most notably including precognition of the future, inspired by deities. As such, it is a form of divination.
Description
The word '' ...
processors.
* A fundamental building block for all Zen-based CPUs is the ''Core Complex'' (CCX) consisting of four cores and their associated caches. Processors with more than four cores consist of multiple CCXs connected by
Infinity Fabric
HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low- latency point-to-point link that was introduced on April 2 ...
. Processors with non-multiple-of-four core counts have some cores disabled.
* Four
ALUs, two
AGUs/
load–store units, and two
floating-point unit
In computing, floating-point arithmetic (FP) is arithmetic that represents real numbers approximately, using an integer with a fixed precision, called the significand, scaled by an integer exponent of a fixed base. For example, 12.345 can b ...
s per core.
* Newly introduced "large"
micro-operation cache
A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which ...
.
* Each SMT core can dispatch up to six micro-ops per cycle (a combination of 6
integer
An integer is the number zero (), a positive natural number (, , , etc.) or a negative integer with a minus sign (−1, −2, −3, etc.). The negative numbers are the additive inverses of the corresponding positive numbers. In the language ...
micro-ops and 4
floating point
In computing, floating-point arithmetic (FP) is arithmetic that represents real numbers approximately, using an integer with a fixed precision, called the significand, scaled by an integer exponent of a fixed base. For example, 12.345 can be ...
micro-ops per cycle).
* Close to 2× faster L1 and L2 bandwidth, with total L3 cache bandwidth up 5×.
*
Clock gating
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation, by removing the clock signal when the circuit is not in use or ignores clock signal. Clock gating saves power by pruning the clock tree, ...
.
* Larger retire, load, and store queues.
* Improved
branch prediction
In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g., an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow ...
using a hashed
perceptron
In machine learning, the perceptron (or McCulloch-Pitts neuron) is an algorithm for supervised learning of binary classifiers. A binary classifier is a function which can decide whether or not an input, represented by a vector of numbers, belon ...
system with Indirect Target Array similar to the Bobcat microarchitecture, something that has been compared to a
neural network
A neural network is a network or circuit of biological neurons, or, in a modern sense, an artificial neural network, composed of artificial neurons or nodes. Thus, a neural network is either a biological neural network, made up of biological ...
by AMD engineer Mike Clark.
* The branch predictor is decoupled from the fetch stage.
* A dedicated
stack engine for modifying the
stack pointer
In computer science, a call stack is a stack data structure that stores information about the active subroutines of a computer program. This kind of stack is also known as an execution stack, program stack, control stack, run-time stack, or mach ...
, similar to that of Intel Haswell and Broadwell processors.
* Move elimination, a method that reduces physical data movement to reduce power consumption.
*
Binary compatibility
Binary-code compatibility (binary compatible or object-code-compatible) is a property of a computer system, meaning that it can run the same executable code, typically machine code for a general-purpose computer CPU, that another computer syst ...
with Intel's
Skylake (excluding VT-x and private MSRs):
**
RDSEED support, a set of high-performance hardware
random number generator
Random number generation is a process by which, often by means of a random number generator (RNG), a sequence of numbers or symbols that cannot be reasonably predicted better than by random chance is generated. This means that the particular out ...
instructions introduced in Broadwell.
** Support for the
SMAP
SMAP was a Japanese boy band, composed of Masahiro Nakai, Takuya Kimura, Goro Inagaki, Tsuyoshi Kusanagi, and Shingo Katori. The group was created in 1988 by music producer Johnny Kitagawa, founder of Johnny & Associates, originally as a six-pi ...
, SMEP, XSAVEC/XSAVES/XRSTORS, and CLFLUSHOPT instructions.
**
ADX support.
**
SHA support.
* CLZERO instruction for clearing a cache line.
Useful for handling ECC-related
Machine-check exception
A machine check exception (MCE) is a type of computer error that occurs when a problem involving the computer's hardware is detected. With most mass-market personal computers, an MCE indicates faulty or misconfigured hardware.
The nature and ...
s.
* PTE (
page table
A page table is the data structure used by a virtual memory system in a computer operating system to store the mapping between virtual addresses and physical addresses. Virtual addresses are used by the program executed by the accessing process, ...
entry)
coalescing, which combines 4kB page tables into 32kB page size.
* "Pure Power" (more accurate power monitoring sensors).
** Support for intel-style running average power limit (RAPL) measurement.
* Smart Prefetch.
* Precision Boost.
* eXtended Frequency Range (XFR), an automated overclocking feature which boosts clock speeds beyond the advertised turbo frequency.
The Zen architecture is built on a
14 nanometer FinFET
A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, f ...
process subcontracted to
GlobalFoundries
GlobalFoundries Inc. (GF or GloFo) is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, th ...
, which in turn licenses its 14nm process from
Samsung Electronics
Samsung Electronics Co., Ltd. (, sometimes shortened to SEC and stylized as SΛMSUNG) is a South Korean multinational corporation, multinational electronics corporation headquartered in Yeongtong-gu, Suwon, South Korea. It is the pinnacle of ...
. This gives greater efficiency than the 32 nm and 28 nm processes of previous
AMD FX CPUs and
AMD APUs, respectively.
The "Summit Ridge" Zen family of CPUs use the AM4 socket and feature
DDR4
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth ("double data rate") interface.
Released to the market in 2014, it is a variant of dynamic rando ...
support and a 95 W TDP (
thermal design power
The thermal design power (TDP), sometimes called thermal design point, is the maximum amount of heat generated by a computer chip or component (often a CPU, GPU or system on a chip) that the cooling system in a computer is designed to dissipate ...
).
While newer roadmaps don't confirm the TDP for desktop products, they suggest a range for low-power mobile products with up to two Zen cores from 5 to 15 W and 15 to 35 W for performance-oriented mobile products with up to four Zen cores.
Each Zen core can decode four
instructions per clock cycle and includes a micro-op cache which feeds two schedulers, one each for the integer and
floating point
In computing, floating-point arithmetic (FP) is arithmetic that represents real numbers approximately, using an integer with a fixed precision, called the significand, scaled by an integer exponent of a fixed base. For example, 12.345 can be ...
segments.
Each core has two address generation units, four integer units, and four floating point units. Two of the floating point units are adders, and two are multiply-adders. However, using multiply-add-operations may prevent simultaneous add operation in one of the adder units. There are also improvements in the branch predictor. The L1 cache size is 64 KB for instructions per core and 32 KB for data per core. The L2 cache size 512 KB per core, and the L3 is 1–2 MB per core. L3 caches offer 5× the bandwidth of previous AMD designs.
History and development
AMD began planning the Zen microarchitecture shortly after re-hiring
Jim Keller in August 2012. AMD formally revealed Zen in 2015.
The team in charge of Zen was led by Keller (who left in September 2015 after a 3-year tenure) and Zen Team Leader Suzanne Plummer.
The Chief Architect of Zen was AMD Senior Fellow Michael Clark.
Zen was originally planned for 2017 following the ARM64-based
K12 sister core, but on AMD's 2015 Financial Analyst Day it was revealed that K12 was delayed in favor of the Zen design, to allow it to enter the market within the 2016 timeframe,
with the release of the first Zen-based processors expected for October 2016.
In November 2015, a source inside AMD reported that Zen microprocessors had been tested and "met all expectations" with "no significant bottlenecks found".
In December 2015, it was rumored that Samsung may have been contracted as a fabricator for AMD's 14 nm FinFET processors, including both Zen and AMD's then-upcoming
Polaris
Polaris is a star in the northern circumpolar constellation of Ursa Minor. It is designated α Ursae Minoris ( Latinized to ''Alpha Ursae Minoris'') and is commonly called the North Star or Pole Star. With an apparent magnitude that ...
GPU architecture. This was clarified by AMD's July 2016 announcement that products had been successfully produced on Samsung's 14 nm FinFET process. AMD stated Samsung would be used "if needed", arguing this would reduce risk for AMD by decreasing dependence on any one foundry.
In December 2019, AMD started putting out first generation Ryzen products built using the second generation Zen+ architecture.
Advantages over predecessors
Manufacturing process
Processors based on Zen use 14 nm
FinFET
A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, f ...
silicon. These processors are reportedly produced at
GlobalFoundries
GlobalFoundries Inc. (GF or GloFo) is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, th ...
. Prior to Zen, AMD's smallest process size was 28 nm, as utilized by their
Steamroller
A steamroller (or steam roller) is a form of road roller – a type of heavy construction machinery used for leveling surfaces, such as roads or airfields – that is powered by a steam engine. The leveling/flattening action is achieved through ...
and
Excavator
Excavators are heavy construction equipment consisting of a boom, dipper (or stick), bucket and cab on a rotating platform known as the "house". The house sits atop an undercarriage with tracks or wheels. They are a natural progression fro ...
microarchitectures. The immediate competition, Intel's
Skylake and
Kaby Lake
Kaby Lake is Intel's codename for its seventh generation Core microprocessor family announced on August 30, 2016. Like the preceding Skylake, Kaby Lake is produced using a 14 nanometer manufacturing process technology. Breaking with Intel's ...
microarchitecture, are also fabricated on 14 nm FinFET; though Intel planned to begin the release of
10 nm
The following are examples of orders of magnitude for different lengths.
__TOC__
Overview
Detailed list
To help compare different orders of magnitude, the following list describes various lengths between 1.6 \times 10^ metres and 10^ ...
parts later in 2017. Intel was unable to reach this goal, and in 2021, only mobile chips have been produced with the 10nm process. In comparison to Intel's 14 nm FinFET, AMD claimed in February 2017 the Zen cores would be 10% smaller. Intel has later announced in July 2018 that 10nm mainstream processors should not be expected before the second half of 2019.
For identical designs, these
die shrink
The term die shrink (sometimes optical shrink or process shrink) refers to the scaling of metal-oxide-semiconductor (MOS) devices. The act of shrinking a die is to create a somewhat identical circuit using a more advanced fabrication process, us ...
s would use less current (and power) at the same frequency (or voltage). As CPUs are usually power limited (typically up to ~125W, or ~45W for mobile), smaller transistors allow for either lower power at the same frequency, or higher frequency at the same power.
Performance
One of Zen's major goals in 2016 was to focus on performance per-core, and it was targeting a 40% improvement in
instructions per cycle (IPC) over its predecessor.
Excavator
Excavators are heavy construction equipment consisting of a boom, dipper (or stick), bucket and cab on a rotating platform known as the "house". The house sits atop an undercarriage with tracks or wheels. They are a natural progression fro ...
, in comparison, offered 4–15% improvement over previous architectures. AMD announced the final Zen microarchitecture actually achieved 52% improvement in IPC over Excavator.
The inclusion of SMT also allows each core to process up to two threads, increasing processing throughput by better use of available resources.
The Zen processors also employ sensors across the chip to dynamically scale frequency and voltage.
This allows for the maximum frequency to be dynamically and automatically defined by the processor itself based upon available cooling.
AMD has demonstrated an 8-core/16-thread Zen processor outperforming an equally-clocked
Intel Broadwell-E processor in
Blender
A blender (sometimes called a mixer or liquidiser in British English) is a kitchen appliance, kitchen and laboratory appliance used to mix, crush, purée or emulsion, emulsify food and other substances. A stationary blender consists of a blender ...
rendering
and
HandBrake benchmarks.
Zen supports
AVX2
Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge ...
but it requires two clock cycles to complete each AVX2 instruction compared to Intel's one. This difference was corrected in
Zen 2
Zen 2 is a computer processor microarchitecture by AMD. It is the successor of AMD's Zen and Zen+ microarchitectures, and is fabricated on the 7 nanometer MOSFET node from TSMC. The microarchitecture powers the third generation of Ryzen proces ...
.
Memory
Zen supports
DDR4 memory (up to eight channels) and
ECC.
Pre-release reports stated APUs using the Zen architecture would also support
High Bandwidth Memory
High Bandwidth Memory (HBM) is a high-speed computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM) initially from Samsung, AMD and SK Hynix. It is used in conjunction with high-performance graphics accelerators ...
(HBM).
However, the first demonstrated APU did not use HBM. Previous APUs from AMD relied on shared memory for both the GPU and the CPU.
Power consumption and heat output
Processors built at the 14 nm node on FinFET silicon should show reduced power consumption and therefore heat over their 28 nm and 32 nm non-FinFET predecessors (for equivalent designs), or be more computationally powerful at equivalent heat output/power consumption.
Zen also uses
clock gating
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation, by removing the clock signal when the circuit is not in use or ignores clock signal. Clock gating saves power by pruning the clock tree, ...
,
reducing the frequency of underutilized portions of the core to save power. This comes from AMD's SenseMI technology, using sensors across the chip to dynamically scale frequency and voltage.
Enhanced security and virtualization support
Zen added support for AMD's Secure Memory Encryption (SME) and AMD's Secure Encrypted Virtualization (SEV). Secure Memory Encryption is real-time memory encryption done per page table entry. Encryption occurs on a hardware AES engine and keys are managed by the onboard "Security" Processor (
ARM Cortex-A5
The ARM Cortex-A5 is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture announced in 2009.
Overview
The Cortex-A5 is intended to replace the ARM9 and ARM11 cores for use in low-end devices. The Cortex-A5 offe ...
) at boot time to encrypt each page, allowing any DDR4 memory (including non-volatile varieties) to be encrypted. AMD SME also makes the contents of the memory more resistant to memory snooping and
cold boot attack
In computer security, a cold boot attack (or to a lesser extent, a platform reset attack) is a type of side channel attack in which an attacker with physical access to a computer performs a memory dump of a computer's random-access memory (RAM) b ...
s.
The Secure Encrypted Virtualization (SEV) feature allows the memory contents of a virtual machine (VM) to be transparently encrypted with a key unique to the guest VM. The memory controller contains a high-performance encryption engine which can be programmed with multiple keys for use by different VMs in the system. The programming and management of these keys is handled by the AMD Secure Processor firmware which exposes an API for these tasks.
Connectivity
Incorporating much of the
southbridge into the
SoC, the Zen CPU includes
SATA
SATA (Serial AT Attachment) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) standard to ...
,
USB
Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply (interfacing) between computers, peripherals and other computers. A broad ...
, and
PCI Express
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
NVMe
NVM Express (NVMe) or Non-Volatile Memory Host Controller Interface Specification (NVMHCIS) is an open, logical-device interface specification for accessing a computer's non-volatile storage media usually attached via PCI Express (PCIe) bus. The ...
links. This can be augmented by available
Socket AM4 chipsets which add connectivity options including additional SATA and USB connections, and support for
AMD's Crossfire and
Nvidia's SLI.
AMD, in announcing its Radeon Instinct line, argued that the upcoming Zen-based Naples server CPU would be particularly suited for building
deep learning
Deep learning (also known as deep structured learning) is part of a broader family of machine learning methods based on artificial neural networks with representation learning. Learning can be supervised, semi-supervised or unsupervised.
De ...
systems. The 128
PCIe
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common mo ...
lanes per Naples CPU allows for eight
Instinct cards to connect at PCIe x16 to a single CPU. This compares favorably to the Intel Xeon line, with only 40 PCIe lanes.
Features
CPUs
CPU features table
APUs
APU features table
Products
The Zen architecture is used in the current-generation desktop
Ryzen
Ryzen ( ) is a brand of multi-core x86-64 microprocessors designed and marketed by AMD for desktop, mobile, server, and embedded platforms based on the Zen microarchitecture. It consists of central processing units (CPUs) marketed for mainst ...
CPUs. It is also in
Epyc
Epyc is a brand of multi-core x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets. Epyc processors share t ...
server processors (successor of
Opteron
Opteron is AMD's x86 former server and workstation processor line, and was the first processor which supported the AMD64 instruction set architecture (known generically as x86-64 or AMD64). It was released on April 22, 2003, with the ''SledgeHa ...
processors), and APUs.
The first desktop processors without graphics processing units (codenamed "Summit Ridge") were initially expected to start selling at the end of 2016, according to an AMD roadmap; with the first mobile and desktop processors of the
AMD Accelerated Processing Unit
AMD Accelerated Processing Unit (APU), formerly known as Fusion, is a series of 64-bit microprocessors from Advanced Micro Devices (AMD), combining a general-purpose AMD64 central processing unit ( CPU) and integrated graphics processing unit ...
type (codenamed "Raven Ridge") following in late 2017. AMD officially delayed Zen until Q1 of 2017. In August 2016, an early demonstration of the architecture showed an 8-core/16-thread engineering sample CPU at 3.0 GHz.
In December 2016, AMD officially announced the desktop CPU line under the
Ryzen
Ryzen ( ) is a brand of multi-core x86-64 microprocessors designed and marketed by AMD for desktop, mobile, server, and embedded platforms based on the Zen microarchitecture. It consists of central processing units (CPUs) marketed for mainst ...
brand for release in Q1 2017. It also confirmed Server processors would be released in Q2 2017, and mobile APUs in H2 2017.
On March 2, 2017, AMD officially launched the first Zen architecture-based octacore Ryzen desktop CPUs. The final clock speeds and TDPs for the 3 CPUs released in Q1 of 2017 demonstrated significant performance-per-watt benefits over the previous
K15h (Piledriver) architecture. The octacore Ryzen desktop CPUs demonstrated performance-per-watt comparable to Intel's Broadwell octacore CPUs.
In March 2017, AMD also demonstrated an engineering sample of a server CPU based on the Zen architecture. The CPU (codenamed "Naples") was configured as a dual-socket server platform with each CPU having 32 cores/64 threads.
Desktop processors
Desktop APUs
Ryzen APUs are identified by either the G or GE suffix in their name.
Mobile APUs
Ultra-mobile APUs
Dalí
Pollock
Embedded processors
V1000
In February 2018, AMD announced the V1000 series of embedded Zen+Vega APUs with four SKUs.
R1000
In 2019, AMD announced the R1000 series of embedded Zen+Vega APUs.
Server processors
![EpycProcessor](https://upload.wikimedia.org/wikipedia/commons/7/7d/EpycProcessor.jpg)
AMD announced in March 2017 that it would release a server platform based on Zen, codenamed Naples, in the second quarter of the year. The platform include 1- and 2-socket systems. The CPUs in multi-processor configurations communicate via AMD's Infinity Fabric. Each chip supports eight channels of memory and 128 PCIe 3.0 lanes, of which 64 lanes are used for CPU-to-CPU communication through Infinity Fabric when installed in a dual-processor configuration. AMD officially revealed Naples under the brand name Epyc in May 2017.
On June 20, 2017, AMD officially released the Epyc 7000 series CPUs at a launch event in Austin, Texas.
Embedded server processors
In February 2018, AMD also announced the EPYC 3000 series of embedded Zen CPUs.
See also
*
AMD K9
The AMD K9 represents a microarchitecture by AMD designed to replace the K8 processors, featuring dual-core processing.
Development
K9 appears originally to have been an ambitious 8 issue per clock cycle core redesign of the K7 or the K8 pr ...
*
AMD K10
The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. Though there were once reports that the K10 had been canceled,
*
Jim Keller (engineer)
James B. Keller (born 1958/1959) is a microprocessor engineer best known for his work at AMD and Apple. He was the lead architect of the AMD K8 microarchitecture (including the original Athlon 64) and was involved in designing the Athlon (K7) a ...
*
Ryzen
Ryzen ( ) is a brand of multi-core x86-64 microprocessors designed and marketed by AMD for desktop, mobile, server, and embedded platforms based on the Zen microarchitecture. It consists of central processing units (CPUs) marketed for mainst ...
*
Steamroller (microarchitecture)
AMD Steamroller Family 15h is a microarchitecture developed by AMD for AMD APUs, which succeeded Piledriver in the beginning of 2014 as the third-generation Bulldozer-based microarchitecture. Steamroller APUs continue to use two-core modules as ...
*
Zen+
Zen+ is the codename for a computer processor microarchitecture by AMD. It is the successor to the first gen Zen microarchitecture, first released in April 2018, powering the second generation of Ryzen processors, known as Ryzen 2000 for mainstre ...
*
Zen 2
Zen 2 is a computer processor microarchitecture by AMD. It is the successor of AMD's Zen and Zen+ microarchitectures, and is fabricated on the 7 nanometer MOSFET node from TSMC. The microarchitecture powers the third generation of Ryzen proces ...
References
External links
Ryzen ProcessorsAMD
{{DEFAULTSORT:Zen 1.0
AMD microarchitectures
Computer-related introductions in 2017
X86 microarchitectures