Intel CPU Core i7 2600K Sandy Bridge perspective

Sandy Bridge is the

codename A code name, call sign or cryptonym is a code word or name used, sometimes clandestinely, to refer to another name, word, project, or person. Code names are often used for military purposes, or in espionage. They may also be used in industrial c ...

for Intel's 32 nm

microarchitecture In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular processor. A given ISA may be imp ...

used in the second generation of the Intel Core processors ( Core i7, i5, i3). The Sandy Bridge microarchitecture is the successor to Nehalem and Westmere microarchitecture. Intel demonstrated a Sandy Bridge processor in 2009, and released first products based on the architecture in January 2011 under the Core brand. Sandy Bridge is manufactured in the 32 nm process and has a soldered contact with the die and IHS (Integrated Heat Spreader), while Intel's subsequent generation Ivy Bridge uses a

22 nm The 22 nm node is the process step following 32 nm in CMOS MOSFET semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22 nm. ...

die shrink The term die shrink (sometimes optical shrink or process shrink) refers to the scaling of metal-oxide-semiconductor (MOS) devices. The act of shrinking a die is to create a somewhat identical circuit using a more advanced fabrication process, ...

and a TIM (Thermal Interface Material) between the die and the IHS.

Technology

Intel demonstrated a Sandy Bridge processor with A1 stepping at 2 GHz during the

Intel Developer Forum The Intel Developer Forum (IDF) was a biannual gathering of technologists to discuss Intel products and products based on Intel products. The first IDF was held in 1997. To emphasize the importance of China, the Spring 2007 IDF was held in Beij ...

in September 2009. Upgraded features from Nehalem include:

CPU

* Intel Turbo Boost 2.0 * 32 KB data + 32 KB instruction L1 cache and 256 KB

L2 cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, whic ...

per core * Shared L3 cache which includes the processor graphics ( LGA 1155) * 64-byte cache line size * New µOP cache, up to 1536-entry * Improved 3 integer ALU, 2 vector ALU and 2 AGU per core * Two load/store operations per

CPU cycle The instruction cycle (also known as the fetch–decode–execute cycle, or simply the fetch-execute cycle) is the cycle that the central processing unit (CPU) follows from boot-up until the computer has shut down in order to process instructions ...

for each memory channel * Decoded micro-operation cache, and enlarged, optimized

branch predictor In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g., an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow i ...

* Sandy Bridge retains the four branch predictors found in Nehalem: the branch target buffer (BTB), indirect branch target array, loop detector and renamed

return stack buffer Return may refer to: In business, economics, and finance * Return on investment (ROI), the financial gain after an expense. * Rate of return, the financial term for the profit or loss derived from an investment * Tax return, a blank document or t ...

(RSB). Sandy Bridge has a single BTB that holds twice as many branch targets as the L1 and L2 BTBs in Nehalem. * Improved performance for transcendental mathematics,

AES encryption The Advanced Encryption Standard (AES), also known by its original name Rijndael (), is a specification for the encryption of electronic data established by the U.S. National Institute of Standards and Technology (NIST) in 2001. AES is a variant ...

(

AES instruction set An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...

), and

SHA-1 In cryptography, SHA-1 (Secure Hash Algorithm 1) is a cryptographically broken but still widely used hash function which takes an input and produces a 160-bit (20- byte) hash value known as a message digest – typically rendered as 40 hexadec ...

hashing * 256-bit/cycle ring bus interconnect between cores, graphics, cache and System Agent Domain *

Advanced Vector Extensions Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridg ...

(AVX) 256-bit instruction set with wider vectors, new extensible syntax and rich functionality * Up to 8 physical cores, or 16 logical cores through

hyper-threading Hyper-threading (officially called Hyper-Threading Technology or HT Technology and abbreviated as HTT or HT) is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multi ...

(From 6 core/12 thread) * Integration of the GMCH (integrated graphics and memory controller) and processor into a single die inside the processor package. In contrast, Sandy Bridge's predecessor, Clarkdale, has two separate dies (one for GMCH, one for processor) within the processor package. This tighter integration reduces memory latency even more. * A 14- to 19-stage

instruction pipeline In computer engineering, instruction pipelining or ILP is a technique for implementing instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing inco ...

, depending on the micro-operation cache hit or miss * Increased ROB to 168 entries (From 128) * Larger Scheduler buffer (54-entry, up from 26-entry) : : All translation lookaside buffers (TLBs) are 4-way

associative In mathematics, the associative property is a property of some binary operations, which means that rearranging the parentheses in an expression will not change the result. In propositional logic, associativity is a valid rule of replacement ...

GPU

* Intel Quick Sync Video, hardware support for video encoding and decoding * Integrated graphics is now integrated on the same die

I/O

* Integrated PCIe Controller

Models and steppings

All Sandy Bridge processors with one, two, or four cores report the same CPUID model 0206A7h and are closely related. The stepping number cannot be seen from the CPUID but only from the PCI configuration space. The later Sandy Bridge-E processors with up to eight cores and no graphics are using CPUIDs 0206D6h and 0206D7h. Ivy Bridge CPUs all have CPUID 0306A9h to date, and are built in four different configurations differing in the number of cores, L3 cache and GPU execution units:

Performance

* The average performance increase, according to IXBT Labs and Semi Accurate as well as many other benchmarking sites, at clock to clock is 11.3% compared to the Nehalem generation, which includes Bloomfield, Clarkdale, and Lynnfield processors. * Around twice the integrated graphics performance compared to Clarkdale's (12

EUs Eus ( in both French and Catalan) is a commune in the Pyrénées-Orientales department in southern France. Geography Localization Eus is located in the canton of Les Pyrénées catalanes and in the arrondissement of Prades. Population ...

comparison).

List of Sandy Bridge processors

¹Processors featuring Intel's HD 3000 graphics are set in bold. Other processors feature HD 2000 graphics, HD graphics (Pentium and Celeron models) or no graphics core (Graphics Clock rate indicated by N/A). * This list may not contain all the Sandy Bridge processors released by Intel. A more complete listing can be found on Intel's website.

Desktop platform

Suffixes to denote: * K – Unlocked (adjustable CPU ratio up to 57 bins) * P – Versions clocked slightly higher than similar models, but with onboard-graphics deactivated * S – Performance-optimized lifestyle (low power with 65W TDP) * T – Power-optimized lifestyle (ultra low power with 35-45W TDP) * X – Extreme performance (adjustable CPU ratio with no ratio limit) NOTE
3970X3960X3930K
an
3820
are actually of Sandy Bridge-E edition.

Server platform

Mobile platform

* Core i5-2515E and Core i7-2715QE processors have support for ECC memory and PCI express port bifurcation. * All mobile processors, except

Celeron Celeron is Intel's brand name for low-end IA-32 and x86-64 computer microprocessor models targeted at low-cost personal computers. Celeron processors are compatible with IA-32 software. They typically offer less performance per clock speed comp ...

and

Pentium Pentium is a brand used for a series of x86 architecture-compatible microprocessors produced by Intel. The original Pentium processor from which the brand took its name was first released on March 22, 1993. After that, the Pentium II and P ...

, use Intel's Graphics subsystem HD 3000 (12 EUs). Suffixes to denote: * M – Mobile processors ** XM – Unlocked ** QM – Quad-core * E – Embedded mobile processors ** QE – Quad-core ** LE – Performance-optimized ** UE – Power-optimized

Cougar Point chipset flaw

On 31 January 2011, Intel issued a recall on all 67-series motherboards due to a flaw in the Cougar Point Chipset. A hardware problem exists, in which the chipset's

SATA II SATA (Serial AT Attachment) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) standard t ...

ports may fail over time, causing failure of connection to SATA devices, though data is not at risk. Intel claims that this problem will affect only 5% of users over 3 years; however, heavier I/O workloads can exacerbate the problem. Intel stopped production of flawed B2 stepping chipsets and began producing B3 stepping chipsets with the silicon fix. Shipping of these new chipsets started on 14 February 2011 and Intel estimated full recovery volume in April 2011. Motherboard manufacturers (such as ASUS and Gigabyte Technology) and computer manufacturers (such as

Dell Dell is an American based technology company. It develops, sells, repairs, and supports computers and related products and services. Dell is owned by its parent company, Dell Technologies. Dell sells personal computers (PCs), servers, data ...

and Hewlett-Packard) stopped selling products that involved the flawed chipset and offered support for affected customers. Options ranged from swapping for B3 motherboards to product refunds. Sandy Bridge processor sales were temporarily on hold, as one cannot use the CPU without a motherboard. However, processor release dates were not affected. After two weeks, Intel continued shipping some chipsets, but manufacturers had to agree to a set of terms that will prevent customers from encountering the bug.

Limitations

Overclocking

With Sandy Bridge, Intel has tied the speed of every bus (USB, SATA, PCI, PCI-E, CPU cores, Uncore, memory etc.) to a single internal clock generator issuing the basic Base Clock (BClk). With CPUs being multiplier locked, the only way to overclock is to increase the BClk, which can be raised by only 5–7% without other hardware components failing. As a work around, Intel made available K/X-series processors, which feature unlocked multipliers; with a multiplier cap of 57 for Sandy Bridge. For the Sandy Bridge-E platform, there is alternative method known as the BClk ratio overclock. During IDF (

) 2010, Intel demonstrated an unknown Sandy Bridge CPU running stably overclocked at 4.9 GHz on air cooling.

Chipset

Non-K edition CPUs can overclock up to four bins from its turbo multiplier. Refer here for chipset support.

vPro remote-control

Sandy and Ivy Bridge processors with

vPro The VPRO (stylized vpro; originally an acronym for , ) is a Dutch public broadcaster, which forms a part of the Dutch public broadcasting system. Founded in 1926 as a liberal Protestant broadcasting organization, it gradually became more so ...

capability have security features that can remotely disable a PC or erase information from hard drives. This can be useful in the case of a lost or stolen PC. The commands can be received through 3G signals, Ethernet, or Internet connections. AES encryption acceleration will be available, which can be useful for video conferencing and VoIP applications.

Intel Insider

Sandy and Ivy Bridge processors contain a DRM technology that some video streaming web sites rely on to restrict use of their content. Such web sites offer 1080p streaming to users with such CPUs and downgrade the quality for other users.

Software development kit

With the introduction of the Sandy Bridge microarchitecture, Intel also introduced the

Intel Data Plane Development Kit The Data Plane Development Kit (DPDK) is an open source software project managed by the Linux Foundation. It provides a set of data plane libraries and network interface controller polling-mode drivers for offloading TCP packet processing from ...

(Intel DPDK) to help developers of communications applications take advantage of the platform in

packet processing In digital communications networks, packet processing refers to the wide variety of algorithms that are applied to a packet of data or information as it moves through the various network elements of a communications network. With the increased p ...

applications, and

network processor A network processor is an integrated circuit which has a feature set specifically targeted at the Computer networking, networking application domain. Network processors are typically software programmable devices and would have generic characteris ...

Roadmap

Intel demonstrated the Haswell architecture in September 2011, released in 2013 as the successor to Sandy Bridge and Ivy Bridge.

Fixes

Microsoft has released a microcode update for selected Sandy Bridge and Ivy Bridge CPUs for Windows 7 and up that addresses stability issues. The update, however, negatively impacts Intel G3258 and 4010U CPU models.

Trivia

Contains uROM implementation of

Eight queens puzzle The eight queens puzzle is the problem of placing eight chess queens on an 8×8 chessboard so that no two queens threaten each other; thus, a solution requires that no two queens share the same row, column, or diagonal. There are 92 solutions. ...

, supporting up-to 20x20, 76*2 bytes ROM, 83*4 bytes data, 185us for all 92 solutions of 8x8 board, 15.24sec for 15x15.