Nehalem is the

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for

Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the devel ...

's 45 nm

microarchitecture In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular processor. A given ISA may be imp ...

released in November 2008. It was used in the first-generation of the

Intel Core Intel Core is a line of streamlined midrange consumer, workstation and enthusiast computer central processing units (CPUs) marketed by Intel Corporation. These processors displaced the existing mid- to high-end Pentium processors at the time ...

i5 and i7 processors, and succeeds the older Core microarchitecture used on Core 2 processors. The term "Nehalem" comes from the Nehalem River. Nehalem is built on the 45 nm process, is able to run at higher clock speeds, and is more energy-efficient than Penryn microprocessors. Hyper-threading is reintroduced, along with a reduction in L2 cache size, as well as an enlarged L3 cache that is shared among all cores. Nehalem is an architecture that differs radically from Netburst, while retaining some of the latter's minor features. Nehalem later received a die-shrink to 32 nm with Westmere, and was fully succeeded by "second-generation" Sandy Bridge in January 2011.

Technology

* Cache line block on L2/L3 cache was reduced from 128 bytes in Netburst & Conroe/Penryn to 64 bytes per line in this generation (same size as Yonah and Pentium M). * Hyper-threading reintroduced. * Intel Turbo Boost 1.0. * 2–24 MiB L3 cache *

Instruction Fetch Unit The instruction unit (I-unit or IU), also called, e.g., instruction fetch unit (IFU), instruction issue unit (IIU), instruction sequencing unit (ISU), in a central processing unit (CPU) is responsible for organizing program instructions to be fetche ...

(IFU) containing second-level

branch predictor In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g., an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow i ...

with two level Branch Target Buffer (BTB) and

Return Stack Buffer Return may refer to: In business, economics, and finance * Return on investment (ROI), the financial gain after an expense. * Rate of return, the financial term for the profit or loss derived from an investment * Tax return, a blank document or t ...

(RSB). Nehalem also supports all predictor types previously used in Intel's processors like Indirect Predictor and Loop Detector. * sTLB (second level unified

translation lookaside buffer A translation lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory to physical memory. It is used to reduce the time taken to access a user memory location. It can be called an address-translation cache. ...

) (i.e. both instructions and data) that contains 512 entries for small pages only, and is again 4 way associative. * 3 integer ALU, 2 vector ALU and 2 AGU per core. * Native (all processor cores on a single die) quad- and octa-core processors *

Intel QuickPath Interconnect The Intel QuickPath Interconnect (QPI) is a point-to-point processor interconnect developed by Intel which replaced the front-side bus (FSB) in Xeon, Itanium, and certain desktop platforms starting in 2008. It increased the scalability and availab ...

in high-end models replacing the legacy front side bus * 64 KB L1 cache per core (32 KB L1 data and 32 KB L1 instruction), and 256 KB L2 cache per core. * Integration of

PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common m ...

and

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into the processor in mid-range models, replacing the northbridge * Integrated

memory controller The memory controller is a digital circuit that manages the flow of data going to and from the computer's main memory. A memory controller can be a separate chip or integrated into another chip, such as being placed on the same die or as an in ...

supporting two or three memory channels of DDR3 SDRAM or four FB-DIMM2 channels * Second-generation Intel Virtualization Technology, which introduced Extended Page Table support, virtual processor identifiers (VPIDs), and non-maskable interrupt-window exiting *

SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...

and POPCNT instructions *

Macro-op fusion In computer central processing units, micro-operations (also known as micro-ops or μops, historically also as micro-actions) are detailed low-level instructions used in some designs to implement complex machine instructions (sometimes termed m ...

now works in 64-bit mode. * 20 to 24 pipeline stages :

Performance and power improvements

It has been reported that Nehalem has a focus on performance, thus the increased core size. Compared to Penryn, Nehalem has: * 10–25% better single-threaded performance / 20–100% better multithreaded performance at the same power level * 30% lower power consumption for the same

performance A performance is an act of staging or presenting a play, concert, or other form of entertainment. It is also defined as the action or process of carrying out or accomplishing an action, task, or function. Management science In the work place ...

* On average, Nehalem provides a 15–20% clock-for-clock increase in performance per core. Overclocking is possible with Bloomfield processors and the X58 chipset. Lynnfield processors use a PCH removing the need for a northbridge. Nehalem processors incorporate SSE 4.2

SIMD Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal (part of the hardware design) and it can be directly accessible through an instruction set architecture (ISA), but it should ...

instructions, adding seven new instructions to the SSE 4.1 set in the Core 2 series. The Nehalem architecture reduces atomic operation latency by 50% in an attempt to eliminate overhead on atomic operations such as the LOCK CMPXCHG compare-and-swap instruction.

Variants

* Lynnfield processors feature 16

PCIe PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common m ...

lanes, which can be used in 1x16 or 2x8 configuration. * ¹ 6500 series scalable up to 2 sockets, 7500 series scalable up to 4/8 sockets.

Server and desktop processors

* Intel states the Gainestown processors have six memory channels. Gainestown processors have dual QPI links and have a separate set of memory registers for each link in effect, a multiplexed six-channel system.

Mobile processors

References

External links

Nehalem processor
at

.com {{Intel processor roadmap Intel x86 microprocessors Intel microarchitectures X86 microarchitectures