List Of AMD Athlon Processors
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Athlon Athlon is the brand name applied to a series of x86-compatible microprocessors designed and manufactured by Advanced Micro Devices (AMD). The original Athlon (now called Athlon Classic) was the first seventh-generation x86 processor and the fi ...
is the name of a family of CPUs designed by
AMD Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactur ...
, targeted mostly at the desktop market. It has been largely unused as just "Athlon" since 2001 when AMD started naming its processors
Athlon XP Athlon is the brand name applied to a series of x86-compatible microprocessors designed and manufactured by Advanced Micro Devices (AMD). The original Athlon (now called Athlon Classic) was the first seventh-generation x86 processor and the fi ...
, but in 2008 began referring to single core 64-bit processors from the AMD Athlon X2 and
AMD Phenom Phenom is the 64-bit AMD desktop processor line based on the K10 microarchitecture, in what AMD calls family 10h (10 hex, i.e. 16 in normal decimal numbers) processors, sometimes incorrectly called "K10h". Triple-core versions (codenamed ''To ...
product lines. Later the name began being used for some
APUs Apus is a small constellation in the Southern Celestial Hemisphere, southern sky. It represents a bird-of-paradise, and its name means "without feet" in Greek language, Greek because the bird-of-paradise was once wrongly believed to lack feet. ...
.


Features overview


"Pure" CPUs

CPU features table


APUs

APU features table


Athlon (Model 1,K7 "Argon", 250 nm)

* L2 cache always runs with 50% of CPU speed * All models support: '' MMX, Enhanced 3DNow!''


Athlon (Model 2, K75 "Pluto/Orion", 180 nm)

* L2 cache runs with 50% (up to 700 MHz), 40% (up to 850 MHz) or 33% (up to 1000 MHz) of CPU speed. * 900 - 1000 MHz have Orion designation. * All models support: '' MMX, Enhanced 3DNow!''


Athlon (Model 4, "Thunderbird", 180 nm)

* L2 cache always runs with full CPU speed * All models support: '' MMX, Enhanced 3DNow!''


Athlon XP


Athlon 64


Athlon X2


Athlon II


Athlon (Piledriver)


"Trinity" (2012)

* Platform "Virgo" * Fabrication 32 nm on GlobalFoundries SOI process * Socket FM2 * CPU: Piledriver ** L1 Cache: 16 KB Data per core and 64 KB Instructions per module * Die Size: , 1.303 Billion transistors * Support for up to four DIMMs of up to DDR3-1866 memory * 5 GT/s UMI * Integrated
PCIe 2.0 PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial communication, serial computer expansion bus standard, designed to replace the older Conventional PCI, PCI, PCI-X and A ...
controller, and Turbo Core technology for faster CPU/GPU operation when the thermal specification permits * MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitecture ...
,
SSE4a SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
,
SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; mor ...
,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core (microarchitecture), Core microarchitecture and AMD K10, AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vag ...
,
AMD64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
,
AMD-V x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
, AES,
CLMUL Carry-less Multiplication (CLMUL) is an extension to the x86 instruction set used by microprocessors from Intel and AMD which was proposed by Intel in March 2008 and made available in the Intel Westmere processors announced in early 2010. Mathemati ...
,
AVX AVX may refer to: Technology * Advanced Vector Extensions, an instruction set extension in the x86 microprocessor architecture ** AVX2, an expansion of the AVX instruction set ** AVX-512, 512-bit extensions to the 256-bit AVX * AVX Corporation, a m ...
, XOP,
FMA3 The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations."FMA3 and FMA4 are not instruction sets, they are indi ...
, FMA4,
F16C The F16C (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats. History The ...
,
ABM ABM or Abm may refer to: Companies * ABM Industries, a US facility management provider * ABM Intelligence, a UK software company * Advantage Business Media, a US digital marketing and information services company * Associated British Maltsters, ac ...
,
BMI1 Polycomb complex protein BMI-1 also known as polycomb group RING finger protein 4 (PCGF4) or RING finger protein 51 (RNF51) is a protein that in humans is encoded by the ''BMI1'' gene ( B cell-specific Moloney murine leukemia virus integration ...
, TBM


"Richland" (2013)

* Fabrication 32 nm on GlobalFoundries SOI process * Socket FM2 * Two or four CPU cores based on the Piledriver microarchitecture ** Die Size: , 1.303 Billion transistors ** L1 Cache: 16 KB Data per core and 64 KB Instructions per module ** MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, SSSE3,
SSE4a SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, SSE4.1, SSE4.2,
AMD64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
,
AMD-V x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
, AES,
AVX AVX may refer to: Technology * Advanced Vector Extensions, an instruction set extension in the x86 microprocessor architecture ** AVX2, an expansion of the AVX instruction set ** AVX-512, 512-bit extensions to the 256-bit AVX * AVX Corporation, a m ...
, AVX1.1, XOP,
FMA3 The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations."FMA3 and FMA4 are not instruction sets, they are indi ...
, FMA4,
F16C The F16C (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats. History The ...
,
ABM ABM or Abm may refer to: Companies * ABM Industries, a US facility management provider * ABM Intelligence, a UK software company * Advantage Business Media, a US digital marketing and information services company * Associated British Maltsters, ac ...
,
BMI1 Polycomb complex protein BMI-1 also known as polycomb group RING finger protein 4 (PCGF4) or RING finger protein 51 (RNF51) is a protein that in humans is encoded by the ''BMI1'' gene ( B cell-specific Moloney murine leukemia virus integration ...
, TBM, Turbo Core 3.0,
NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...
,
PowerNow! __NOTOC__ AMD PowerNow! is AMD's dynamic frequency scaling and power saving technology for laptop processors. The CPU's clock speed and VCore are automatically decreased when the computer is under low load or idle, to save battery power, reduce ...


Athlon (Jaguar)


"Kabini" (2013, SoC)

* Fabrication 28 nm by
GlobalFoundries GlobalFoundries Inc. (GF or GloFo) is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, th ...
*
Socket AM1 Socket FS1b (rebranded as Socket AM1 ) is a socket designed by AMD, launched in April 2014 for desktop SoCs in the value segment. Socket AM1 is intended for a class of CPUs that contain both an integrated GPU and a chipset, essentially forming a ...
, aka Socket FS1b (AM1 platform) * 2 to 4 CPU Cores (
Jaguar (microarchitecture) The AMD Jaguar Family 16h is a low-power microarchitecture designed by AMD. It is used in APUs succeeding the Bobcat Family microarchitecture in 2013 and being succeeded by AMD's Puma architecture in 2014. It is two-way superscalar and capable ...
) * L1 Cache: 32 KB Data per core and 32 KB Instructions per core * MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitecture ...
,
SSE4a SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
,
SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; mor ...
,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core (microarchitecture), Core microarchitecture and AMD K10, AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vag ...
,
AMD64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
,
AVX AVX may refer to: Technology * Advanced Vector Extensions, an instruction set extension in the x86 microprocessor architecture ** AVX2, an expansion of the AVX instruction set ** AVX-512, 512-bit extensions to the 256-bit AVX * AVX Corporation, a m ...
,
F16C The F16C (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats. History The ...
,
CLMUL Carry-less Multiplication (CLMUL) is an extension to the x86 instruction set used by microprocessors from Intel and AMD which was proposed by Intel in March 2008 and made available in the Intel Westmere processors announced in early 2010. Mathemati ...
, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT,
ABM ABM or Abm may refer to: Companies * ABM Industries, a US facility management provider * ABM Intelligence, a UK software company * Advantage Business Media, a US digital marketing and information services company * Associated British Maltsters, ac ...
,
BMI1 Polycomb complex protein BMI-1 also known as polycomb group RING finger protein 4 (PCGF4) or RING finger protein 51 (RNF51) is a protein that in humans is encoded by the ''BMI1'' gene ( B cell-specific Moloney murine leukemia virus integration ...
,
AMD-V x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
support * SoC with integrated memory, PCIe, 2× USB 3.0, 6× USB 2.0, Gigabit Ethernet, and 2× SATA III (6 Gb/s) controllers * GPU based on
Graphics Core Next Graphics Core Next (GCN) is the codename for a series of microarchitectures and an instruction set architecture that were developed by AMD for its GPUs as the successor to its TeraScale microarchitecture. The first product featuring GCN was lau ...
(GCN)


Athlon (Steamroller, Excavator)


"Kaveri" (2014) & "Godavari" (2015)

* Fabrication 28 nm by
GlobalFoundries GlobalFoundries Inc. (GF or GloFo) is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, th ...
. *
Socket FM2+ Socket FM2+ (FM2b, FM2r2) is a zero insertion force CPU socket designed by AMD for their desktop "Kaveri" APUs (Steamroller-based) and Godavari APUs (Steamroller-based) to connect to the motherboard. The FM2+ has a slightly different pin configur ...
, support for
PCIe 3.0 PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common mot ...
. * Two or four CPU cores based on the
Steamroller A steamroller (or steam roller) is a form of road roller – a type of heavy construction machinery used for leveling surfaces, such as roads or airfields – that is powered by a steam engine. The leveling/flattening action is achieved through ...
microarchitecture. **Kaveri refresh models have codename Godavari. * Die Size: , 2.41 Billion transistors. * L1 Cache: 16 KB Data per core and 96 KB Instructions per module. * MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitecture ...
,
SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; mor ...
,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core (microarchitecture), Core microarchitecture and AMD K10, AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vag ...
,
SSE4a SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
,
AMD64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
,
AMD-V x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
, AES,
CLMUL Carry-less Multiplication (CLMUL) is an extension to the x86 instruction set used by microprocessors from Intel and AMD which was proposed by Intel in March 2008 and made available in the Intel Westmere processors announced in early 2010. Mathemati ...
,
AVX AVX may refer to: Technology * Advanced Vector Extensions, an instruction set extension in the x86 microprocessor architecture ** AVX2, an expansion of the AVX instruction set ** AVX-512, 512-bit extensions to the 256-bit AVX * AVX Corporation, a m ...
, AVX 1.1, XOP,
FMA3 The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations."FMA3 and FMA4 are not instruction sets, they are indi ...
, FMA4,
F16C The F16C (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats. History The ...
,
ABM ABM or Abm may refer to: Companies * ABM Industries, a US facility management provider * ABM Intelligence, a UK software company * Advantage Business Media, a US digital marketing and information services company * Associated British Maltsters, ac ...
,
BMI1 Polycomb complex protein BMI-1 also known as polycomb group RING finger protein 4 (PCGF4) or RING finger protein 51 (RNF51) is a protein that in humans is encoded by the ''BMI1'' gene ( B cell-specific Moloney murine leukemia virus integration ...
, TBM,
Turbo Core AMD Turbo Core a.k.a. AMD Core Performance Boost (CPB) is a dynamic frequency scaling technology implemented by AMD that allows the processor to dynamically adjust and control the processor operating frequency in certain versions of its processors ...
* Dual-channel (2× 64 Bit)
DDR3 Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface, and has been in use since 2007. It is the higher-speed ...
memory controller.


"Carrizo" (2016)

* Fabrication 28 nm by
GlobalFoundries GlobalFoundries Inc. (GF or GloFo) is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, th ...
* Socket FM2+, AM4, support for
PCIe 3.0 PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common mot ...
* Two or four CPU cores based on the
Excavator Excavators are heavy construction equipment consisting of a boom, dipper (or stick), bucket and cab on a rotating platform known as the "house". The house sits atop an undercarriage with tracks or wheels. They are a natural progression fro ...
microarchitecture * Die Size: , 3.1 Billion transistors * L1 Cache: 32 KB Data per core and 96 KB Instructions per module * MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitecture ...
,
SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; mor ...
,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core (microarchitecture), Core microarchitecture and AMD K10, AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vag ...
,
SSE4a SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
,
AMD64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
,
AMD-V x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
, AES,
CLMUL Carry-less Multiplication (CLMUL) is an extension to the x86 instruction set used by microprocessors from Intel and AMD which was proposed by Intel in March 2008 and made available in the Intel Westmere processors announced in early 2010. Mathemati ...
,
AVX AVX may refer to: Technology * Advanced Vector Extensions, an instruction set extension in the x86 microprocessor architecture ** AVX2, an expansion of the AVX instruction set ** AVX-512, 512-bit extensions to the 256-bit AVX * AVX Corporation, a m ...
, AVX 1.1,
AVX2 Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge ...
, XOP,
FMA3 The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations."FMA3 and FMA4 are not instruction sets, they are indi ...
, FMA4,
F16C The F16C (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats. History The ...
,
ABM ABM or Abm may refer to: Companies * ABM Industries, a US facility management provider * ABM Intelligence, a UK software company * Advantage Business Media, a US digital marketing and information services company * Associated British Maltsters, ac ...
,
BMI1 Polycomb complex protein BMI-1 also known as polycomb group RING finger protein 4 (PCGF4) or RING finger protein 51 (RNF51) is a protein that in humans is encoded by the ''BMI1'' gene ( B cell-specific Moloney murine leukemia virus integration ...
,
BMI2 Bit manipulation instructions sets (BMI sets) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is to improve the speed of bit manipulation. All the instructions i ...
, TBM,
RDRAND RDRAND (for "read random"; known as Intel Secure Key Technology, previously known as Bull Mountain) is an instruction for returning random numbers from an Intel on-chip hardware random number generator which has been seeded by an on-chip entropy s ...
,
Turbo Core AMD Turbo Core a.k.a. AMD Core Performance Boost (CPB) is a dynamic frequency scaling technology implemented by AMD that allows the processor to dynamically adjust and control the processor operating frequency in certain versions of its processors ...
* Dual-channel DDR3 or
DDR4 Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth ("double data rate") interface. Released to the market in 2014, it is a variant of dynamic rando ...
memory controller


"Bristol Ridge" (2016)

* Fabrication 28 nm by
GlobalFoundries GlobalFoundries Inc. (GF or GloFo) is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, th ...
*
Socket AM4 Socket AM4 is a PGA microprocessor socket used by AMD's central processing units (CPUs) built on the Zen (including Zen+, Zen 2 and Zen 3) and Excavator microarchitectures. ''AM4'' was launched in September 2016 and was designed to replace the ...
, support for
PCIe 3.0 PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common mot ...
* Two or four " Excavator+" CPU cores * L1 Cache: 32 KB Data per core and 96 KB Instructions per module * MMX, SSE,
SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...
,
SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitecture ...
,
SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; mor ...
,
SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core (microarchitecture), Core microarchitecture and AMD K10, AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vag ...
,
SSE4a SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
,
AMD64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
,
AMD-V x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
, AES,
CLMUL Carry-less Multiplication (CLMUL) is an extension to the x86 instruction set used by microprocessors from Intel and AMD which was proposed by Intel in March 2008 and made available in the Intel Westmere processors announced in early 2010. Mathemati ...
,
AVX AVX may refer to: Technology * Advanced Vector Extensions, an instruction set extension in the x86 microprocessor architecture ** AVX2, an expansion of the AVX instruction set ** AVX-512, 512-bit extensions to the 256-bit AVX * AVX Corporation, a m ...
, AVX 1.1,
AVX2 Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge ...
, XOP,
FMA3 The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations."FMA3 and FMA4 are not instruction sets, they are indi ...
, FMA4,
F16C The F16C (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats. History The ...
,
ABM ABM or Abm may refer to: Companies * ABM Industries, a US facility management provider * ABM Intelligence, a UK software company * Advantage Business Media, a US digital marketing and information services company * Associated British Maltsters, ac ...
,
BMI1 Polycomb complex protein BMI-1 also known as polycomb group RING finger protein 4 (PCGF4) or RING finger protein 51 (RNF51) is a protein that in humans is encoded by the ''BMI1'' gene ( B cell-specific Moloney murine leukemia virus integration ...
,
BMI2 Bit manipulation instructions sets (BMI sets) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is to improve the speed of bit manipulation. All the instructions i ...
, TBM,
RDRAND RDRAND (for "read random"; known as Intel Secure Key Technology, previously known as Bull Mountain) is an instruction for returning random numbers from an Intel on-chip hardware random number generator which has been seeded by an on-chip entropy s ...
,
Turbo Core AMD Turbo Core a.k.a. AMD Core Performance Boost (CPB) is a dynamic frequency scaling technology implemented by AMD that allows the processor to dynamically adjust and control the processor operating frequency in certain versions of its processors ...
* Dual-channel
DDR4 Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth ("double data rate") interface. Released to the market in 2014, it is a variant of dynamic rando ...
memory controller *
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
3.0 x8 (No Bifurcation support, requires a PCI-e switch for any configuration other than x8) *
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
3.0 x4 as link to optional external chipset * 4x
USB 3.1 USB 3.0, released in November 2008, is the third major version of the Universal Serial Bus (USB) standard for interfacing computers and electronic devices. Among other improvements, USB 3.0 adds the new transfer rate referred to as '' ...
Gen 1 * Storage: 2x
SATA SATA (Serial AT Attachment) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the earlier Parallel ATA (PATA) standard to ...
and 2x
NVMe NVM Express (NVMe) or Non-Volatile Memory Host Controller Interface Specification (NVMHCIS) is an open, logical-device interface specification for accessing a computer's non-volatile storage media usually attached via PCI Express (PCIe) bus. The ...
or 2x PCI Express


Athlon (Zen-based)


Desktop


"Raven Ridge", 14 nm

*
Zen Zen ( zh, t=禪, p=Chán; ja, text= 禅, translit=zen; ko, text=선, translit=Seon; vi, text=Thiền) is a school of Mahayana Buddhism that originated in China during the Tang dynasty, known as the Chan School (''Chánzong'' 禪宗), and ...
CPU cores


"Picasso", 12 nm

*
Zen+ Zen+ is the codename for a computer processor microarchitecture by AMD. It is the successor to the first gen Zen microarchitecture, first released in April 2018, powering the second generation of Ryzen processors, known as Ryzen 2000 for mainstre ...
CPU cores


Mobile


"Raven Ridge", 14 nm

*
Zen Zen ( zh, t=禪, p=Chán; ja, text= 禅, translit=zen; ko, text=선, translit=Seon; vi, text=Thiền) is a school of Mahayana Buddhism that originated in China during the Tang dynasty, known as the Chan School (''Chánzong'' 禪宗), and ...
CPU cores


"Dalí", 14 nm

*
Zen Zen ( zh, t=禪, p=Chán; ja, text= 禅, translit=zen; ko, text=선, translit=Seon; vi, text=Thiền) is a school of Mahayana Buddhism that originated in China during the Tang dynasty, known as the Chan School (''Chánzong'' 禪宗), and ...
CPU cores


Athlon (Zen 2 based)


Mobile


"Mendocino", 6 nm

*
Zen 2 Zen 2 is a computer processor microarchitecture by AMD. It is the successor of AMD's Zen and Zen+ microarchitectures, and is fabricated on the 7 nanometer MOSFET node from TSMC. The microarchitecture powers the third generation of Ryzen proces ...
CPU cores * Fabrication process:
TSMC Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational corporation, multinational semiconductor contract manufacturing and design company. It is the world's most valuable semicon ...
6 nm FinFET * Includes integrated RDNA2 GPU * Athlon Gold 7220U * Athlon Silver 7120U


See also

*
List of AMD processors This article gives a list of AMD microprocessors, sorted by generation and release year. If applicable and openly known, the designation(s) of each processor's core (versions) is (are) listed in parentheses. For an overview over concrete product, y ...
* List of AMD Duron processors *
List of AMD Athlon XP processors The Athlon XP microprocessor from AMD is a seventh-generation 32-bit CPU targeted at the consumer market. Features overview Desktop CPU Athlon XP "Palomino" (Model 6, 180 nm) * CPU-ID: 6-6-0, 6-6-1, 6-6-2 * All models support: '' MMX, SSE, ...
*
List of AMD Athlon 64 processors The Athlon 64 microprocessor from Advanced Micro Devices (AMD) is an eighth-generation central processing unit (CPU). Athlon 64 is targeted at the consumer market. Features overview CPU features table Single-core desktop processors Athlon 6 ...
*
List of AMD Athlon X2 processors The AMD Athlon X2 processor family consists of processors based on both the Athlon 64 X2 and the Phenom processor families. The original Athlon X2 processors were low-power Athlon 64 X2 ''Brisbane'' processors, while newer processors released in ...
*
List of AMD Athlon II processors The AMD Athlon II family is a 64-bit microprocessor family from Advanced Micro Devices (AMD), based on the K10 microarchitecture. As with the Phenom II, it's an improved second generation of said microarchitecture. Desktop processors "''Zos ...
*
List of AMD Phenom processors The AMD Phenom family is a 64-bit microprocessor family from Advanced Micro Devices (AMD), based on the K10 microarchitecture. It includes the AMD Phenom II X6 hex-core series, Phenom X4 and Phenom II X4 quad-core series, Phenom X3 and Phenom II ...
*
List of AMD Opteron processors Opteron is the name of a central processing unit (CPU) family within the AMD64 line. Designed by Advanced Micro Devices (AMD) for the server market, Opteron competed with Intel's Xeon. The Opteron family is succeeded by the Zen-based Epyc, and Ry ...
*
List of AMD Sempron processors The Sempron is a name used for AMD's low-end CPUs, replacing the Duron processor. The name was introduced in 2004, and processors with this name continued to be available for the FM2/FM2+ socket in 2015. Features overview CPU features table Desk ...
*
List of AMD Ryzen processors The Advanced Micro Devices, AMD Ryzen family is an x86-64 microprocessor family from AMD, based on the Zen microarchitecture. The Ryzen lineup includes Ryzen 3, Ryzen 5, Ryzen 7, Ryzen 9, and Ryzen Threadripper with up to 64 cores. All consumer Ryz ...
*
List of Intel processors This generational list of Intel processors attempts to present all of Intel's processors from the pioneering 4-bit 4004 (1971) to the present high-end offerings. Concise technical data is given for each product. Latest 13th generation Cor ...
*
Table of AMD processors References See also * List of AMD microprocessors * List of AMD CPU microarchitectures * List of AMD mobile microprocessors * List of AMD Athlon microprocessors * List of AMD Athlon XP microprocessors * List of AMD Athlon 64 microprocesso ...


Notes

Note 1: Athlons use a
double data rate In computing, a computer bus operating with double data rate (DDR) transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition. The term toggle mode is used i ...
(DDR)
front-side bus A front-side bus (FSB) is a computer communication interface (bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between the ...
, (EV-6) meaning that the actual data transfer rate of the bus is twice its physical clock rate. The FSB's true data rate, 200 or 266 MT/s, is used in the tables, and the physical clock rates are 100 and 133 MHz, respectively. The multipliers in the tables above apply to the physical clock rate, not the data transfer rate.


References


External links


AMD technical documentation for Athlon
*

' AMD, 28 April 2008 {{AMD_processors *Athlon
AMD Athlon Athlon is the brand name applied to a series of x86-compatible microprocessors designed and manufactured by Advanced Micro Devices (AMD). The original Athlon (now called Athlon Classic) was the first seventh-generation x86 processor and the fi ...