I
2C (Inter-Integrated Circuit, ), alternatively known as I2C or IIC, is a
synchronous
Synchronization is the coordination of events to operate a system in unison. For example, the conductor of an orchestra keeps the orchestra synchronized or ''in time''. Systems that operate with all parts in synchrony are said to be synchronou ...
, multi-controller/multi-target (master/slave),
packet switched
In telecommunications, packet switching is a method of grouping data into '' packets'' that are transmitted over a digital network. Packets are made of a header and a payload. Data in the header is used by networking hardware to direct the pack ...
,
single-ended,
serial communication
In telecommunication and data transmission, serial communication is the process of sending data one bit at a time, sequentially, over a communication channel or computer bus. This is in contrast to parallel communication, where several bits are ...
bus
A bus (contracted from omnibus, with variants multibus, motorbus, autobus, etc.) is a road vehicle that carries significantly more passengers than an average car or van. It is most commonly used in public transport, but is also in use for cha ...
invented in 1982 by
Philips Semiconductors
NXP Semiconductors N.V. (NXP) is a Dutch semiconductor designer and manufacturer with headquarters in Eindhoven, Netherlands. The company employs approximately 31,000 people in more than 30 countries. NXP reported revenue of $11.06 billion in 2 ...
. It is widely used for attaching lower-speed peripheral
ICs to processors and
microcontroller
A microcontroller (MCU for ''microcontroller unit'', often also MC, UC, or μC) is a small computer on a single VLSI integrated circuit (IC) chip. A microcontroller contains one or more CPUs (processor cores) along with memory and programmable i ...
s in short-distance, intra-board communication.
Several competitors, such as
Siemens
Siemens AG ( ) is a German multinational conglomerate corporation and the largest industrial manufacturing company in Europe headquartered in Munich with branch offices abroad.
The principal divisions of the corporation are ''Industry'', '' ...
,
NEC
is a Japanese multinational information technology and electronics corporation, headquartered in Minato, Tokyo. The company was known as the Nippon Electric Company, Limited, before rebranding in 1983 as NEC. It provides IT and network soluti ...
,
Texas Instruments
Texas Instruments Incorporated (TI) is an American technology company headquartered in Dallas, Texas, that designs and manufactures semiconductors and various integrated circuits, which it sells to electronics designers and manufacturers globall ...
,
STMicroelectronics
STMicroelectronics N.V. commonly referred as ST or STMicro is a Dutch multinational corporation and technology company of French-Italian origin headquartered in Plan-les-Ouates near Geneva, Switzerland and listed on the French stock market. ST ...
,
Motorola
Motorola, Inc. () was an American Multinational corporation, multinational telecommunications company based in Schaumburg, Illinois, United States. After having lost $4.3 billion from 2007 to 2009, the company split into two independent p ...
,
Nordic Semiconductor
Nordic Semiconductor (formerly Nordic VLSI) is a fabless semiconductor company headquartered in Trondheim, Norway, and focused on low-power wireless communications devices.
Overview
The company specializes in ultra-low-power performance wireles ...
and
Intersil
Intersil is an American semiconductor company headquartered in Milpitas, California. As of February 24, 2017, Intersil is a subsidiary of Renesas. The previous Intersil was formed in August 1999 through the acquisition of the semiconductor busin ...
, have introduced compatible I
2C products to the market since the mid-1990s.
System Management Bus The System Management Bus (abbreviated to SMBus or SMB) is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with the power source for ON/OFF instru ...
(SMBus), defined by Intel in 1995, is a subset of I
2C, defining a stricter usage. One purpose of SMBus is to promote robustness and interoperability. Accordingly, modern I
2C systems incorporate some policies and rules from SMBus, sometimes supporting both I
2C and SMBus, requiring only minimal reconfiguration either by commanding or output pin use.
Applications
![I O Expander - MCP23008 (46357574392)](https://upload.wikimedia.org/wikipedia/commons/8/87/I_O_Expander_-_MCP23008_%2846357574392%29.jpg)
I
2C is appropriate for peripherals where simplicity and low manufacturing cost are more important than speed. Common applications of the I
2C bus are:
* Describing connectable devices via small ROM configuration tables to enable
plug and play
In computing, a plug and play (PnP) device or computer bus is one with a specification that facilitates the recognition of a hardware component in a system without the need for physical device configuration or user intervention in resolving resou ...
operation, such as in
serial presence detect
In computing, serial presence detect (SPD) is a standardized way to automatically access information about a memory module. Earlier 72-pin SIMMs included five pins that provided five bits of ''parallel presence detect'' (PPD) data, but the 168-pi ...
(SPD)
EEPROM
EEPROM (also called E2PROM) stands for electrically erasable programmable read-only memory and is a type of non-volatile memory used in computers, usually integrated in microcontrollers such as smart cards and remote keyless systems, or as a ...
s on
dual in-line memory module
A DIMM () (Dual In-line Memory Module), commonly called a RAM stick, comprises a series of dynamic random-access memory integrated circuits. These memory modules are mounted on a printed circuit board and designed for use in personal computers, ...
s (DIMMs), and
Extended Display Identification Data Extended Display Identification Data (EDID) and Enhanced EDID (E-EDID) are metadata formats for display devices to describe their capabilities to a video source (e.g. graphics card or set-top box). The data format is defined by a standard published ...
(EDID) for monitors via
VGA
Video Graphics Array (VGA) is a video display controller and accompanying de facto graphics standard, first introduced with the IBM PS/2 line of computers in 1987, which became ubiquitous in the PC industry within three years. The term can no ...
,
DVI
Digital Visual Interface (DVI) is a video display interface developed by the Digital Display Working Group (DDWG). The digital interface is used to connect a video source, such as a video display controller, to a display device, such as a comp ...
and
HDMI
High-Definition Multimedia Interface (HDMI) is a proprietary audio/video interface for transmitting uncompressed video data and compressed or uncompressed digital audio data from an HDMI-compliant source device, such as a display controller, ...
connectors.
* System management for PC systems via
SMBus The System Management Bus (abbreviated to SMBus or SMB) is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with the power source for ON/OFF instru ...
; SMBus pins are allocated in both conventional
PCI and
PCI Express
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
connectors.
* Accessing
real-time clock
A real-time clock (RTC) is an electronic device (most often in the form of an integrated circuit) that measures the passage of time.
Although the term often refers to the devices in personal computers, servers and embedded systems, RTCs are pr ...
s and
NVRAM
Non-volatile random-access memory (NVRAM) is random-access memory that retains data without applied power. This is in contrast to dynamic random-access memory (DRAM) and static random-access memory (SRAM), which both maintain data only for as lon ...
chips that keep user settings.
* Accessing low-speed
DACs and
ADCs.
* Changing backlight, contrast, hue, color balance settings etc in monitors (via
Display Data Channel
The Display Data Channel, or DDC, is a collection of protocols for digital communication between a computer display and a graphics adapter that enable the display to communicate its supported display modes to the adapter and that enable the com ...
).
* Changing sound volume in intelligent speakers.
* Controlling small (e.g.
feature phone
A feature phone (also spelled featurephone) is a type or class of mobile phone that retains the form factor of earlier generations of mobile telephones, typically with press-button based inputs and a small non-touch display. They tend to use an ...
)
LCD or
OLED
An organic light-emitting diode (OLED or organic LED), also known as organic electroluminescent (organic EL) diode, is a light-emitting diode (LED) in which the emissive electroluminescent layer is a film of organic compound that emits light i ...
displays.
* Reading hardware monitors and diagnostic sensors, e.g. a fan's speed.
* Turning on and off the power supply of system components.
A particular strength of I
2C is the capability of a
microcontroller
A microcontroller (MCU for ''microcontroller unit'', often also MC, UC, or μC) is a small computer on a single VLSI integrated circuit (IC) chip. A microcontroller contains one or more CPUs (processor cores) along with memory and programmable i ...
to control a network of device chips with just two
general-purpose I/O pins and software. Many other bus technologies used in similar applications, such as
Serial Peripheral Interface Bus
The Serial Peripheral Interface (SPI) is a synchronous serial communication interface specification used for short-distance communication, primarily in embedded systems. The interface was developed by Motorola in the mid-1980s and has become a ...
(SPI), require more pins and signals to connect multiple devices.
Revisions
Design
![I2C controller-target](https://upload.wikimedia.org/wikipedia/commons/0/04/I2C_controller-target.svg)
I
2C uses only two bidirectional
open-collector
An open collector is a common type of output found on many integrated circuits (IC), which behaves like a switch that is either connected to ground or disconnected. Instead of outputting a signal of a specific voltage or current, the output sig ...
or
open-drain
An open collector is a common type of output found on many integrated circuits (IC), which behaves like a switch that is either connected to ground or disconnected. Instead of outputting a signal of a specific voltage or current, the output sig ...
lines: serial data line (SDA) and serial clock line (SCL),
pulled up with
resistor
A resistor is a passive two-terminal electrical component that implements electrical resistance as a circuit element. In electronic circuits, resistors are used to reduce current flow, adjust signal levels, to divide voltages, bias active el ...
s.
Typical voltages used are +5 V or +3.3 V, although systems with other voltages are permitted.
The I
2C
reference design
Reference design refers to a technical blueprint of a system that is intended for others to copy. It contains the essential elements of the system; however, third parties may enhance or modify the design as required. When discussing computer desi ...
has a 7-bit
address space
In computing, an address space defines a range of discrete addresses, each of which may correspond to a network host, peripheral device, disk sector, a memory cell or other logical or physical entity.
For software programs to save and retrieve st ...
, with a rarely used 10-bit extension. Common I
2C bus speeds are the 100
kbit/s
In telecommunications, data-transfer rate is the average number of bits (bitrate), characters or symbols (baudrate), or data blocks per unit time passing through a communication link in a data-transmission system. Common data rate units are multi ...
''standard mode'' and the 400 kbit/s ''fast mode''. There is also a 10 kbit/s ''low-speed mode'', but arbitrarily low clock frequencies are also allowed. Later revisions of I
2C can host more nodes and run at faster speeds (400 kbit/s ''fast mode'', 1 Mbit/s ''fast mode plus'', 3.4
Mbit/s
In telecommunications, data-transfer rate is the average number of bits (bitrate), characters or symbols (baudrate), or data blocks per unit time passing through a communication link in a data-transmission system. Common data rate units are multi ...
''high-speed mode'', and 5
Mbit/s
In telecommunications, data-transfer rate is the average number of bits (bitrate), characters or symbols (baudrate), or data blocks per unit time passing through a communication link in a data-transmission system. Common data rate units are multi ...
''ultra-fast mode''). These speeds are more widely used on embedded systems than on PCs.
Note that the bit rates are quoted for the transfers between controller (master) and target (slave) without clock stretching or other hardware overhead. Protocol overheads include a target address and perhaps a register address within the target device, as well as per-byte ACK/NACK bits. Thus the actual transfer rate of user data is lower than those peak bit rates alone would imply. For example, if each interaction with a target inefficiently allows only 1 byte of data to be transferred, the data rate will be less than half the peak bit rate.
The number of nodes which can exist on a given I
2C bus is limited by the address space and also by the total bus
capacitance
Capacitance is the capability of a material object or device to store electric charge. It is measured by the change in charge in response to a difference in electric potential, expressed as the ratio of those quantities. Commonly recognized are ...
of 400
pF, which restricts practical communication distances to a few meters. The relatively high impedance and low noise immunity requires a common ground potential, which again restricts practical use to communication within the same PC board or small system of boards.
Reference design
The aforementioned reference design is a bus with a
clock
A clock or a timepiece is a device used to measure and indicate time. The clock is one of the oldest human inventions, meeting the need to measure intervals of time shorter than the natural units such as the day, the lunar month and the ...
(SCL) and data (SDA) lines with 7-bit addressing. The bus has two roles for nodes,
either controller (master) or target (slave):
* Controller (master) node: Node that generates the clock and initiates communication with targets (slaves).
* Target (slave) node: Node that receives the clock and responds when addressed by the controller (master).
The bus is a multi-controller bus, which means that any number of controller nodes can be present. Additionally, controller and target roles may be changed between messages (after a STOP is sent).
There may be four potential modes of operation for a given bus device, although most devices only use a single role and its two modes:
* Controller (master) transmit: Controller node is sending data to a target (slave).
* Controller (master) receive: Controller node is receiving data from a target (slave).
* Target (slave) transmit: Target node is sending data to the controller (master).
* Target (slave) receive: Target node is receiving data from the controller (master).
In addition to 0 and 1 data bits, the I
2C bus allows special START and STOP signals which act as message delimiters and are distinct from the data bits. (This is in contrast to the
start bit
Asynchronous serial communication is a form of serial communication in which the communicating endpoints' interfaces are not continuously synchronized by a common clock signal. Instead of a common synchronization signal, the data stream contai ...
s and
stop bit
Asynchronous serial communication is a form of serial communication in which the communicating endpoints' interfaces are not continuously synchronized by a common clock signal. Instead of a common synchronization signal, the data stream contai ...
s used in
asynchronous serial communication
Asynchronous serial communication is a form of serial communication in which the communicating endpoints' interfaces are not continuously synchronized by a common clock signal. Instead of a common synchronization signal, the data stream contai ...
, which are distinguished from data bits only by their timing.)
The controller is initially in controller transmit mode by sending a START followed by the 7-bit address of the target it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write (0) to or read (1) from the target.
If the target exists on the bus then it will respond with an
ACK bit (active low for acknowledged) for that address. The controller then continues in either transmit or receive mode (according to the read/write bit it sent), and the target continues in the complementary mode (receive or transmit, respectively).
The address and the data bytes are sent
most significant bit
In computing, bit numbering is the convention used to identify the bit positions in a binary number.
Bit significance and indexing
In computing, the least significant bit (LSB) is the bit position in a binary integer representing the binary 1 ...
first. The start condition is indicated by a high-to-low transition of SDA with SCL high; the stop condition is indicated by a low-to-high transition of SDA with SCL high. All other transitions of SDA take place with SCL low.
If the controller wishes to write to the target, then it repeatedly sends a byte with the target sending an ACK bit. (In this situation, the controller is in controller transmit mode, and the target is in target receive mode.)
If the controller wishes to read from the target, then it repeatedly receives a byte from the target, the controller sending an ACK bit after every byte except the last one. (In this situation, the controller is in controller receive mode, and the target is in target transmit mode.)
An I
2C transaction may consist of multiple messages. The controller terminates a message with a STOP condition if this is the end of the transaction or it may send another START condition to retain control of the bus for another message (a "combined format" transaction).
Message protocols
I
2C defines basic types of transactions, each of which begins with a START and ends with a STOP:
* Single message where a controller (master) writes data to a target (slave).
* Single message where a controller (master) reads data from a target (slave).
* Combined format, where a controller (master) issues at least two reads or writes to one or more targets (slaves).
In a combined transaction, each read or write begins with a START and the target address. The START conditions after the first are also called ''repeated START'' bits. Repeated STARTs are not preceded by STOP conditions, which is how targets know that the next message is part of the same transaction.
Any given target will only respond to certain messages, as specified in its product documentation.
Pure I
2C systems support arbitrary message structures.
SMBus The System Management Bus (abbreviated to SMBus or SMB) is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with the power source for ON/OFF instru ...
is restricted to nine of those structures, such as ''read word N'' and ''write word N'', involving a single target.
PMBus
The Power Management Bus (PMBus) is a variant of the System Management Bus (SMBus) which is targeted at digital management of power supplies. Like SMBus, it is a relatively slow speed two wire communications protocol based on I²C. Unlike either ...
extends SMBus with a ''Group'' protocol, allowing multiple such SMBus transactions to be sent in one combined message. The terminating STOP indicates when those grouped actions should take effect. For example, one PMBus operation might reconfigure three power supplies (using three different I
2C target addresses), and their new configurations would take effect at the same time: when they receive that STOP.
With only a few exceptions, neither I
2C nor SMBus define message semantics, such as the meaning of data bytes in messages. Message semantics are otherwise product-specific. Those exceptions include messages addressed to the I
2C ''general call'' address (0x00) or to the SMBus ''Alert Response Address''; and messages involved in the SMBus ''Address Resolution Protocol'' (ARP) for dynamic address allocation and management.
In practice, most targets adopt request-response control models, where one or more bytes following a write command are treated as a command or address. Those bytes determine how subsequent written bytes are treated or how the target responds on subsequent reads. Most SMBus operations involve single-byte commands.
Messaging example: 24C32 EEPROM
![Medion MD8910 - STMicroelectronics 24C08-8003](https://upload.wikimedia.org/wikipedia/commons/3/34/Medion_MD8910_-_STMicroelectronics_24C08-8003.jpg)
One specific example is the 24C32 type
EEPROM
EEPROM (also called E2PROM) stands for electrically erasable programmable read-only memory and is a type of non-volatile memory used in computers, usually integrated in microcontrollers such as smart cards and remote keyless systems, or as a ...
, which uses two request bytes that are called Address High and Address Low. (Accordingly, these EEPROMs are not usable by pure SMBus hosts, which support only single-byte commands or addresses.) These bytes are used for addressing bytes within the 32
kbit (or 4
kB) EEPROM address space. The same two-byte addressing is also used by larger EEPROMs, like the 24C512 which stores 512 kbits (or 64 kB). Writing data to and reading from these EEPROMs uses a simple protocol: the address is written, and then data is transferred until the end of the message. The data transfer part of the protocol can cause trouble on the SMBus, since the data bytes are not preceded by a count, and more than 32 bytes can be transferred at once. I
2C EEPROMs smaller than 32 kbit, like the 2 kbit 24C02, are often used on the SMBus with inefficient single-byte data transfers to overcome this problem.
A single message writes to the EEPROM. After the START, the controller sends the chip's bus address with the direction bit clear (''write''), then sends the two-byte address of data within the EEPROM and then sends data bytes to be written starting at that address, followed by a STOP. When writing multiple bytes, all the bytes must be in the same 32-byte page. While it is busy saving those bytes to memory, the EEPROM will not respond to further I
2C requests. (That is another incompatibility with SMBus: SMBus devices must always respond to their bus addresses.)
To read starting at a particular address in the EEPROM, a combined message is used. After a START, the controller first writes that chip's bus address with the direction bit clear (''write'') and then the two bytes of EEPROM data address. It then sends a (repeated) START and the EEPROM's bus address with the direction bit set (''read''). The EEPROM will then respond with the data bytes beginning at the specified EEPROM data address — a combined message: first a write, then a read. The controller issues an ACK after each read byte except the last byte, and then issues a STOP. The EEPROM increments the address after each data byte transferred; multi-byte reads can retrieve the entire contents of the EEPROM using one combined message.
Physical layer
![Iicrp](https://upload.wikimedia.org/wikipedia/commons/2/27/Iicrp.png)
At the
physical layer
In the seven-layer OSI model of computer networking, the physical layer or layer 1 is the first and lowest layer; The layer most closely associated with the physical connection between devices. This layer may be implemented by a PHY chip.
The ...
, both SCL and SDA lines are an
open-drain
An open collector is a common type of output found on many integrated circuits (IC), which behaves like a switch that is either connected to ground or disconnected. Instead of outputting a signal of a specific voltage or current, the output sig ...
(
MOSFET
The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which d ...
) or
open-collector
An open collector is a common type of output found on many integrated circuits (IC), which behaves like a switch that is either connected to ground or disconnected. Instead of outputting a signal of a specific voltage or current, the output sig ...
(
BJT
A bipolar junction transistor (BJT) is a type of transistor that uses both electrons and electron holes as charge carriers. In contrast, a unipolar transistor, such as a field-effect transistor, uses only one kind of charge carrier. A bipolar ...
) bus design, thus a
pull-up resistor
In electronic logic circuits, a pull-up resistor (PU) or pull-down resistor (PD) is a resistor used to ensure a known state for a signal. It is typically used in combination with components such as switches and transistors, which physically in ...
is needed for each line. A logic "0" is output by pulling the line to ground, and a logic "1" is output by letting the line float (output
high impedance
In electronics, high impedance means that a point in a circuit (a node) allows a relatively small amount of current through, per unit of applied voltage at that point. High impedance circuits are low current and potentially high voltage, whereas l ...
) so that the pull-up resistor pulls it high. A line is never actively driven high. This wiring allows multiple nodes to connect to the bus without short circuits from signal contention. High-speed systems (and some others) may use a
current source
A current source is an electronic circuit that delivers or absorbs an electric current which is independent of the voltage across it.
A current source is the dual of a voltage source. The term ''current sink'' is sometimes used for sources f ...
instead of a resistor to pull-up only SCL or both SCL and SDA, to accommodate higher bus capacitance and enable faster rise times.
An important consequence of this is that multiple nodes may be driving the lines simultaneously. If ''any'' node is driving the line low, it will be low. Nodes that are trying to transmit a logical one (i.e. letting the line float high) can detect this and conclude that another node is active at the same time.
When used on SCL, this is called ''clock stretching'' and is a flow-control mechanism for targets. When used on SDA, this is called
arbitration
Arbitration is a form of alternative dispute resolution (ADR) that resolves disputes outside the judiciary courts. The dispute will be decided by one or more persons (the 'arbitrators', 'arbiters' or 'arbitral tribunal'), which renders the ' ...
and ensures that there is only one transmitter at a time.
When idle, both lines are high. To start a transaction, SDA is pulled low while SCL remains high. It is illegal to transmit a stop marker by releasing SDA to float high again (although such a "void message" is usually harmless), so the next step is to pull SCL low.
Except for the start and stop signals, the SDA line only changes while the clock is low; transmitting a data bit consists of pulsing the clock line high while holding the data line steady at the desired level.
While SCL is low, the transmitter (initially the controller) sets SDA to the desired value and (after a small delay to let the value propagate) lets SCL float high. The controller then waits for SCL to actually go high; this will be delayed by the finite rise time of the SCL signal (the
RC time constant
The RC time constant, also called tau, the time constant (in seconds) of an RC circuit, is equal to the product of the circuit resistance (in ohms) and the circuit capacitance (in farads), i.e.
: \tau = RC econds
It is the time required to c ...
of the
pull-up resistor
In electronic logic circuits, a pull-up resistor (PU) or pull-down resistor (PD) is a resistor used to ensure a known state for a signal. It is typically used in combination with components such as switches and transistors, which physically in ...
and the
parasitic capacitance
Parasitic capacitance is an unavoidable and usually unwanted capacitance that exists between the parts of an electronic component or circuit simply because of their proximity to each other. When two electrical conductors at different voltages a ...
of the bus) and may be additionally delayed by a target's clock stretching.
Once SCL is high, the controller waits a minimum time (4 μs for standard-speed I
2C) to ensure that the receiver has seen the bit, then pulls it low again. This completes transmission of one bit.
After every 8 data bits in one direction, an "acknowledge" bit is transmitted in the other direction. The transmitter and receiver switch roles for one bit, and the original receiver transmits a single "0" bit (ACK) back. If the transmitter sees a "1" bit (NACK) instead, it learns that:
* (If controller transmitting to target) The target is unable to accept the data. No such target, command not understood, or unable to accept any more data.
* (If target transmitting to controller) The controller wishes the transfer to stop after this data byte.
Only the SDA line changes direction during acknowledge bits; the SCL is always controlled by the controller.
After the acknowledge bit, the clock line is low and the controller may do one of three things:
* Begin transferring another byte of data: the transmitter sets SDA, and the controller pulses SCL high.
* Send a "Stop": Set SDA low, let SCL go high, then let SDA go high. This releases the I
2C bus.
* Send a "Repeated start": Set SDA high, let SCL go high, then pull SDA low again. This starts a new I
2C bus message without releasing the bus.
Clock stretching using SCL
One of the more significant features of the I
2C protocol is clock stretching. An addressed target device may hold the clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The controller that is communicating with the target may not finish the transmission of the current bit, but must wait until the clock line actually goes high. If the target is clock-stretching, the clock line will still be low (because the connections are
open-drain
An open collector is a common type of output found on many integrated circuits (IC), which behaves like a switch that is either connected to ground or disconnected. Instead of outputting a signal of a specific voltage or current, the output sig ...
). The same is true if a second, slower, controller tries to drive the clock at the same time. (If there is more than one controller, all but one of them will normally lose arbitration.)
The controller must wait until it observes the clock line going high, and an additional minimal time (4 μs for standard 100 kbit/s I
2C) before pulling the clock low again.
Although the controller may also hold the SCL line low for as long as it desires (this is not allowed since Rev. 6 of the protocol – subsection 3.1.1), the term "clock stretching" is normally used only when targets do it. Although in theory any clock pulse may be stretched, generally it is the intervals before or after the acknowledgment bit which are used. For example, if the target is a
microcontroller
A microcontroller (MCU for ''microcontroller unit'', often also MC, UC, or μC) is a small computer on a single VLSI integrated circuit (IC) chip. A microcontroller contains one or more CPUs (processor cores) along with memory and programmable i ...
, its I
2C interface could stretch the clock after each byte, until the software decides whether to send a positive acknowledgment or a NACK.
Clock stretching is the only time in I
2C where the target drives SCL. Many targets do not need to clock stretch and thus treat SCL as strictly an input with no circuitry to drive it. Some controllers, such as those found inside custom
ASICs may not support clock stretching; often these devices will be labeled as a "two-wire interface" and not I
2C.
To ensure a minimal bus
throughput
Network throughput (or just throughput, when in context) refers to the rate of message delivery over a communication channel, such as Ethernet or packet radio, in a communication network. The data that these messages contain may be delivered ov ...
,
SMBus The System Management Bus (abbreviated to SMBus or SMB) is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with the power source for ON/OFF instru ...
places limits on how far clocks may be stretched. Hosts and targets adhering to those limits cannot block access to the bus for more than a short time, which is not a guarantee made by pure I
2C systems.
Arbitration using SDA
Every controller monitors the bus for start and stop bits and does not start a message while another controller is keeping the bus busy. However, two controllers may start transmission at about the same time; in this case, arbitration occurs. Target transmit mode can also be arbitrated, when a controller addresses multiple targets, but this is less common. In contrast to protocols (such as
Ethernet
Ethernet () is a family of wired computer networking technologies commonly used in local area networks (LAN), metropolitan area networks (MAN) and wide area networks (WAN). It was commercially introduced in 1980 and first standardized in 198 ...
) that use random back-off delays before issuing a retry, I
2C has a deterministic arbitration policy. Each transmitter checks the level of the data line (SDA) and compares it with the levels it expects; if they do not match, that transmitter has lost arbitration and drops out of this protocol interaction.
If one transmitter sets SDA to 1 (not driving a signal) and a second transmitter sets it to 0 (pull to ground), the result is that the line is low. The first transmitter then observes that the level of the line is different from that expected and concludes that another node is transmitting. The first node to notice such a difference is the one that loses arbitration: it stops driving SDA. If it is a controller, it also stops driving SCL and waits for a STOP; then it may try to reissue its entire message. In the meantime, the other node has not noticed any difference between the expected and actual levels on SDA and therefore continues transmission. It can do so without problems because so far the signal has been exactly as it expected; no other transmitter has disturbed its message.
If the two controllers are sending a message to two different targets, the one sending the lower target address always "wins" arbitration in the address stage. Since the two controllers may send messages to the same target address, and addresses sometimes refer to multiple targets, arbitration must sometimes continue into the data stages.
Arbitration occurs very rarely, but is necessary for proper multi-controller support. As with clock stretching, not all devices support arbitration. Those that do, generally label themselves as supporting "multi-controller" communication.
One case which must be handled carefully in multi-controller I
2C implementations is that of the controllers talking to each other. One controller may lose arbitration to an incoming message, and must change its role from controller to target in time to acknowledge its own address.
In the extremely rare case that two controllers simultaneously send identical messages, both will regard the communication as successful, but the target will only see one message. For this reason, when a target can be accessed by multiple controllers, every command recognized by the target either must be
idempotent
Idempotence (, ) is the property of certain operations in mathematics and computer science whereby they can be applied multiple times without changing the result beyond the initial application. The concept of idempotence arises in a number of pl ...
or must be guaranteed never to be issued by two controllers at the same time. (For example, a command which is issued by only one controller need not be idempotent, nor is it necessary for a specific command to be idempotent when some mutual exclusion mechanism ensures that only one controller can be caused to issue that command at any given time.)
Arbitration in SMBus
While I
2C only arbitrates between controllers,
SMBus The System Management Bus (abbreviated to SMBus or SMB) is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with the power source for ON/OFF instru ...
uses arbitration in three additional contexts, where multiple targets respond to the controller, and one gets its message through.
* Although conceptually a single-controller bus, a target device that supports the "host notify protocol" acts as a controller to perform the notification. It seizes the bus and writes a 3-byte message to the reserved "SMBus Host" address (0x08), passing its address and two bytes of data. When two targets try to notify the host at the same time, one of them will lose arbitration and need to retry.
* An alternative target notification system uses the separate SMBALERT# signal to request attention. In this case, the host performs a 1-byte read from the reserved "SMBus Alert Response Address" (0x0C), which is a kind of broadcast address. All alerting targets respond with a data bytes containing their own address. When the target successfully transmits its own address (winning arbitration against others) it stops raising that interrupt. In both this and the preceding case, arbitration ensures that one target's message will be received, and the others will know they must retry.
* SMBus also supports an "address resolution protocol", wherein devices return a 16-byte "universal device ID" (
UDID
UDID is an acronym for Unique Device Identifier. The UDID is a feature of Apple's devices running iOS, tvOS, watchOS, and macOS. It is a unique identifier that is calculated from different hardware values, such as the ECID. It is sent to Apple ...
). Multiple devices may respond; the one with the lowest UDID will win arbitration and be recognized.
Arbitration in PMBus
PMBus
The Power Management Bus (PMBus) is a variant of the System Management Bus (SMBus) which is targeted at digital management of power supplies. Like SMBus, it is a relatively slow speed two wire communications protocol based on I²C. Unlike either ...
version 1.3 extends the SMBus alert response protocol in its "zone read" protocol. Targets may be grouped into "zones", and all targets in a zone may be addressed to respond, with their responses masked (omitting unwanted information), inverted (so wanted information is sent as 0 bits, which win arbitration), or reordered (so the most significant information is sent first). Arbitration ensures that the highest priority response is the one first returned to the controller.
PMBus reserves I
2C addresses 0x28 and 0x37 for zone reads and writes, respectively.
Differences between modes
There are several possible operating modes for I
2C communication. All are compatible in that the 100 kbit/s ''standard mode'' may always be used, but combining devices of different capabilities on the same bus can cause issues, as follows:
* ''Fast mode'' is highly compatible and simply tightens several of the timing parameters to achieve 400 kbit/s speed. ''Fast mode'' is widely supported by I
2C target devices, so a controller may use it as long as it knows that the bus capacitance and pull-up strength allow it.
* ''Fast mode plus'' achieves up to 1 Mbit/s using more powerful (20 mA) drivers and pull-ups to achieve faster rise and fall times. Compatibility with ''standard'' and ''fast mode'' devices (with 3 mA pull-down capability) can be achieved if there is some way to reduce the strength of the pull-ups when talking to them.
* ''High speed mode'' (3.4 Mbit/s) is compatible with normal I
2C devices on the same bus, but requires the controller have an active pull-up on the clock line which is enabled during high speed transfers. The first data bit is transferred with a normal open-drain rising clock edge, which may be stretched. For the remaining seven data bits, and the ACK, the controller drives the clock high at the appropriate time and the target may not stretch it. All high-speed transfers are preceded by a single-byte "controller code" at fast or standard speed. This code serves three purposes:
*# it tells high-speed target devices to change to high-speed timing rules,
*# it ensures that fast or normal speed devices will not try to participate in the transfer (because it does not match their address), and
*# because it identifies the controller (there are eight controller codes, and each controller must use a different one), it ensures that arbitration is complete before the high-speed portion of the transfer, and so the high-speed portion need not make allowances for that ability.
* ''Ultra-Fast mode'' is essentially a write-only I
2C subset, which is incompatible with other modes except in that it is easy to add support for it to an existing I
2C interface hardware design. Only one controller is permitted, and it actively drives data lines at all times to achieve a 5 Mbit/s transfer rate. Clock stretching, arbitration, read transfers, and acknowledgements are all omitted. It is mainly intended for animated
LED display
A LED display is a flat panel display that uses an array of light-emitting diodes as pixels for a video display. Their brightness allows them to be used outdoors where they are visible in the sun for store signs and billboards. In recent ...
s where a transmission error would only cause an inconsequential brief visual
glitch
A glitch is a short-lived fault in a system, such as a transient fault that corrects itself, making it difficult to troubleshoot. The term is particularly common in the computing and electronics industries, in circuit bending, as well as among ...
. The resemblance to other I
2C bus modes is limited to:
** the start and stop conditions are used to delimit transfers,
** I
2C addressing allows multiple target devices to share the bus without
SPI bus style target select signals, and
** a ninth clock pulse is sent per byte transmitted marking the position of the unused acknowledgement bits.
Some of the vendors provide a so called non-standard ''Turbo mode'' with a speed up to 1.4 Mbit/s.
In all modes, the clock frequency is controlled by the controller(s), and a longer-than-normal bus may be operated at a slower-than-nominal speed by
underclocking
Underclocking, also known as downclocking, is modifying a computer or electronic circuit's timing settings to run at a lower clock rate than is specified. Underclocking is used to reduce a computer's power consumption, increase battery life, red ...
.
Circuit interconnections
![16bit ADC Card](https://upload.wikimedia.org/wikipedia/commons/9/9d/16bit_ADC_Card.jpg)
I
2C is popular for interfacing peripheral circuits to prototyping systems, such as the
Arduino
Arduino () is an open-source hardware and software company, project, and user community that designs and manufactures single-board microcontrollers and microcontroller kits for building digital devices. Its hardware products are licensed unde ...
and
Raspberry Pi
Raspberry Pi () is a series of small single-board computers (SBCs) developed in the United Kingdom by the Raspberry Pi Foundation in association with Broadcom. The Raspberry Pi project originally leaned towards the promotion of teaching basic ...
. I
2C does not employ a standardized connector, however, board designers have created various wiring schemes for I
2C interconnections. To minimize the possible damage due to plugging 0.1-inch headers in backwards, some developers have suggested using alternating signal and power connections of the following wiring schemes: (GND, SCL, VCC, SDA) or (VCC, SDA, GND, SCL).
The vast majority of applications use I
2C in the way it was originally designed—peripheral ICs directly wired to a processor on the same printed circuit board, and therefore over relatively short distances of less than , without a connector. However using a differential driver, an alternate version of I
2C can communicate up to 20 meters (possibly over 100 meters) over
CAT5 or other cable.
Several standard connectors carry I
2C signals. For example, the
UEXT
Universal EXTension (UEXT) is a connector layout which includes power and three serial buses: Asynchronous, I2C, and SPI. The connector layout was specified by Olimex Ltd and declared an open-project that is royalty-free.
Physical characteris ...
connector carries I
2C;
the 10-pin iPack connector carries I
2C; the
6P6C
A modular connector is a type of electrical connector for cords and cables of electronic devices and appliances, such as in computer networking, telecommunication equipment, and audio headsets.
Modular connectors were originally developed for ...
Lego Mindstorms NXT connector carries I
2C; a few people use the 8P8C connectors and CAT5 cable normally used for
Ethernet physical layer
The physical-layer specifications of the Ethernet family of computer network standards are published by the Institute of Electrical and Electronics Engineers (IEEE), which defines the electrical or optical properties and the transfer speed ...
to instead carry differential-encoded I
2C signals or boosted single-ended I
2C signals; and every
HDMI
High-Definition Multimedia Interface (HDMI) is a proprietary audio/video interface for transmitting uncompressed video data and compressed or uncompressed digital audio data from an HDMI-compliant source device, such as a display controller, ...
and most
DVI
Digital Visual Interface (DVI) is a video display interface developed by the Digital Display Working Group (DDWG). The digital interface is used to connect a video source, such as a video display controller, to a display device, such as a comp ...
and
VGA connector
The Video Graphics Array (VGA) connector is a standard connector used for computer video output. Originating with the 1987 IBM PS/2 and its VGA graphics system, the 15-pin connector went on to become ubiquitous on PCs, as well as many monitors ...
s carry
DDC2 data over I
2C.
Buffering and multiplexing
When there are many I
2C devices in a system, there can be a need to include bus
buffers or
multiplexer
In electronics, a multiplexer (or mux; spelled sometimes as multiplexor), also known as a data selector, is a device that selects between several analog or digital input signals and forwards the selected input to a single output line. The sel ...
s to split large bus segments into smaller ones. This can be necessary to keep the capacitance of a bus segment below the allowable value or to allow multiple devices with the same address to be separated by a multiplexer. Many types of multiplexers and buffers exist and all must take into account the fact that I
2C lines are specified to be bidirectional. Multiplexers can be implemented with analog switches, which can tie one segment to another. Analog switches maintain the bidirectional nature of the lines but do not isolate the capacitance of one segment from another or provide buffering capability.
Buffers can be used to isolate capacitance on one segment from another and/or allow I
2C to be sent over longer cables or traces. Buffers for bi-directional lines such as I
2C must use one of several schemes for preventing latch-up. I
2C is open-drain, so buffers must drive a low on one side when they see a low on the other. One method for preventing latch-up is for a buffer to have carefully selected input and output levels such that the output level of its driver is higher than its input threshold, preventing it from triggering itself. For example, a buffer may have an input threshold of 0.4 V for detecting a low, but an output low level of 0.5 V. This method requires that all other devices on the bus have thresholds which are compatible and often means that multiple buffers implementing this scheme cannot be put in series with one another.
Alternatively, other types of buffers exist that implement current amplifiers or keep track of the state (i.e. which side drove the bus low) to prevent latch-up. The state method typically means that an unintended pulse is created during a hand-off when one side is driving the bus low, then the other drives it low, then the first side releases (this is common during an I
2C acknowledgement).
Sharing SCL between multiple buses
When having a single controller, it is possible to have multiple I
2C buses share the same SCL line. The packets on each bus are either sent one after the other or at the same time. This is possible, because the communication on each bus can be subdivided in alternating short periods with high SCL followed by short periods with low SCL. And the clock can be stretched, if one bus needs more time in one state.
Advantages are using targets devices with the same address at the same time and saving connections or a faster throughput by using several data lines at the same time.
Line state table
These tables show the various atomic states and bit operations that may occur during an I
2C message.
Addressing structure
7-bit addressing
10-bit addressing
Reserved addresses in 7-bit address space
Two groups of addresses are reserved for special functions:
*
*
SMBus reserves some additional addresses. In particular,
0001 000
is reserved for the SMBus host, which may be used by controller-capable devices,
0001 100
is the "SMBus alert response address" which is polled by the host after an out-of-band interrupt, and
1100 001
is the default address which is initially used by devices capable of dynamic address assignment.
This leaves a total of 107 unreserved 7-bit addresses in common between I
2C, SMBus, and PMBus.
Non-reserved addresses in 7-bit address space
Although MSB 1111 is reserved for Device ID and 10-bit target (slave) addressing, it is also used by VESA
DDC display dependent devices such as
pointing device
A pointing device is a human interface device that allows a user to input spatial (i.e., continuous and multi-dimensional) data to a computer. CAD systems and graphical user interfaces (GUI) allow the user to control and provide data to ...
s.
Transaction format
An I
2C ''transaction'' consists of one or more ''messages''. Each message begins with a start symbol, and the transaction ends with a stop symbol. Start symbols after the first, which begin a message but not a transaction, are referred to as ''repeated start'' symbols.
Each message is a read or a write. A transaction consisting of a single message is called either a read or a write transaction. A transaction consisting of multiple messages is called a combined transaction. The most common form of the latter is a write message providing intra-device address information, followed by a read message.
Many I
2C devices do not distinguish between a combined transaction and the same messages sent as separate transactions, but not all. The device ID protocol requires a single transaction; targets are forbidden from responding if they observe a stop symbol. Configuration, calibration or self-test modes which cause the target to respond unusually are also often automatically terminated at the end of a transaction.
Timing diagram
# Data transfer is initiated with a ''start'' condition (S) signalled by SDA being pulled low while SCL stays high.
# SCL is pulled low, and SDA sets the first data bit level while keeping SCL low (during blue bar time).
# The data is sampled (received) when SCL rises for the first bit (B1). For a bit to be valid, SDA must not change between a rising edge of SCL and the subsequent falling edge (the entire green bar time).
# This process repeats, SDA transitioning while SCL is low, and the data being read while SCL is high (B2 through Bn).
# The final bit is followed by a clock pulse, during which SDA is pulled low in preparation for the ''stop'' bit.
# A ''stop'' condition (P) is signalled when SCL rises, followed by SDA rising.
In order to avoid false marker detection, there is a minimum delay between the SCL falling edge and changing SDA, and between changing SDA and the SCL rising edge. Note that an I
2C message containing data bits (including acknowledges) contains clock pulses.
Software Design
I
2C lends itself to a "bus driver" software design. Software for attached devices is written to call a "bus driver" that handles the actual low-level I
2C hardware. This permits the driver code for attached devices to port easily to other hardware, including a bit-banging design.
Example of bit-banging the I2C protocol
Below is an example of
bit-banging the I
2C protocol as an I
2C controller (master). The example is written in
pseudo
The prefix pseudo- (from Greek ψευδής, ''pseudes'', "false") is used to mark something that superficially appears to be (or behaves like) one thing, but is something else. Subject to context, ''pseudo'' may connote coincidence, imitation, ...
C. It illustrates all of the I
2C features described before (clock stretching, arbitration, start/stop bit, ack/nack).
// Hardware-specific support functions that MUST be customized:
#define I2CSPEED 100
void I2C_delay(void);
bool read_SCL(void); // Return current level of SCL line, 0 or 1
bool read_SDA(void); // Return current level of SDA line, 0 or 1
void set_SCL(void); // Do not drive SCL (set pin high-impedance)
void clear_SCL(void); // Actively drive SCL signal low
void set_SDA(void); // Do not drive SDA (set pin high-impedance)
void clear_SDA(void); // Actively drive SDA signal low
void arbitration_lost(void);
bool started = false; // global data
void i2c_start_cond(void)
void i2c_stop_cond(void)
// Write a bit to I2C bus
void i2c_write_bit(bool bit)
// Read a bit from I2C bus
bool i2c_read_bit(void)
// Write a byte to I2C bus. Return 0 if ack by the target.
bool i2c_write_byte(bool send_start,
bool send_stop,
unsigned char byte)
// Read a byte from I2C bus
unsigned char i2c_read_byte(bool nack, bool send_stop)
void I2C_delay(void)
Operating system support
* In
AmigaOS
AmigaOS is a family of proprietary native operating systems of the Amiga and AmigaOne personal computers. It was developed first by Commodore International and introduced with the launch of the first Amiga, the Amiga 1000, in 1985. Early version ...
one can use the i2c.resource component for AmigaOS 4.x and
MorphOS
MorphOS is an AmigaOS-like computer operating system (OS). It is a mixed proprietary and open source OS produced for the Pegasos PowerPC (PPC) processor based computer, PowerUP accelerator equipped Amiga computers, and a series of Freescale dev ...
3.x or the shared library ''i2c.library'' by Wilhelm Noeker for older systems.
*
Arduino
Arduino () is an open-source hardware and software company, project, and user community that designs and manufactures single-board microcontrollers and microcontroller kits for building digital devices. Its hardware products are licensed unde ...
developers can use the "Wire" library.
*
Maximite Maximite Microcomputer is a Microchip PIC32 microcontroller-based microcomputer. Originally designed as a hobby kit, the Maximite was introduced in a three-part article in Silicon Chip magazine in autumn of 2011 by Australian designer Geoff Graha ...
supports I
2C communications natively as part of its MMBasic.
*
PICAXE uses the i2c and hi2c commands.
*
eCos
The Embedded Configurable Operating System (eCos) is a free and open-source real-time operating system intended for embedded systems and applications which need only one process with multiple threads. It is designed to be customizable to prec ...
supports I
2C for several hardware architectures.
*
ChibiOS/RT
ChibiOS/RT is a compact and fast real-time operating system supporting multiple architectures and released under a mix of the GNU General Public License version 3 (GPL3) and the Apache License 2.0 (depending on module). It is developed by Giovann ...
supports I
2C for several hardware architectures.
*
FreeBSD
FreeBSD is a free and open-source Unix-like operating system descended from the Berkeley Software Distribution (BSD), which was based on Research Unix. The first version of FreeBSD was released in 1993. In 2005, FreeBSD was the most popular ...
,
NetBSD
NetBSD is a free and open-source Unix operating system based on the Berkeley Software Distribution (BSD). It was the first open-source BSD descendant officially released after 386BSD was forked. It continues to be actively developed and is a ...
and
OpenBSD
OpenBSD is a security-focused, free and open-source, Unix-like operating system based on the Berkeley Software Distribution (BSD). Theo de Raadt created OpenBSD in 1995 by forking NetBSD 1.0. According to the website, the OpenBSD project em ...
also provide an I
2C framework, with support for a number of common controllers and sensors.
** Since
OpenBSD
OpenBSD is a security-focused, free and open-source, Unix-like operating system based on the Berkeley Software Distribution (BSD). Theo de Raadt created OpenBSD in 1995 by forking NetBSD 1.0. According to the website, the OpenBSD project em ...
3.9 (released ), a central subsystem probes all possible sensor chips at once during boot, using an
ad hoc
Ad hoc is a Latin phrase meaning literally 'to this'. In English, it typically signifies a solution for a specific purpose, problem, or task rather than a generalized solution adaptable to collateral instances. (Compare with ''a priori''.)
Com ...
weighting scheme and a local caching function for reading register values from the I
2C targets;
this makes it possible to probe sensors on
general-purpose off-the-shelf
Off-the-shelf may refer to:
* Commercial off-the-shelf, a phrase in computing and industrial supply terminology
* Government off-the-shelf
* Ready-to-wear
* Shelf corporation, a type of company
* Off the Shelf Festival, a festival of writing and r ...
i386/amd64 hardware during boot without any configuration by the user nor a noticeable probing delay; the matching procedures of the individual drivers then only has to rely on a string-based "friendly-name" for matching;
as a result, most I
2C sensor drivers are automatically enabled by default in applicable architectures without ill effects on stability; individual sensors, both I
2C and otherwise, are exported to the userland through the sysctl
hw.sensors
The hw.sensors framework is a kernel-level hardware sensors framework originating from OpenBSD, which uses the sysctl kernel interface as the transport layer between the kernel and the userland. , the framework is used by over a hundred devi ...
framework. , OpenBSD has over two dozen device drivers on I
2C that export some kind of a sensor through the
hw.sensors
The hw.sensors framework is a kernel-level hardware sensors framework originating from OpenBSD, which uses the sysctl kernel interface as the transport layer between the kernel and the userland. , the framework is used by over a hundred devi ...
framework, and the majority of these drivers are fully enabled by default in i386/amd64
GENERIC
kernels of OpenBSD.
** In
NetBSD
NetBSD is a free and open-source Unix operating system based on the Berkeley Software Distribution (BSD). It was the first open-source BSD descendant officially released after 386BSD was forked. It continues to be actively developed and is a ...
, over two dozen I
2C target devices exist that feature hardware monitoring sensors, which are accessible through the sysmon
envsys
The envsys framework is a kernel-level hardware monitoring sensors framework in NetBSD. , the framework is used by close to 85 device drivers to export various environmental monitoring sensors, as evidenced by references of the sysmon_envsys_ ...
framework as
property list
In the macOS, iOS, NeXTSTEP, and GNUstep programming frameworks, property list files are files that store serialized objects. Property list files use the filename extension .plist, and thus are often referred to as p-list files.
Property lis ...
s. On general-purpose hardware, each driver has to do its own probing, hence all drivers for the I
2C targets are disabled by default in NetBSD in
GENERIC
i386/amd64 builds.
* In
Linux
Linux ( or ) is a family of open-source Unix-like operating systems based on the Linux kernel, an operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically packaged as a Linux distribution, which ...
, I
2C is handled with a device driver for the specific device, and another for the I
2C (or
SMBus The System Management Bus (abbreviated to SMBus or SMB) is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with the power source for ON/OFF instru ...
) adapter to which it is connected. Hundreds of such drivers are part of current Linux kernel releases.
* In
Mac OS X
macOS (; previously OS X and originally Mac OS X) is a Unix operating system developed and marketed by Apple Inc. since 2001. It is the primary operating system for Apple's Mac (computer), Mac computers. Within the market of ...
, there are about two dozen I
2C kernel extensions that communicate with sensors for reading voltage, current, temperature, motion, and other physical status.
* In
Microsoft Windows
Windows is a group of several proprietary graphical operating system families developed and marketed by Microsoft. Each family caters to a certain sector of the computing industry. For example, Windows NT for consumers, Windows Server for serv ...
, I
2C is implemented by the respective device drivers of much of the industry's available hardware. For
HID embedded/
SoC devices, Windows 8 and later have an integrated I²C bus driver.
* In
Windows CE
Windows Embedded Compact, formerly Windows Embedded CE, Windows Powered and Windows CE, is an operating system subfamily developed by Microsoft as part of its Windows Embedded family of products.
Unlike Windows Embedded Standard, which is base ...
, I
2C is implemented by the respective device drivers of much of the industry's available hardware.
* Unison OS, a POSIX RTOS for IoT, supports I
2C for several MCU and MPU hardware architectures.
* In
RISC OS
RISC OS is a computer operating system originally designed by Acorn Computers Ltd in Cambridge, England. First released in 1987, it was designed to run on the ARM chipset, which Acorn had designed concurrently for use in its new line of Archim ...
, I
2C is provided with a generic I
2C interface from the IO controller and supported from the OS module system
* In
Sinclair QDOS
QDOS is the multitasking operating system found on the Sinclair QL personal computer and its clones. It was designed by Tony Tebby whilst working at Sinclair Research, as an in-house alternative to 68K/OS, which was later cancelled by Sinclair ...
and
Minerva
Minerva (; ett, Menrva) is the Roman goddess of wisdom, justice, law, victory, and the sponsor of arts, trade, and strategy. Minerva is not a patron of violence such as Mars, but of strategic war. From the second century BC onward, the Roma ...
QL operating systems
An operating system (OS) is system software that manages computer hardware, software resources, and provides common services for computer programs.
Time-sharing operating systems schedule tasks for efficient use of the system and may also inc ...
I
2C is supported by a set of extensions provided by TF Services.
Development tools
When developing or troubleshooting systems using I
2C, visibility at the level of hardware signals can be important.
Host adapters
There are a number of I
2C host adapter hardware solutions for making a I
2C controller or target connection to host computers, running
Linux
Linux ( or ) is a family of open-source Unix-like operating systems based on the Linux kernel, an operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically packaged as a Linux distribution, which ...
,
Mac or
Windows
Windows is a group of several proprietary graphical operating system families developed and marketed by Microsoft. Each family caters to a certain sector of the computing industry. For example, Windows NT for consumers, Windows Server for serv ...
. Most options are
USB
Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply (interfacing) between computers, peripherals and other computers. A broad ...
-to-I
2C adapters. Not all of them require proprietary drivers or
APIs.
Protocol analyzers
I
2C protocol analyzers are tools that sample an I
2C bus and decode the electrical signals to provide a higher-level view of the data being transmitted on the bus.
Logic analyzers
When developing and/or troubleshooting the I
2C bus, examination of hardware signals can be very important.
Logic analyzers
A logic analyzer is an electronic instrument that captures and displays multiple signals from a digital system or digital circuit. A logic analyzer may convert the captured data into timing diagrams, protocol decodes, state machine traces, ass ...
are tools that collect, analyze, decode, and store signals, so people can view the high-speed waveforms at their leisure. Logic analyzers display time stamps of each signal level change, which can help find protocol problems. Most logic analyzers have the capability to decode bus signals into high-level protocol data and show ASCII data.
Limitations
On low-power systems, the pull-up resistors can use more power than the entire rest of the design combined. On these, the resistors are often powered by a switchable voltage source, such as a DIO from a microcontroller. The pull-ups also limit the speed of the bus and have a small additional cost. Therefore, some designers are turning to other serial buses, e.g.
I3C or
SPI, that do not need pull-ups.
The assignment of target addresses is a weakness of I
2C. Seven bits is too few to prevent address collisions between the many thousands of available devices. What alleviates the issue of address collisions between different vendors and also allows to connect to several identical devices is that manufacturers dedicate pins that can be used to set the target address to one of a few address options per device. Two or three pins is typical, and with many devices, there are three or more wiring options per address pin.
[Linear Technology's LTC4151](_blank)
has two pins for address selection, each of which can be tied high or low or left unconnected, offering 9 different addresses.[Maxim's MAX7314](_blank)
has a single pin for address selection to be tied high or low or connected to SDA or SCL, offering 4 different addresses.[TI's UCD9224](_blank)
uses two ADC channels discriminating twelve levels each to select any valid 7-bit address.
10-bit I
2C addresses are not yet widely used, and many host operating systems do not support them. Neither is the complex SMBus "ARP" scheme for dynamically assigning addresses (other than for PCI cards with SMBus presence, for which it is required).
Automatic bus configuration is a related issue. A given address may be used by a number of different protocol-incompatible devices in various systems, and hardly any device types can be detected at runtime. For example,
0x51
may be used by a 24LC02 or 24C32
EEPROM
EEPROM (also called E2PROM) stands for electrically erasable programmable read-only memory and is a type of non-volatile memory used in computers, usually integrated in microcontrollers such as smart cards and remote keyless systems, or as a ...
, with incompatible addressing; or by a PCF8563
RTC, which cannot reliably be distinguished from either (without changing device state, which might not be allowed). The only reliable configuration mechanisms available to hosts involve out-of-band mechanisms such as tables provided by system firmware, which list the available devices. Again, this issue can partially be addressed by ARP in SMBus systems, especially when vendor and product identifiers are used; but that has not really caught on. The Rev. 3 version of the I
2C specification adds a device ID mechanism.
I
2C supports a limited range of speeds. Hosts supporting the multi-megabit speeds are rare. Support for the Fm+ 1 Mbit/s speed is more widespread, since its electronics are simple variants of what is used at lower speeds. Many devices do not support the 400 kbit/s speed (in part because SMBus does not yet support it). I
2C nodes implemented in software (instead of dedicated hardware) may not even support the 100 kbit/s speed; so the whole range defined in the specification is rarely usable. All devices must at least partially support the highest speed used or they may spuriously detect their device address.
Devices are allowed to stretch clock cycles to suit their particular needs, which can starve bandwidth needed by faster devices and increase latencies when talking to other device addresses. Bus capacitance also places a limit on the transfer speed, especially when current sources are not used to decrease signal rise times.
Because I
2C is a shared bus, there is the potential for any device to have a fault and hang the entire bus. For example, if any device holds the SDA or SCL line low, it prevents the controller from sending START or STOP commands to reset the bus. Thus it is common for designs to include a reset signal that provides an external method of resetting the bus devices. However many devices do not have a dedicated reset pin, forcing the designer to put in circuitry to allow devices to be power-cycled if they need to be reset.
Because of these limits (address management, bus configuration, potential faults, speed), few I
2C bus segments have even a dozen devices. It is common for systems to have several such segments. One might be dedicated to use with high-speed devices, for low-latency power management. Another might be used to control a few devices where latency and throughput are not important issues; yet another segment might be used only to read EEPROM chips describing add-on cards (such as the
SPD
The Social Democratic Party of Germany (german: Sozialdemokratische Partei Deutschlands, ; SPD, ) is a centre-left social democratic political party in Germany. It is one of the major parties of contemporary Germany.
Saskia Esken has been t ...
standard used with DRAM sticks).
Derivative technologies
I
2C is the basis for the
ACCESS.bus, the
VESA
VESA (), formally known as Video Electronics Standards Association, is an American technical standards organization for computer display standards. The organization was incorporated in California in July 1989To retrieve the information, searc ...
Display Data Channel
The Display Data Channel, or DDC, is a collection of protocols for digital communication between a computer display and a graphics adapter that enable the display to communicate its supported display modes to the adapter and that enable the com ...
(DDC) interface, the
System Management Bus The System Management Bus (abbreviated to SMBus or SMB) is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with the power source for ON/OFF instru ...
(SMBus),
Power Management Bus
The Power Management Bus (PMBus) is a variant of the System Management Bus (SMBus) which is targeted at digital management of power supplies. Like SMBus, it is a relatively slow speed two wire communications protocol based on I²C. Unlike either o ...
(PMBus) and the Intelligent Platform Management Bus (IPMB, one of the protocols of
IPMI). These variants have differences in voltage and clock frequency ranges, and may have
interrupt lines.
High-availability
High availability (HA) is a characteristic of a system which aims to ensure an agreed level of operational performance, usually uptime, for a higher than normal period.
Modernization has resulted in an increased reliance on these systems. Fo ...
systems (
AdvancedTCA
Advanced Telecommunications Computing Architecture (ATCA or AdvancedTCA) is the largest specification effort in the history of the PCI Industrial Computer Manufacturers Group (PICMG), with more than 100 companies participating. Known as AdvancedTC ...
,
MicroTCA MicroTCA (short for ''Micro Telecommunications Computing Architecture'', also: μTCA) is a modular, open standard, created and maintained by the PCI Industrial Computer Manufacturers Group (PICMG). It provides the electrical, mechanical, thermal an ...
) use 2-way redundant I
2C for shelf management. Multi-controller I
2C capability is a requirement in these systems.
TWI (Two-Wire Interface) or TWSI (Two-Wire Serial Interface) is essentially the same bus implemented on various system-on-chip processors from
Atmel
Atmel Corporation was a creator and manufacturer of semiconductors before being subsumed by Microchip Technology in 2016. Atmel was founded in 1984. The company focused on embedded systems built around microcontrollers. Its products included micr ...
and other vendors. Vendors use the name TWI, even though I
2C is not a registered trademark as of 2014-11-07. Trademark protection only exists for the respective logo (see upper right corner), and patents on I
2C have now lapsed. According to
Microchip Technology
Microchip Technology Inc. is a publicly-listed American corporation that manufactures microcontroller, mixed-signal, analog and Flash-IP integrated circuits. Its products include microcontrollers ( PIC, dsPIC, AVR and SAM), Serial EEPROM ...
, TWI and I2C have a few differences. One of them is that TWI does not support START byte.
In some cases, use of the term "two-wire interface" indicates incomplete implementation of the I
2C specification. Not supporting arbitration or clock stretching is one common limitation, which is still useful for a single controller communicating with simple targets that never stretch the clock.
MIPI I3C sensor interface standard (I3C) is a development of I
2C, under development in 2017.
See also
*
List of network buses
*
ACCESS.bus
*
I3C
*
Power Management Bus
The Power Management Bus (PMBus) is a variant of the System Management Bus (SMBus) which is targeted at digital management of power supplies. Like SMBus, it is a relatively slow speed two wire communications protocol based on I²C. Unlike either o ...
*
System Management Bus The System Management Bus (abbreviated to SMBus or SMB) is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with the power source for ON/OFF instru ...
*
UEXT
Universal EXTension (UEXT) is a connector layout which includes power and three serial buses: Asynchronous, I2C, and SPI. The connector layout was specified by Olimex Ltd and declared an open-project that is royalty-free.
Physical characteris ...
Connector
*
VESA Display Data Channel
References
Further reading
* (248 pages)
* (314 pages)
External links
Official I2C Specification Rev 6 (free)- NXP
Detailed I2C Introduction & PrimerI2C Pullup Resistor Calculation- TI
Effects of Varying I2C Pullup Resistors (Scope Captures of 5V I2C with 9 Different Pullup Resistances)
{{DEFAULTSORT:I2c
Serial buses