The zEC12

microprocessor A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circu ...

(''zEnterprise EC12'' or just ''z12'') is a chip made by IBM for their zEnterprise EC12 and zEnterprise BC12

mainframe computer A mainframe computer, informally called a mainframe or big iron, is a computer used primarily by large organizations for critical applications like bulk data processing for tasks such as censuses, industry and consumer statistics, enterpris ...

s, announced on August 28, 2012. It is manufactured at the

East Fishkill, New York East Fishkill is a town on the southern border of Dutchess County, New York, United States. The population was 29,707 at the 2020 census. The town was once the eastern portion of the town of Fishkill. Hudson Valley Research Park is located in ...

fabrication plant (previously owned by IBM but production will continue for ten years by new owner

GlobalFoundries GlobalFoundries Inc. (GF or GloFo) is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, ...

). The processor began shipping in the fall of 2012. IBM stated that it was the world's fastest microprocessor and is about 25% faster than its predecessor the z196.IBMs Mainframe zEC12 mit 5,5 GHz schnellen Prozessoren
/ref>IBM embiggens iron with System zEnterprise EC12 mainframe
/ref>

Description

The chip measures 597.24 mm² and consists of 2.75 billion

transistor upright=1.4, gate (G), body (B), source (S) and drain (D) terminals. The gate is separated from the body by an insulating layer (pink). A transistor is a semiconductor device used to Electronic amplifier, amplify or electronic switch, switch e ...

s fabricated in IBM's 32 nm

CMOS Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", ) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFE ...

silicon on insulator

fabrication process Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuit (IC) chips such as modern computer processors, microcontrollers, and memory chips such as NAND flash and DRAM that are p ...

, supporting speeds of 5.5

GHz The hertz (symbol: Hz) is the unit of frequency in the International System of Units (SI), equivalent to one event (or cycle) per second. The hertz is an SI derived unit whose expression in terms of SI base units is s−1, meaning that one he ...

, the highest clock speed CPU ever produced for commercial sale.IBM zEnterprise EC12 Technical Introduction
/ref> The processor implements the CISC

z/Architecture z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), is IBM's 64-bit complex instruction set computer (CISC) instruction set architecture, implemented by its mainframe computers. IBM introduced its first z/Architecture ...

with a superscalar, out-of-order

pipeline Pipeline may refer to: Electronics, computers and computing * Pipeline (computing), a chain of data-processing stages or a CPU optimization found on ** Instruction pipelining, a technique for implementing instruction-level parallelism within a s ...

and some new

instructions Instruction or instructions may refer to: Computing * Instruction, one operation of a processor within a computer architecture instruction set * Computer program, a collection of instructions Music * Instruction (band), a 2002 rock band from Ne ...

mainly related to transactional execution. The cores have numerous other enhancements such as better

branch prediction In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g., an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow ...

, out of order execution and one dedicated co-processor for compression and cryptography. The instruction pipeline has 15 to 17 stages; the instruction queue can hold 40 instructions; and up to 90 instructions can be "in flight". It has six cores, each with a private 64 KB L1 instruction cache, a private 96 KB L1 data cache, a private 1 MB

L2 cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, whic ...

instruction cache, and a private 1 MB L2 data cache. In addition, there is a 48 MB shared L3 cache implemented in eDRAM and controlled by two on-chip L3 cache controllers. There's also an additional shared L1 cache used for compression and cryptography operations. Each core has six RISC-like execution units, including two integer units, two load-store units, one binary

floating point unit Floating may refer to: * a type of dental work performed on horse teeth * use of an isolation tank * the guitar-playing technique where chords are sustained rather than scratched * ''Floating'' (play), by Hugh Hughes * Floating (psychological ...

and one

decimal floating point Decimal floating-point (DFP) arithmetic refers to both a representation and operations on decimal floating-point numbers. Working directly with decimal (base-10) fractions can avoid the rounding errors that otherwise typically occur when convert ...

unit. The zEC12 chip can decode three instructions and execute seven operations in a single clock cycle. Attached to each core is a special co-processor accelerator unit; in the previous z CPU there were two shared by all four cores. The zEC12 chip has on board multi-channel DDR3 RAM

memory controller The memory controller is a digital circuit that manages the flow of data going to and from the computer's main memory. A memory controller can be a separate chip or integrated into another chip, such as being placed on the same die or as an int ...

supporting a

RAID Raid, RAID or Raids may refer to: Attack * Raid (military), a sudden attack behind the enemy's lines without the intention of holding ground * Corporate raid, a type of hostile takeover in business * Panty raid, a prankish raid by male college ...

like configuration to recover from memory faults. The zEC12 also includes two GX bus controllers for accessing host channel adapters and peripherals.

Shared Cache

Even though each chip has 48 MB L3 cache shared by the 6 cores and other on-die facilities for

symmetric multiprocessing Symmetric multiprocessing or shared-memory multiprocessing (SMP) involves a multiprocessor computer hardware and software architecture where two or more identical processors are connected to a single, shared main memory, have full access to all ...

(SMP), there are 2 dedicated companion chips called the ''Shared Cache'' (SC) that each adds 192 MB off-die

L4 cache A CPU cache is a hardware cache In computing, a cache ( ) is a hardware or software component that stores data so that future requests for that data can be served faster; the data stored in a cache might be the result of an earlier computation ...

for a total of 384 MB L4 cache. L4 cache is shared by all processors in the book. The SC chips are manufactured on the same process as the zEC12 processor chips, measures 28.4 x 23.9 mm and have 3.3 billion transistors each.IBM zEnterprise EC12 Technical Guide
/ref>

Multi-chip module

The zEnterprise System EC12 uses

multi-chip module A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or "pins") where multiple integrated circuits (ICs or "chips"), semiconductor dies and/or other discrete components are in ...

s (MCMs) which allows for six zEC12 chips to be on a single module. Each MCM has two shared cache chips allowing processors on the MCM to be connected with 40 GB/s links. One zEC12 chip draws in the region of 300 W and the MCM is cooled by a liquid cooling mechanism capable of 1800 W. The different models of the zEnterprise System have a different number of active cores. To accomplish this, some processors in each MCM may have its fifth and/or sixth core disabled.

References

{{DEFAULTSORT:Ibm zEC12 (Microprocessor) Computer-related introductions in 2012 zEC12 zEC12 zEC12