Asynchronous circuit (clockless or self-timed circuit)
is a
sequential
In mathematics, a sequence is an enumerated collection of objects in which repetitions are allowed and order matters. Like a set, it contains members (also called ''elements'', or ''terms''). The number of elements (possibly infinite) is called t ...
digital logic
A logic gate is an idealized or physical device implementing a Boolean function, a logical operation performed on one or more Binary number, binary inputs that produces a single binary output. Depending on the context, the term may refer to an id ...
circuit that does not use a global
clock circuit
A clock generator is an electronic oscillator that produces a clock signal for use in synchronizing a circuit's operation. The signal can range from a simple symmetrical square wave to more complex arrangements. The basic parts that all clock ge ...
or
signal
In signal processing, a signal is a function that conveys information about a phenomenon. Any quantity that can vary over space or time can be used as a signal to share messages between observers. The ''IEEE Transactions on Signal Processing'' ...
generator to synchronize its components.
Instead, the components are driven by a handshaking circuit which indicates a completion of a set of instructions. Handshaking works by simple data transfer
protocols
Protocol may refer to:
Sociology and politics
* Protocol (politics), a formal agreement between nation states
* Protocol (diplomacy), the etiquette of diplomacy and affairs of state
* Etiquette, a code of personal behavior
Science and technology
...
. Many synchronous circuits were developed in early 1950s as part of bigger
asynchronous system
The primary focus of this article is asynchronous control in digital electronic systems. In a synchronous system, operations (instructions, calculations, logic, etc.) are coordinated by one, or more, centralized clock signals. An asynchronous ...
s (e.g.
ORDVAC
The ORDVAC (''Ordnance Discrete Variable Automatic Computer)'', is an early computer built by the University of Illinois for the Ballistic Research Laboratory at Aberdeen Proving Ground. A successor to the ENIAC (along with EDVAC built earlier). ...
). Asynchronous circuits and theory surrounding is a part of several steps in
integrated circuit design
Integrated circuit design, or IC design, is a sub-field of electronics engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic component ...
, a field of
digital electronics
Digital electronics is a field of electronics involving the study of digital signals and the engineering of devices that use or produce them. This is in contrast to analog electronics and analog signals.
Digital electronic circuits are usual ...
engineering.
Asynchronous circuits are contrasted with
synchronous circuit
In digital electronics, a synchronous circuit is a digital circuit in which the changes in the state of memory elements are synchronized by a clock signal. In a sequential digital logic circuit, data are stored in memory devices called flip-fl ...
s, in which changes to the signal values in the circuit are triggered by repetitive pulses called a
clock signal
In electronics and especially synchronous digital circuits, a clock signal (historically also known as ''logic beat'') oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits.
A clock sign ...
. Most digital devices today use synchronous circuits. However asynchronous circuits have a potential to be much faster, have a lower level of power consumption, electromagnetic interference, and better modularity in large systems. Asynchronous circuits are an active area of research in
digital logic design.
It was not until the 1990s when viability of the asynchronous circuits was shown by real-life commercial products.
Overview
All
digital logic
A logic gate is an idealized or physical device implementing a Boolean function, a logical operation performed on one or more Binary number, binary inputs that produces a single binary output. Depending on the context, the term may refer to an id ...
circuits can be divided into
combinational logic
In automata theory, combinational logic (also referred to as time-independent logic or combinatorial logic) is a type of digital logic which is implemented by Boolean circuits, where the output is a pure function of the present input only. This i ...
, in which the output signals depend only on the current input signals, and
sequential logic
In automata theory, sequential logic is a type of logic circuit whose output depends on the present value of its input signals and on the sequence of past inputs, the input history. This is in contrast to ''combinational logic'', whose output i ...
, in which the output depends both on current input and on past inputs. In other words, sequential logic is combinational logic with
memory
Memory is the faculty of the mind by which data or information is encoded, stored, and retrieved when needed. It is the retention of information over time for the purpose of influencing future action. If past events could not be remembered, ...
. Virtually all practical digital devices require sequential logic. Sequential logic can be divided into two types, synchronous logic and asynchronous logic.
Synchronous circuits
In
synchronous logic circuits, an
electronic oscillator
An electronic oscillator is an electronic circuit that produces a periodic, oscillation, oscillating electronic signal, often a sine wave or a square wave or a triangle wave. Oscillation, Oscillators convert direct current (DC) from a power supp ...
generates a repetitive series of equally spaced pulses called the ''
clock signal
In electronics and especially synchronous digital circuits, a clock signal (historically also known as ''logic beat'') oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits.
A clock sign ...
''. The clock signal is supplied to all the components of the IC. E.g. the flip-flops only flips when triggered by the
edge
Edge or EDGE may refer to:
Technology Computing
* Edge computing, a network load-balancing system
* Edge device, an entry point to a computer network
* Adobe Edge, a graphical development application
* Microsoft Edge, a web browser developed by ...
of the clock pulse, so changes to the logic signals throughout the circuit begin at the same time and at regular intervals. The output of all memory elements in a circuit is called the ''
state
State may refer to:
Arts, entertainment, and media Literature
* ''State Magazine'', a monthly magazine published by the U.S. Department of State
* ''The State'' (newspaper), a daily newspaper in Columbia, South Carolina, United States
* ''Our S ...
'' of the circuit. The state of a synchronous circuit changes only on the clock pulse. The changes in signal require a certain amount of time to propagate through the combinational logic gates of the circuit. This time is called a
propagation delay
Propagation delay is the time duration taken for a signal to reach its destination. It can relate to networking, electronics or physics. ''Hold time'' is the minimum interval required for the logic level to remain on the input after triggering e ...
.
As of 2021, timing of modern synchronous ICs takes significant engineering efforts and sophisticated
design automation tools.
Designers have to ensure that clock arrival is not faulty. With the ever-growing size and complexity of ICs (e.g.
ASICs) it's a challenging task.
In huge circuits, signals sent over clock distribution network often end up at different times at different parts.
This problem is widely known as "
clock skew Clock skew (sometimes called timing skew) is a phenomenon in synchronous digital circuit systems (such as computer systems) in which the same sourced clock signal arrives at different components at different times due to gate or, in more advanced s ...
".
The maximum possible clock rate is capped by the logic path with the longest propagation delay, called the critical path. Because of that the paths that may operate quickly are idle most of the time. Widely distributed clock network dissipates a lot of useful power and must run whether the circuit is receiving inputs or not.
Because of this level of complexity in all dimensions the synchronous circuits testing and debugging takes over half of its development time.
Asynchronous circuits
The asynchronous circuits do not need a global clock, and the state of the circuit changes as soon as the inputs change. The local functional blocks may be still employed but the ''
clock skew Clock skew (sometimes called timing skew) is a phenomenon in synchronous digital circuit systems (such as computer systems) in which the same sourced clock signal arrives at different components at different times due to gate or, in more advanced s ...
'' problem still can be tolerated.
Since asynchronous circuits do not have to wait for a clock pulse to begin processing inputs, they can operate faster. Their speed is theoretically limited only by the
propagation delay
Propagation delay is the time duration taken for a signal to reach its destination. It can relate to networking, electronics or physics. ''Hold time'' is the minimum interval required for the logic level to remain on the input after triggering e ...
s of the logic gates and other elements.
However, asynchronous circuits are more difficult to design and subject to problems not found in synchronous circuits. This is because the resulting state of an asynchronous circuit can be sensitive to the relative arrival times of inputs at gates. If transitions on two inputs arrive at almost the same time, the circuit can go into the wrong state depending on slight differences in the propagation delays of the gates.
This is called a
race condition
A race condition or race hazard is the condition of an electronics, software, or other system where the system's substantive behavior is dependent on the sequence or timing of other uncontrollable events. It becomes a bug when one or more of t ...
. In synchronous circuits this problem is less severe because race conditions can only occur due to inputs from outside the synchronous system, called ''asynchronous inputs''.
Although some fully asynchronous digital systems have been built (see below), today asynchronous circuits are typically used in a few critical parts of otherwise synchronous systems where speed is at a premium, such as signal processing circuits.
Theoretical foundation
The original theory of asynchronous circuits was created by
David E. Muller
David Eugene Muller (November 2, 1924 – April 27, 2008) was an American mathematician and computer scientist. He was a professor of mathematics and computer science at the University of Illinois (1953–92), after which he became an emeritu ...
in mid-1950s. This theory was presented later in the well-known book "Switching Theory" by Raymond Miller.
The term "asynchronous logic" is used to describe a variety of design styles, which use different assumptions about circuit properties. These vary from the
bundled delay Software bundle may refer to:
* Pre-installed software
* Bundled software
* Software suite
A software suite (also known as an application suite) is a collection of computer programs (application software, or programming software) of related func ...
model – which uses "conventional" data processing elements with completion indicated by a locally generated delay model – to
delay-insensitive
A delay-insensitive circuit is a type of asynchronous circuit which performs a digital logic operation often within a computing processor chip. Instead of using clock signals or other global control signals, the sequencing of computation in dela ...
design – where arbitrary delays through circuit elements can be accommodated. The latter style tends to yield circuits which are larger than bundled data implementations, but which are insensitive to layout and parametric variations and are thus "correct by design".
Asynchronous logic
Asynchronous logic is the
logic
Logic is the study of correct reasoning. It includes both formal and informal logic. Formal logic is the science of deductively valid inferences or of logical truths. It is a formal science investigating how conclusions follow from premises ...
required for the design of asynchronous digital systems. These function without a
clock signal
In electronics and especially synchronous digital circuits, a clock signal (historically also known as ''logic beat'') oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits.
A clock sign ...
and so individual logic elements cannot be relied upon to have a discrete true/false state at any given time.
Boolean (two valued) logic is inadequate for this and so extensions are required. Karl Fant developed a theoretical treatment of this in his work ''Logically determined design'' in 2005 which used
four-valued logic
In logic, a four-valued logic is any logic with four truth values. Several types of four-valued logic have been advanced.
Belnap
Nuel Belnap considered the challenge of question answering by computer in 1975. Noting human fallibility, he was conc ...
with
''null'' and ''intermediate'' being the additional values. This architecture is important because it is
quasi-delay-insensitive
In digital logic design, an asynchronous circuit is quasi delay-insensitive (QDI) when it operates correctly, independent of gate and wire delay with the weakest exception necessary to be turing-complete.
Overview
Pros
* Robust to process varia ...
. Scott Smith and Jia Di developed an ultra-low-power variation of Fant's Null Convention Logic that incorporates
multi-threshold CMOS Multi-threshold CMOS (MTCMOS) is a variation of CMOS chip technology which has transistors with multiple threshold voltages (Vth) in order to optimize delay or power. The Vth of a MOSFET is the gate voltage where an inversion layer forms at the in ...
. This variation is termed Multi-threshold Null Convention Logic (MTNCL), or alternatively Sleep Convention Logic (SCL).
Vadim Vasyukevich developed a different approach based upon a new logical operation which he called ''venjunction''. This takes into account not only the current value of an element,
but also its history.
Petri nets
Petri net
A Petri net, also known as a place/transition (PT) net, is one of several mathematical modeling languages for the description of distributed systems. It is a class of discrete event dynamic system. A Petri net is a directed bipartite graph that ...
s are an attractive and powerful model for reasoning about asynchronous circuits (see
Subsequent models of concurrency). A particularly useful type of interpreted Petri nets, called
Signal Transition Graphs Signal Transition Graphs (STGs) are typically used in electronic engineering and computer engineering to describe dynamic behaviour of asynchronous circuits, for the purposes of their analysis or synthesis.
Main definitions and applications
Info ...
(STGs), was proposed independently in 1985 by Leonid Rosenblum and Alex Yakovlev and Tam-Anh Chu. Since then, STGs have been studied extensively in theory and practice, which has led to the development of popular software tools for analysis and synthesis of asynchronous control circuits, such as Petrify and Workcraft.
Subsequent to Petri nets other models of concurrency have been developed that can model asynchronous circuits including the
Actor model
The actor model in computer science is a mathematical model of concurrent computation that treats ''actor'' as the universal primitive of concurrent computation. In response to a message it receives, an actor can: make local decisions, create more ...
and
process calculi
In computer science, the process calculi (or process algebras) are a diverse family of related approaches for formally modelling concurrent systems. Process calculi provide a tool for the high-level description of interactions, communications, and ...
.
Benefits
A variety of advantages have been demonstrated by asynchronous circuits. Both
quasi-delay-insensitive
In digital logic design, an asynchronous circuit is quasi delay-insensitive (QDI) when it operates correctly, independent of gate and wire delay with the weakest exception necessary to be turing-complete.
Overview
Pros
* Robust to process varia ...
(QDI) circuits (generally agreed to be the most "pure" form of asynchronous logic that retains computational universality) and less pure forms of asynchronous circuitry which use timing constraints for higher performance and lower area and power present several advantages.
* Robust and cheap handling of
metastability
In chemistry and physics, metastability denotes an intermediate Energy level, energetic state within a dynamical system other than the system's ground state, state of least energy.
A ball resting in a hollow on a slope is a simple example of me ...
of
arbiters.
* Average-case performance: an average-case time (delay) of operation is not limited to the worst-case completion time of component (gate, wire, block etc.) as it is in synchronous circuits. This results in better latency and throughput performance. Examples include ''speculative completion'' which has been applied to design parallel prefix adders faster than synchronous ones, and a high-performance double-precision floating point adder which outperforms leading synchronous designs.
**
Early completion
Early completion is a property of some classes of asynchronous circuit. It means that the output of a electrical network, circuit may be available as soon as sufficient inputs have arrived to allow it to be determined. For example, if all of the i ...
: the output may be generated ahead of time, when result of input processing is predictable or irrelevant.
**Inherent elasticity: variable number of data items may appear in pipeline inputs at any time (pipeline means a cascade of linked functional blocks). This contributes to high performance while gracefully handling variable input and output rates due to unclocked pipeline stages (functional blocks) delays (congestions may still be possible however and input-output gates delay should be also taken into account).
**No need for timing-matching between functional blocks either. Though given different delay models (predictions of gate/wire delay times) this depends on actual approach of asynchronous circuit implementation.
**Freedom from the ever-worsening difficulties of distributing a high-
fan-out
In digital electronics, the fan-out is the number of gate inputs driven by the output of another single logic gate.
In most designs, logic gates are connected to form more complex circuits. While no logic gate input can be fed by more than one ...
, timing-sensitive clock signal.
**Circuit speed adapts to changing temperature and voltage conditions rather than being locked at the speed mandated by worst-case assumptions.
* Lower, on-demand power consumption;
zero standby power consumption. In 2005
Epson
Seiko Epson Corporation, or simply known as Epson, is a Japanese multinational electronics company and one of the world's largest manufacturers of computer printers and information- and imaging-related equipment. Headquartered in Suwa, Nagano, ...
has reported 70% lower power consumption compared to synchronous design. Also, clock drivers can be removed which can significantly reduce power consumption. However, when using certain encodings, asynchronous circuits may require more area, adding similar power overhead if the underlying process has poor leakage properties (for example, deep submicrometer processes used prior to the introduction of
high-κ dielectric The term high-κ dielectric refers to a material with a high dielectric constant (κ, kappa), as compared to silicon dioxide. High-κ dielectrics are used in semiconductor manufacturing processes where they are usually used to replace a silicon dio ...
s).
**No need for power-matching between local asynchronous functional domains of circuitry. Synchronous circuits tend to draw a large amount of current right at the clock edge and shortly thereafter. The number of nodes switching (and hence, the amount of current drawn) drops off rapidly after the clock edge, reaching zero just before the next clock edge. In an asynchronous circuit, the switching times of the nodes does not correlated in this manner, so the current draw tends to be more uniform and less bursty.
* Robustness toward transistor-to-transistor variability in the manufacturing transfer process (which is one of the most serious problems facing the semiconductor industry as dies shrink), variations of voltage supply, temperature, and fabrication process parameters.
* Less severe
electromagnetic interference
Electromagnetic interference (EMI), also called radio-frequency interference (RFI) when in the radio frequency spectrum, is a disturbance generated by an external source that affects an electrical circuit by electromagnetic induction, electros ...
(EMI). Synchronous circuits create a great deal of EMI in the frequency band at (or very near) their clock frequency and its harmonics; asynchronous circuits generate EMI patterns which are much more evenly spread across the spectrum.
* Design modularity (reuse), improved noise immunity and electromagnetic compatibility. Asynchronous circuits are more tolerant to process variations and external voltage fluctuations.
Disadvantages
* Area overhead caused by additional logic implementing handshaking. In some cases an asynchronous design may require up to double the resources (area, circuit speed, power consumption) of a synchronous design, due to addition of completion detection and design-for-test circuits.
* Compared to a synchronous design, as of the 1990s and early 2000s not many people are trained or experienced in the design of asynchronous circuits.
* Synchronous designs are inherently easier to test and debug than asynchronous designs. However, this position is disputed by Fant, who claims that the apparent simplicity of synchronous logic is an artifact of the mathematical models used by the common design approaches.
*
Clock gating
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation, by removing the clock signal when the circuit is not in use or ignores clock signal. Clock gating saves power by pruning the clock tree, ...
in more conventional synchronous designs is an approximation of the asynchronous ideal, and in some cases, its simplicity may outweigh the advantages of a fully asynchronous design.
* Performance (speed) of asynchronous circuits may be reduced in architectures that require input-completeness (more complex data path).
* Lack of dedicated, asynchronous design-focused commercial
EDA EDA or Eda may refer to:
Computing
* Electronic design automation
* Enterprise Desktop Alliance, a computer technology consortium
* Enterprise digital assistant
* Estimation of distribution algorithm
* Event-driven architecture
* Exploratory ...
tools.
As of 2006 the situation was slowly improving, however.
Communication
There are several ways to create asynchronous communication channels that can be classified by their protocol and data encoding.
Protocols
There are two widely used protocol families which differ in the way communications are encoded:
*two-phase handshake ( two-phase protocol, Non-Return-to-Zero (NRZ) encoding, or transition signalling): Communications are represented by any wire transition; transitions from 0 to 1 and from 1 to 0 both count as communications.
*four-phase handshake (a.k.a. four-phase protocol, or Return-to-Zero (RZ) encoding): Communications are represented by a wire transition followed by a reset; a transition sequence from 0 to 1 and back to 0 counts as single communication.
![2 and 4 phase handshakes](https://upload.wikimedia.org/wikipedia/commons/c/c1/2_and_4_phase_handshakes.svg)
Despite involving more transitions per communication, circuits implementing four-phase protocols are usually faster and simpler than two-phase protocols because the signal lines return to their original state by the end of each communication. In two-phase protocols, the circuit implementations would have to store the state of the signal line internally.
Note that these basic distinctions do not account for the wide variety of protocols. These protocols may encode only requests and acknowledgements or also encode the data, which leads to the popular multi-wire data encoding. Many other, less common protocols have been proposed including using a single wire for request and acknowledgment, using several significant voltages, using only pulses or balancing timings in order to remove the latches.
Data encoding
There are two widely used data encodings in asynchronous circuits: bundled-data encoding and multi-rail encoding
Another common way to encode the data is to use multiple wires to encode a single digit: the value is determined by the wire on which the event occurs. This avoids some of the delay assumptions necessary with bundled-data encoding, since the request and the data are not separated anymore.
Bundled-data encoding
Bundled-data encoding uses one wire per bit of data with a request and an acknowledge signal; this is the same encoding used in synchronous circuits without the restriction that transitions occur on a clock edge. The request and the acknowledge are sent on separate wires with one of the above protocols. These circuits usually assume a bounded delay model with the completion signals delayed long enough for the calculations to take place.
In operation, the sender signals the availability and validity of data with a request. The receiver then indicates completion with an acknowledgement, indicating that it is able to process new requests. That is, the request is bundled with the data, hence the name "bundled-data".
Bundled-data circuits are often referred to as micropipelines, whether they use a two-phase or four-phase protocol, even if the term was initially introduced for two-phase bundled-data.
Multi-rail encoding
Multi-rail encoding uses multiple wires without a one-to-one relationship between bits and wires and a separate acknowledge signal. Data availability is indicated by the transitions themselves on one or more of the data wires (depending on the type of multi-rail encoding) instead of with a request signal as in the bundled-data encoding. This provides the advantage that the data communication is delay-insensitive. Two common multi-rail encodings are one-hot and dual rail. The one-hot (a.k.a. 1-of-n) encoding represents a number in base n with a communication on one of the n wires. The dual-rail encoding uses pairs of wires to represent each bit of the data, hence the name "dual-rail"; one wire in the pair represents the bit value of 0 and the other represents the bit value of 1. For example, a dual-rail encoded two bit number will be represented with two pairs of wires for four wires in total. During a data communication, communications occur on one of each pair of wires to indicate the data's bits. In the general case, an m
n encoding represent data as m words of base n.
Dual-rail encoding
Dual-rail encoding with a four-phase protocol is the most common and is also called ''three-state encoding'', since it has two valid states (10 and 01, after a transition) and a reset state (00). Another common encoding, which leads to a simpler implementation than one-hot, two-phase dual-rail is ''four-state encoding'', or level-encoded dual-rail, and uses a data bit and a parity bit to achieve a two-phase protocol.
Asynchronous CPU
Asynchronous CPUs are one of
several ideas for radically changing CPU design.
Unlike a conventional processor, a clockless processor (asynchronous CPU) has no central clock to coordinate the progress of data through the pipeline.
Instead, stages of the CPU are coordinated using logic devices called "pipeline controls" or "FIFO sequencers." Basically, the pipeline controller clocks the next stage of logic when the existing stage is complete. In this way, a central clock is unnecessary. It may actually be even easier to implement high performance devices in asynchronous, as opposed to clocked, logic:
* components can run at different speeds on an asynchronous CPU; all major components of a clocked CPU must remain synchronized with the central clock;
* a traditional CPU cannot "go faster" than the expected worst-case performance of the slowest stage/instruction/component. When an asynchronous CPU completes an operation more quickly than anticipated, the next stage can immediately begin processing the results, rather than waiting for synchronization with a central clock. An operation might finish faster than normal because of attributes of the data being processed (e.g., multiplication can be very fast when multiplying by 0 or 1, even when running code produced by a naive compiler), or because of the presence of a higher voltage or bus speed setting, or a lower ambient temperature, than 'normal' or expected.
Asynchronous logic proponents believe these capabilities would have these benefits:
* lower power dissipation for a given performance level, and
* highest possible execution speeds.
The biggest disadvantage of the clockless CPU is that most
CPU design
Processor design is a subfield of computer engineering and electronics engineering (fabrication) that deals with creating a processor, a key component of computer hardware.
The design process involves choosing an instruction set and a certain exec ...
tools assume a clocked CPU (i.e., a
synchronous circuit
In digital electronics, a synchronous circuit is a digital circuit in which the changes in the state of memory elements are synchronized by a clock signal. In a sequential digital logic circuit, data are stored in memory devices called flip-fl ...
). Many tools "enforce synchronous design practices". Making a clockless CPU (designing an asynchronous circuit) involves modifying the design tools to handle clockless logic and doing extra testing to ensure the design avoids
metastable
In chemistry and physics, metastability denotes an intermediate Energy level, energetic state within a dynamical system other than the system's ground state, state of least energy.
A ball resting in a hollow on a slope is a simple example of me ...
problems. The group that designed the
AMULET
An amulet, also known as a good luck charm or phylactery, is an object believed to confer protection upon its possessor. The word "amulet" comes from the Latin word amuletum, which Pliny's ''Natural History'' describes as "an object that protects ...
, for example, developed a tool called LARD to cope with the complex design of AMULET3.
Examples
Despite all the difficulties numerous asynchronous CPUs have been built.
The
ORDVAC
The ORDVAC (''Ordnance Discrete Variable Automatic Computer)'', is an early computer built by the University of Illinois for the Ballistic Research Laboratory at Aberdeen Proving Ground. A successor to the ENIAC (along with EDVAC built earlier). ...
of 1951 was a successor to the
ENIAC
ENIAC (; Electronic Numerical Integrator and Computer) was the first programmable, electronic, general-purpose digital computer, completed in 1945. There were other computers that had these features, but the ENIAC had all of them in one packa ...
and the first asynchronous computer ever built.
The
ILLIAC II
The ILLIAC II was a revolutionary super-computer built by the University of Illinois that became operational in 1962.
Description
The concept, proposed in 1958, pioneered Emitter-coupled logic (ECL) circuitry, pipelining, and transistor memory ...
was the first completely asynchronous, speed independent processor design ever built; it was the most powerful computer at the time.
DEC
PDP-16
The PDP-16 (Programmed Data Processor-16) was mainly intended for industrial control systems, but with more capability than DEC's PDP-14 The PDP-14 was a specialized computer from Digital Equipment Corporation’s Industrial Products Group desig ...
Register Transfer Modules (ca. 1973) allowed the experimenter to construct asynchronous, 16-bit processing elements. Delays for each module were fixed and based on the module's worst-case timing.
Caltech
Since the mid-1980s,
Caltech
The California Institute of Technology (branded as Caltech or CIT)The university itself only spells its short form as "Caltech"; the institution considers other spellings such a"Cal Tech" and "CalTech" incorrect. The institute is also occasional ...
has designed four non-commercial CPUs in attempt to evaluate performance and energy efficiency of the asynchronous circuits.
; Caltech Asynchronous Microprocessor (CAM)
In 1988 the Caltech Asynchronous Microprocessor (CAM) was the first asynchronous,
quasi delay-insensitive (QDI) microprocessor made by Caltech.
The processor had 16-bit wide
RISC
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set comput ...
ISA and
separate instruction and data memories.
It was manufactured by
MOSIS
MOSIS (Metal Oxide Semiconductor Implementation Service) is multi-project wafer service that provides metal–oxide–semiconductor (MOS) chip design tools and related services that enable universities, government agencies, research institutes and ...
and funded by
DARPA
The Defense Advanced Research Projects Agency (DARPA) is a research and development agency of the United States Department of Defense responsible for the development of emerging technologies for use by the military.
Originally known as the Adv ...
. The project was supervised by the
Office of Naval Research
The Office of Naval Research (ONR) is an organization within the United States Department of the Navy responsible for the science and technology programs of the U.S. Navy and Marine Corps. Established by Congress in 1946, its mission is to plan ...
, the
Army Research Office
The U.S. Army Combat Capabilities Development Command Army Research Laboratory (DEVCOM ARL) is the U.S. Army's foundational research laboratory. ARL is headquartered at the Adelphi Laboratory Center (ALC) in Adelphi, Maryland. Its largest singl ...
, and the
Air Force Office of Scientific Research
The Air Force Research Laboratory (AFRL) is a scientific research organization operated by the United States Air Force Materiel Command dedicated to leading the discovery, development, and integration of aerospace warfighting technologies, pl ...
.
During demonstrations, the researchers loaded a simple program which ran in a tight loop, pulsing one of the output lines after each instruction. This output line was connected to an oscilloscope. When a cup of hot coffee was placed on the chip, the pulse rate (the effective "clock rate") naturally slowed down to adapt to the worsening performance of the heated transistors. When
liquid nitrogen
Liquid nitrogen—LN2—is nitrogen in a liquid state at low temperature. Liquid nitrogen has a boiling point of about . It is produced industrially by fractional distillation of liquid air. It is a colorless, low viscosity liquid that is wide ...
was poured on the chip, the instruction rate shot up with no additional intervention. Additionally, at lower temperatures, the voltage supplied to the chip could be safely increased, which also improved the instruction rate – again, with no additional configuration.
When implemented in
gallium arsenide
Gallium arsenide (GaAs) is a III-V direct band gap semiconductor with a Zincblende (crystal structure), zinc blende crystal structure.
Gallium arsenide is used in the manufacture of devices such as microwave frequency integrated circuits, monoli ...
() it was claimed to achieve 100MIPS. Overall, the research paper interpreted the resultant performance of CAM as superior compared to commercial alternatives available at the time.
; MiniMIPS
In 1998 the MiniMIPS, an experimental, asynchronous
MIPS I
MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, ...
-based microcontroller was made. Even though its
SPICE
A spice is a seed, fruit, root, bark, or other plant substance primarily used for flavoring or coloring food. Spices are distinguished from herbs, which are the leaves, flowers, or stems of plants used for flavoring or as a garnish. Spices a ...
-predicted performance was around 280 MIPS at 3.3 V the implementation suffered from several mistakes in layout (human mistake) and the results turned out be lower by about 40% (see table).
; The Lutonium 8051
Made in 2003, it was a
quasi delay-insensitive asynchronous microcontroller designed for energy efficiency.
The microcontroller's implementation followed the
Harvard architecture
The Harvard architecture is a computer architecture with separate storage and signal pathways for instructions and data. It contrasts with the von Neumann architecture, where program instructions and data share the same memory and pathways.
...
.
Epson
In 2004, Epson manufactured the world's first bendable microprocessor called ACT11, an 8-bit asynchronous chip. Synchronous flexible processors are slower, since bending the material on which a chip is fabricated causes wild and unpredictable variations in the delays of various transistors, for which worst-case scenarios must be assumed everywhere and everything must be clocked at worst-case speed. The processor is intended for use in
smart cards
A smart card, chip card, or integrated circuit card (ICC or IC card) is a physical electronic authentication device, used to control access to a resource. It is typically a plastic credit card-sized card with an embedded integrated circuit (IC) c ...
, whose chips are currently limited in size to those small enough that they can remain perfectly rigid.
IBM
In 2014, IBM announced a
SyNAPSE
In the nervous system, a synapse is a structure that permits a neuron (or nerve cell) to pass an electrical or chemical signal to another neuron or to the target effector cell.
Synapses are essential to the transmission of nervous impulses from ...
-developed chip that runs in an asynchronous manner, with one of the highest
transistor count
The transistor count is the number of transistors in an electronic device (typically on a single substrate or "chip"). It is the most common measure of integrated circuit complexity (although the majority of transistors in modern microprocessors ...
s of any chip ever produced. IBM's chip consumes orders of magnitude less power than traditional computing systems on pattern recognition benchmarks.
Timeline
*
ORDVAC
The ORDVAC (''Ordnance Discrete Variable Automatic Computer)'', is an early computer built by the University of Illinois for the Ballistic Research Laboratory at Aberdeen Proving Ground. A successor to the ENIAC (along with EDVAC built earlier). ...
and the (identical)
ILLIAC I
The ILLIAC I (Illinois Automatic Computer), a pioneering computer in the ILLIAC series of computers built in 1952 by the University of Illinois, was the first computer built and owned entirely by a United States educational institution.
Computer ...
(1951)
[
"In the 1950 and 1960s, asynchronous design was used in many early mainframe computers, including the ILLIAC I and ILLIAC II ... .]
Brief History of asynchronous circuit design
[
"The Illiac is a binary parallel asynchronous computer in which negative numbers are represented as two's complements."
– final summary o]
"Illiac Design Techniques"
1955.
*
Johnniac
The JOHNNIAC was an early computer built by the RAND Corporation (not Remington Rand, maker of the contemporaneous UNIVAC I computer) and based on the von Neumann architecture that had been pioneered on the IAS machine. It was named in honor of v ...
(1953)
[Johnniac history written in 1968](_blank)
/ref>
* WEIZAC
WEIZAC (''Weizmann Automatic Computer'') was the first computer in Israel, and one of the first large-scale, stored-program, electronic computers in the world.
It was built at the Weizmann Institute during 1954–1955, based on the Institute fo ...
(1955)
* Kiev (1958), a Soviet machine using the programming language with pointers much earlier than they came to the PL/1 language[V. M Glushkov and E. L. Yushchenko. Mathematical description of computer "Kiev". UkrSSR, 1962 (in Russian)]
* ILLIAC II
The ILLIAC II was a revolutionary super-computer built by the University of Illinois that became operational in 1962.
Description
The concept, proposed in 1958, pioneered Emitter-coupled logic (ECL) circuitry, pipelining, and transistor memory ...
(1962)
* Victoria University of Manchester
The Victoria University of Manchester, usually referred to as simply the University of Manchester, was a university in Manchester, England. It was founded in 1851 as Owens College. In 1880, the college joined the federal Victoria University. Afte ...
built Atlas
An atlas is a collection of maps; it is typically a bundle of maps of Earth or of a region of Earth.
Atlases have traditionally been bound into book form, but today many atlases are in multimedia formats. In addition to presenting geographic ...
(1964)
* ICL 1906A and 1906S mainframe computers, part of the 1900 series and sold from 1964 for over a decade by ICL
* Polish computers KAR-65 and K-202 (1965 and 1970 respectively)
* Honeywell
Honeywell International Inc. is an American publicly traded, multinational conglomerate corporation headquartered in Charlotte, North Carolina. It primarily operates in four areas of business: aerospace, building technologies, performance ma ...
CPUs 6180 (1972) and Series 60 Level 68 (1981) upon which Multics
Multics ("Multiplexed Information and Computing Service") is an influential early time-sharing operating system based on the concept of a single-level memory.Dennis M. Ritchie, "The Evolution of the Unix Time-sharing System", Communications of t ...
ran asynchronously
* Soviet bit-slice microprocessor modules (late 1970s) produced as К587, К588 and К1883 (U83x in East Germany)
* Caltech Asynchronous Microprocessor, the world-first asynchronous microprocessor (1988)
* ARM
In human anatomy, the arm refers to the upper limb in common usage, although academically the term specifically means the upper arm between the glenohumeral joint (shoulder joint) and the elbow joint. The distal part of the upper limb between the ...
-implementing AMULET
An amulet, also known as a good luck charm or phylactery, is an object believed to confer protection upon its possessor. The word "amulet" comes from the Latin word amuletum, which Pliny's ''Natural History'' describes as "an object that protects ...
(1993 and 2000)
* Asynchronous implementation of MIPS R3000, dubbe
MiniMIPS
(1998)
* Several versions of the XAP processor
The XAP processor is a RISC processor architecture developed by Cambridge Consultants since 1994. XAP processors are a family of 16-bit and 32-bit cores, all of which are intended for use in an application-specific integrated circuit or ASIC chip ...
experimented with different asynchronous design styles: a bundled data XAP, a 1-of-4 XAP, and a 1-of-2 (dual-rail) XAP (2003?)
* ARM-compatible processor (2003?) designed by Z. C. Yu, S. B. Furber, and L. A. Plana; "designed specifically to explore the benefits of asynchronous design for security sensitive applications"
* "Network-based Asynchronous Architecture" processor (2005) that executes a subset of the MIPS architecture
MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, ...
instruction set["A Network-based Asynchronous Architecture for Cryptographic Devices"]
by Ljiljana Spadavecchia
2005
in section "4.10.2 Side-channel analysis of dual-rail asynchronous architectures"
and section "5.5.5.1 Instruction set"
* ARM996HS processor (2006) from Handshake Solutions
* HT80C51 processor (2007?) from Handshake Solutions.
*Vortex, a superscalar
A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single instruction per clock cycle, a sup ...
general purpose CPU with a load/store architecture from Intel (2007); it was developed as Fulcrum Microsystem test Chip 2 and was not commercialized, excepting some of its components; the chip included DDR SDRAM
Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 ...
and a 10Gb Ethernet interface linked via Nexus system-on-chip net to the CPU
* SEAforth multi-core
A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions (such a ...
processor (2008) from Charles H. Moore
Charles Havice Moore II (born 9 September 1938), better known as Chuck Moore, is an American computer engineer and programmer, best known for inventing the Forth programming language in 1968. He cofounded FORTH, Inc., with Elizabeth Rather in ...
* GA144 multi-core
A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions (such a ...
processor (2010) from Charles H. Moore
Charles Havice Moore II (born 9 September 1938), better known as Chuck Moore, is an American computer engineer and programmer, best known for inventing the Forth programming language in 1968. He cofounded FORTH, Inc., with Elizabeth Rather in ...
* TAM16: 16-bit asynchronous microcontroller IP core (Tiempo)
* Aspida asyncronous DLX core; the asynchronous open-source DLX processor (ASPIDA) has been successfully implemented both in ASIC and FPGA versions["Asynchronous Open-Source DLX Processor (ASPIDA)"]
See also
* Globally asynchronous locally synchronous
Globally asynchronous locally synchronous (GALS), in electronics, is an architecture for designing electronic circuits which addresses the problem of safe and reliable data transfer between independent clock domains. GALS is a model of computatio ...
circuits
* Sequential logic
In automata theory, sequential logic is a type of logic circuit whose output depends on the present value of its input signals and on the sequence of past inputs, the input history. This is in contrast to ''combinational logic'', whose output i ...
(asynchronous)
* Adiabatic logic
Adiabatic circuits are low-power electronic circuits which use " reversible logic" to conserve energy. The term " adiabatic" refers to an ideal thermodynamic process in which no heat or mass is exchanged with the surrounding environment, allud ...
* Perfect clock gating
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation, by removing the clock signal when the circuit is not in use or ignores clock signal. Clock gating saves power by pruning the clock tree ...
*Signal transition graphs Signal Transition Graphs (STGs) are typically used in electronic engineering and computer engineering to describe dynamic behaviour of asynchronous circuits, for the purposes of their analysis or synthesis.
Main definitions and applications
Info ...
*Petri net
A Petri net, also known as a place/transition (PT) net, is one of several mathematical modeling languages for the description of distributed systems. It is a class of discrete event dynamic system. A Petri net is a directed bipartite graph that ...
s
Notes
References
Further reading
TiDE
from Handshake Solutions in The Netherlands, Commercial asynchronous circuits design tool. Commercial asynchronous ARM (ARM996HS) and 8051 (HT80C51) are available.
An introduction to asynchronous circuit design
by Davis and Nowick
Asynchronous logic elements. Venjunction and sequention
by V. O. Vasyukevich
a design style pioneered by Theseus Logic, who have fabricated over 20 ASICs based on their NCL08 and NCL8501 microcontroller core
The Status of Asynchronous Design in Industry
Information Society Technologies (IST) Programme, IST-1999-29119, D. A. Edwards W. B. Toms, June 2004, via ''www.scism.lsbu.ac.uk''
* Th
Red Star
is a version of the MIPS R3000 implemented in asynchronous logic
* Th
Amulet microprocessors
were asynchronous ARMs, built in the 1990s at University of Manchester
, mottoeng = Knowledge, Wisdom, Humanity
, established = 2004 – University of Manchester Predecessor institutions: 1956 – UMIST (as university college; university 1994) 1904 – Victoria University of Manchester 1880 – Victoria Univer ...
, England
* Th
N-Protocol
developed by Navarre AsyncArt, the first commercial asynchronous design methodology for conventional FPGAs
PGPSALM
an asynchronous implementation of the 6502 microprocessor
Caltech Async Group home page
Tiempo
French company providing asynchronous IP and design tools
Epson ACT11 Flexible CPU Press Release
Newcastle upon Tyne Async Group page
{{DEFAULTSORT:Asynchronous Circuit
Automata (computation)
Clock signal