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Sunway (processor)
Sunway, or ShenWei, (), is a series of computer microprocessors, developed by Jiangnan Computing Lab () in Wuxi, China. It uses a reduced instruction set computer (RISC) architecture, but details are still sparse. History The Sunway series microprocessors were developed mainly for the use of the military of the People's Republic of China. It is expressed on online forums that the original microarchitecture is believed to be inspired by the DEC Alpha. The SW-3 is thought especially to be based on the Alpha 21164. Jack Dongarra states about the follow-on SW26010, the "ShenWei-64 Instruction Set (this is NOT related to the DEC Alpha instruction set)", and doesn't say it's a new instruction set from the three prior generations he names; although precise details of the instruction set are unknown. Sunway SW-1 * First generation, 2006 * Single-core * 900 MHz Sunway SW-2 * Second generation, 2008 * Dual-core * 1400 MHz * SMIC 130 nm process * 70–100 W Sunwa ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Microprocessor
A microprocessor is a computer processor (computing), processor for which the data processing logic and control is included on a single integrated circuit (IC), or a small number of ICs. The microprocessor contains the arithmetic, logic, and control circuitry required to perform the functions of a computer's central processing unit (CPU). The IC is capable of interpreting and executing program instructions and performing arithmetic operations. The microprocessor is a multipurpose, Clock signal, clock-driven, Processor register, register-based, digital integrated circuit that accepts binary code, binary data as input, processes it according to instruction (computing), instructions stored in its computer memory, memory, and provides results (also in binary form) as output. Microprocessors contain both combinational logic and sequential logic, sequential digital logic, and operate on numbers and symbols represented in the binary number system. The integration of a whole CPU on ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Superscalar
A superscalar processor (or multiple-issue processor) is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single instruction per clock cycle, a superscalar processor can execute or start executing more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to different execution units on the processor. It therefore allows more throughput (the number of instructions that can be executed in a unit of time which can even be less than 1) than would otherwise be possible at a given clock rate. Each execution unit is not a separate processor (or a core if the processor is a multi-core processor), but an execution resource within a single CPU such as an arithmetic logic unit. While a superscalar CPU is typically also pipelined, superscalar and pipelining execution are considered different performance enhancement techni ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
MIPS Architecture
MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, Inc. developed by MIPS Computer Systems, now MIPS Technologies, based in the United States. There are multiple versions of MIPS, including MIPS I, II, III, IV, and V, as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6. MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture. The MIPS architecture has several optional extensions: MIPS-3D, a simple set of floating-point SIMD instructions dedicated to 3D computer graphics; MDMX (MaDMaX), a more extensive i ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Loongson
Loongson () is the name of a family of general-purpose, MIPS architecture-compatible, later in-house LoongArch architecture central processing unit, microprocessors, as well as the name of the Chinese Fabless manufacturing, fabless company (Loongson Technology) that develops them. The processors are alternately called Godson processors, which is described as its academic name. History The ''Godson'' processors, based on MIPS architecture, were initially developed at the ''Institute of Computing Technology'' (ICT), Chinese Academy of Sciences (CAS). The chief architect was . The development of the first Loongson chip was started in 2001. The aim of the Godson project was to develop "high performance general-purpose microprocessors in China", and to become technologically self-sufficient as part of the Made in China 2025 plan. The development was supported by funding via the Chinese Communist Party's Tenth five-year plan (China), 10th and Eleventh five-year plan (China), 11th Five ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Alpha 21164
The Alpha 21164, also known by its code name, EV5, is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA). It was introduced in January 1995, succeeding the Alpha 21064A as Digital's flagship microprocessor. It was succeeded by the Alpha 21264 in 1998. History First silicon of the Alpha 21164 was produced in February 1994, and the OpenVMS, Digital UNIX and Windows NT operating systems were successfully booted on it. It was sampled in late 1994 and was introduced in January 1995 at 266 MHz. A 300 MHz version was introduced in March 1995. The final Alpha 21164, a 333 MHz version, was announced on 2 October 1995, available in sample quantities. The Alpha 21164 was replaced by the Alpha 21164A as Digital's flagship microprocessor in 1996 when a 400 MHz version became available in volume quantities. Users Digital used the Alpha 21164 operating at various clock frequencies in the ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Sunway TaihuLight
The Sunway TaihuLight ( ''Shénwēi·tàihú zhī guāng'') is a Chinese supercomputer which, , is ranked 11th in the TOP500 list, with a LINPACK benchmark rating of 93 petaflops. The name is translated as ''divine power, the light of Taihu Lake''. This is nearly three times as fast as the previous Tianhe-2, which ran at 34 petaflops. , it is ranked as the 16th most energy-efficient supercomputer in the Green500, with an efficiency of 6.1 MFLOPS/W, GFlops/watt. It was designed by the National Research Center of Parallel Computer Engineering & Technology (NRCPC) and is located at the National Supercomputing Center in Wuxi in the city of Wuxi, in Jiangsu province, China. The Sunway TaihuLight was the world's fastest supercomputer for two years, from June 2016 to June 2018, according to the TOP500 lists. The record was surpassed in June 2018 by IBM's Summit (supercomputer), Summit. Architecture The Sunway TaihuLight utilizes domestically developed semiconductors, including a tota ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Sunway BlueLight
The Sunway BlueLight () is a Chinese massively parallel supercomputer. It is the first publicly announced PFLOPS supercomputer using Sunway processors solely developed by the People's Republic of China.JOHN MARKOFF, The New York Times.China Has Homemade Supercomputer Gain" October 28, 2011. Retrieved November 7, 2011.Cade Metz, WIRED.China Builds World-Class Supercomputer Sans Intel, AMD" October 31, 2011. Retrieved November 7, 2011. It ranked #2 in the 2011 China HPC Top100, #14 on the November 2011 TOP500 list, and #39 on the November 2011 Green500 List. The machine was installed at National Supercomputing Jǐnán Center () in September 2011 and was developed by National Parallel Computer Engineering Technology Research Center () and supported by Technology Department () 863 project. The water-cooled 9-rack system has 8704 ShenWei SW1600 processors (For the Top100 run 8575 CPUs were used, at 975 MHz each) organized as 34 super nodes (each consisting of 256 compute nodes) ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Network-on-a-chip
A network on a chip or network-on-chip (NoC or )This article uses the convention that "NoC" is pronounced . Therefore, it uses the convention "a" for the indefinite article corresponding to NoC ("a NoC"). Other sources may pronounce it as and therefore use "an NoC". is a network-based communications subsystem on an integrated circuit ("microchip"), most typically between modules in a system on a chip ( SoC). The modules on the IC are typically semiconductor IP cores schematizing various functions of the computer system, and are designed to be modular in the sense of network science. The network on chip is a router-based packet switching network between SoC modules. NoC technology applies the theory and methods of computer networking to on-chip communication and brings notable improvements over conventional bus and crossbar communication architectures. Networks-on-chip come in many network topologies, many of which are still experimental as of 2018. In 2000s, re ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Manycore Processor
Manycore processors are special kinds of multi-core processors designed for a high degree of parallel processing, containing numerous simpler, independent processor cores (from a few tens of cores to thousands or more). Manycore processors are used extensively in embedded computers and high-performance computing. Contrast with multicore architecture Manycore processors are distinct from multi-core processors in being optimized from the outset for a higher degree of explicit parallelism, and for higher throughput (or lower power consumption) at the expense of latency and lower single-thread performance. The broader category of multi-core processors, by contrast, are usually designed to efficiently run ''both'' parallel ''and'' serial code, and therefore place more emphasis on high single-thread performance (e.g. devoting more silicon to out-of-order execution, deeper pipelines, more superscalar execution units, and larger, more general caches), and shared memory. These techn ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
L2 Cache
A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which stores copies of the data from frequently used main memory locations. Most CPUs have a hierarchy of multiple cache levels (L1, L2, often L3, and rarely even L4), with different instruction-specific and data-specific caches at level 1. The cache memory is typically implemented with static random-access memory (SRAM), in modern CPUs by far the largest part of them by chip area, but SRAM is not always used for all levels (of I- or D-cache), or even any level, sometimes some latter or all levels are implemented with eDRAM. Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the translation lookaside buffer (TLB) which is part of the memory management unit (MMU) whic ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Virtual Memory
In computing, virtual memory, or virtual storage, is a memory management technique that provides an "idealized abstraction of the storage resources that are actually available on a given machine" which "creates the illusion to users of a very large (main) memory". The computer's operating system, using a combination of hardware and software, maps memory addresses used by a program, called '' virtual addresses'', into ''physical addresses'' in computer memory. Main storage, as seen by a process or task, appears as a contiguous address space or collection of contiguous segments. The operating system manages virtual address spaces and the assignment of real memory to virtual memory. Address translation hardware in the CPU, often referred to as a memory management unit (MMU), automatically translates virtual addresses to physical addresses. Software within the operating system may extend these capabilities, utilizing, e.g., disk storage, to provide a virtual address space ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
