|
Sunway TaihuLight
The Sunway TaihuLight ( ''Shénwēi·tàihú zhī guāng'') is a Chinese supercomputer which, , is ranked fourth in the TOP500 list, with a LINPACK benchmark rating of 93 petaflops. The name is translated as ''divine power, the light of Taihu Lake''. This is nearly three times as fast as the previous Tianhe-2, which ran at 34 petaflops. , it is ranked as the 16th most energy-efficient supercomputer in the Green500, with an efficiency of 6.051 GFlops/watt. It was designed by the National Research Center of Parallel Computer Engineering & Technology (NRCPC) and is located at the National Supercomputing Center in Wuxi in the city of Wuxi, in Jiangsu province, China. The Sunway TaihuLight was the world's fastest supercomputer for two years, from June 2016 to June 2018, according to the TOP500 lists. The record was surpassed in June 2018 by IBM's Summit. Architecture The Sunway TaihuLight uses a total of 40,960 Chinese-designed SW26010 manycore 64-bit RISC processors based on th ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
National Supercomputing Center In Wuxi
China operates a number of supercomputer centers which, altogether, hold 29.3% performance share of world's fastest 500 supercomputers. China's Sunway TaihuLight ranks third in the TOP500 list. In the November 2019 list, China dominated the globe's highest performance machines list with 228 out of the top 500 fastest supercomputers in the world, exceeding the second placing (United States) which had 117. History The origins of these centers go back to 1980s, when the State Planning Commission, the State Science and Technology Commission and the World Bank jointly launched a project to develop networking and supercomputer facilities in China. In addition to network facilities, the project included three supercomputer centers. The progress of supercomputing in China has been rapid; the country's most powerful supercomputer placed 43rd in November 2002 (DeepComp 1800), 11th by November 2003 (DeepComp 6800), 10th by June 2004 (Dawning 4000A), and by November 2010 (Tianhe-1A) hel ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Green500
The Green500 is a biannual An anniversary is the date on which an event took place or an institution was founded in a previous year, and may also refer to the commemoration or celebration of that event. The word was first used for Catholic feasts to commemorate saints. ... ranking of supercomputers, from the TOP500 list of supercomputers, in terms of Electrical efficiency, energy efficiency. The list measures performance per watt using the TOP500 measure of LINPACK benchmarks#HPLinpack, high performance LINPACK benchmarks at double-precision floating-point format. In 2022, Hewlett Packard Enterprise took the lead, with AMD-based systems (AMD CPUs and AMD GPUs) in the 4 top positions, with the top position over 50% more efficient than the previous year (Japanese) top position. And number two on the list (the current fastest on TOP500) is also over 50% more efficient than the currently most efficient (and much smaller) Nvidia-based system. No large Nvidia-based system make the ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
National Supercomputing Center Of Tianjin
The National Supercomputing Center of Tianjin () is located at the National Defense Science and Technology University in Tianjin, China. One of the fastest supercomputers in the world (see "The TOP500 Project" list of supercomputers), Tianhe-1A, is located at the facility. History The Tianjin Computer Institute had been active as far back as 1984 and had developed the 16-bit TQ-0671 microcomputer system. As the National Supercomputing Center, the facilities came under the direction (purview) of the National Supercomputing Center council, consisting of members of the National Defense Science and Technology University, the various departments of the Tianjin Economic and Technological Development Zone, and the Tianjin Binhai New Area Administrative Committee. The facilities have been used by various people through the Beijing and Tianjin area. The center was built with the purpose of encouraging and initiating technological development and scientific innovation in the Tianjin Binha ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
National University Of Defense Technology
The National University of Defense Technology (NUDT; ) is a National university, national Public university, public research university in Changsha, Hunan, China. Founded in 1953 as the People's Liberation Army Military Academy of Engineering, the institution is directly affiliated to the Central Military Commission (China), Central Military Commission. The university is a Class A Double First Class University Plan, Double First Class University. It is under the direct leadership of China's Central Military Commission (China), Central Military Commission, and the dual management of the Ministry of National Defense of the People's Republic of China, Ministry of National Defense and the Ministry of Education of the People's Republic of China, Ministry of Education. It is designated for Double First Class University Plan, former Project 211 and Project 985, three national plans facilitating the development of Chinese higher education. NUDT was instrumental in the development of th ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Exascale Computing
Exascale computing refers to computing systems capable of calculating at least "1018 IEEE 754 Double Precision (64-bit) operations (multiplications and/or additions) per second (exaFLOPS)"; it is a measure of supercomputer performance. Exascale computing is a significant achievement in computer engineering: primarily, it allows improved scientific applications and better prediction accuracy in domains such as weather forecasting, climate modeling and personalised medicine. Exascale also reaches the estimated processing power of the human brain at the neural level, a target of the Human Brain Project. There has been a race to be the first country to build an exascale computer, typically ranked in the TOP500 list. In 2022, the world's first public exascale computer, ''Frontier'', was announced. , it is the world's fastest supercomputer. Definitions Floating point operations per second (FLOPS) are one measure of computer performance. FLOPS can be recorded in different measures ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
OpenACC 2
OpenACC (for ''open accelerators'') is a programming standard for parallel computing developed by Cray, CAPS, Nvidia and PGI. The standard is designed to simplify parallel programming of heterogeneous CPU/GPU systems. As in OpenMP, the programmer can annotate C, C++ and Fortran source code to identify the areas that should be accelerated using compiler directives and additional functions. Like OpenMP 4.0 and newer, OpenACC can target both the CPU and GPU architectures and launch computational code on them. OpenACC members have worked as members of the OpenMP standard group to merge into OpenMP specification to create a common specification which extends OpenMP to support accelerators in a future release of OpenMP. These efforts resulted in a technical report for comment and discussion timed to include the annual Supercomputing Conference (November 2012, Salt Lake City) and to address non-Nvidia accelerator support with input from hardware vendors who participate in OpenMP. At ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Cache Hierarchy
Cache hierarchy, or multi-level caches, refers to a memory architecture that uses a hierarchy of memory stores based on varying access speeds to cache data. Highly requested data is cached in high-speed access memory stores, allowing swifter access by central processing unit (CPU) cores. Cache hierarchy is a form and part of memory hierarchy and can be considered a form of tiered storage. This design was intended to allow CPU cores to process faster despite the memory latency of main memory access. Accessing main memory can act as a bottleneck for CPU core performance as the CPU waits for data, while making all of main memory high-speed may be prohibitively expensive. High-speed caches are a compromise allowing high-speed access to the data most-used by the CPU, permitting a faster CPU clock. Background In the history of computer and electronic chip development, there was a period when increases in CPU speed outpaced the improvements in memory access speed. The gap between the ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Network On A Chip
A network on a chip or network-on-chip (NoC or )This article uses the convention that "NoC" is pronounced . Therefore, it uses the convention "a" for the indefinite article corresponding to NoC ("a NoC"). Other sources may pronounce it as and therefore use "an NoC". is a network-based communications subsystem on an integrated circuit ("microchip"), most typically between modules in a system on a chip ( SoC). The modules on the IC are typically semiconductor IP cores schematizing various functions of the computer system, and are designed to be modular in the sense of network science. The network on chip is a router-based packet switching network between SoC modules. NoC technology applies the theory and methods of computer networking to on-chip communication and brings notable improvements over conventional bus and crossbar communication architectures. Networks-on-chip come in many network topologies, many of which are still experimental as of 2018. In 2000s researcher ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Scratchpad Memory
Scratchpad memory (SPM), also known as scratchpad, scratchpad RAM or local store in computer terminology, is a high-speed internal memory used for temporary storage of calculations, data, and other work in progress. In reference to a microprocessor (or CPU), scratchpad refers to a special high-speed memory used to hold small items of data for rapid retrieval. It is similar to the usage and size of a scratchpad in life: a pad of paper for preliminary notes or sketches or writings, etc. In some systems it can be considered similar to the L1 cache in that it is the next closest memory to the ALU after the processor registers, with explicit instructions to move data to and from main memory, often using DMA-based data transfer. In contrast to a system that uses caches, a system with scratchpads is a system with non-uniform memory access (NUMA) latencies, because the memory access latencies to the different scratchpads and the main memory vary. Another difference from a system that ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Sunway Architecture
Sunway, or Shenwei, (Chinese: ), is a series of computer microprocessors, developed by Jiangnan Computing Lab () in Wuxi, China. It uses a reduced instruction set computer (RISC) architecture, but details are still sparse. History The Sunway series microprocessors were developed mainly for the use of the military of the People's Republic of China. It is expressed on online forums that the original microarchitecture is believed to be inspired by the DEC Alpha. The SW-3 is thought especially to be based on the Alpha 21164. Jack Dongarra states about the follow-on SW26010, the "Shenwei-64 Instruction Set (this is NOT related to the DEC Alpha instruction set)", and doesn't say it's a new instruction set from the three prior generations he names; although precise details of the instruction set are unknown. Sunway SW-1 * First generation, 2006 * Single-core * 900 MHz Sunway SW-2 * Second generation, 2008 * Dual-core * 1400 MHz * SMIC 130 nm process * 70–100 W ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Reduced Instruction Set Computing
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions (more code) in order to accomplish a task because the individual instructions are written in simpler code. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an instruction pipeline, which may be simpler given simpler instructions. The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). The RISC computer usually has many (16 or 32) high-speed, general-purpose registers with a load/store architecture in which the code for the register-register instructions (for performing arithmetic and tests) are separate fr ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Manycore Processor
Manycore processors are special kinds of multi-core processors designed for a high degree of parallel processing, containing numerous simpler, independent processor cores (from a few tens of cores to thousands or more). Manycore processors are used extensively in embedded computers and high-performance computing. Contrast with multicore architecture Manycore processors are distinct from multi-core processors in being optimized from the outset for a higher degree of explicit parallelism, and for higher throughput (or lower power consumption) at the expense of latency and lower single-thread performance. The broader category of multi-core processors, by contrast, are usually designed to efficiently run ''both'' parallel ''and'' serial code, and therefore place more emphasis on high single-thread performance (e.g. devoting more silicon to out of order execution, deeper pipelines, more superscalar execution units, and larger, more general caches), and shared memory. These techniqu ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
.PNG "Click for more on -> Network On A Chip")
