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Property Specification Language
Property Specification Language (PSL) is a temporal logic extending linear temporal logic with a range of operators for both ease of expression and enhancement of expressive power. PSL makes an extensive use of regular expressions and syntactic sugaring. It is widely used in the hardware design and verification industry, where formal verification tools (such as model checking) and/or logic simulation tools are used to prove or refute that a given PSL formula holds on a given design. PSL was initially developed by Accellera for specifying properties or assertions about hardware designs. Since September 2004 the standardization on the language has been done in IEEE 1850 working group. In September 2005, the IEEE 1850 Standard for Property Specification Language (PSL) was announced. Syntax and semantics PSL can express that if some scenario happens now, then another scenario should happen some time later. For instance, the property "a should always eventually be ed" can be expr ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Temporal Logic
In logic, temporal logic is any system of rules and symbolism for representing, and reasoning about, propositions qualified in terms of time (for example, "I am ''always'' hungry", "I will ''eventually'' be hungry", or "I will be hungry ''until'' I eat something"). It is sometimes also used to refer to tense logic, a modal logic-based system of temporal logic introduced by Arthur Prior in the late 1950s, with important contributions by Hans Kamp. It has been further developed by computer scientists, notably Amir Pnueli, and logicians. Temporal logic has found an important application in formal verification, where it is used to state requirements of hardware or software systems. For instance, one may wish to say that ''whenever'' a request is made, access to a resource is ''eventually'' granted, but it is ''never'' granted to two requestors simultaneously. Such a statement can conveniently be expressed in a temporal logic. Motivation Consider the statement "I am hungry". Though its ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Need For Multiple Clocks
A need is dissatisfaction at a point of time and in a given context. Needs are distinguished from wants. In the case of a need, a deficiency causes a clear adverse outcome: a dysfunction or death. In other words, a need is something required for a safe, stable and healthy life (e.g. air, water, food, land, shelter) while a want is a desire, wish or aspiration. When needs or wants are backed by purchasing power, they have the potential to become economic demands. Basic needs such as air, water, food and protection from environmental dangers are necessary for an organism to live. In addition to basic needs, humans also have needs of a social or societal nature such as the human need to socialise or belong to a family unit or group. Needs can be objective and physical, such as the need for food, or psychical and subjective, such as the need for self-esteem. The concept of "unmet need" arises in relation to needs in a social context which are not being fulfilled. Needs and wants are ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Formal Specification Languages
Formal, formality, informal or informality imply the complying with, or not complying with, some set of requirements (forms, in Ancient Greek). They may refer to: Dress code and events * Formal wear, attire for formal events * Semi-formal attire, attire for semi-formal events * Informal attire, more controlled attire than casual but less than formal * Formal (university), official university dinner, ball or other event * School formal, official school dinner, ball or other event Logic and mathematics *Formal logic, or mathematical logic ** Informal logic, the complement, whose definition and scope is contentious *Formal fallacy, reasoning of invalid structure ** Informal fallacy, the complement *Informal mathematics, also called naïve mathematics *Formal cause, Aristotle's intrinsic, determining cause * Formal power series, a generalization of power series without requiring convergence, used in combinatorics *Formal calculation, a calculation which is systematic, but without a ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Hardware Verification Languages
A hardware verification language, or HVL, is a programming language used to verify the designs of electronic circuits written in a hardware description language. HVLs typically include features of a high-level programming language like C++ or Java as well as features for easy bit-level manipulation similar to those found in HDLs. Many HVLs will provide constrained random stimulus generation, and functional coverage constructs to assist with complex hardware verification. SystemVerilog, OpenVera, e, and SystemC are the most commonly used HVLs. SystemVerilog attempts to combine HDL and HVL constructs into a single standard. See also * OpenVera * e * SystemC *SystemVerilog *Property Specification Language Property Specification Language (PSL) is a temporal logic extending linear temporal logic with a range of operators for both ease of expression and enhancement of expressive power. PSL makes an extensive use of regular expressions and syntactic su ... References ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Computer Aided Verification
In computer science, the International Conference on Computer-Aided Verification (CAV) is an annual academic conference on the theory and practice of computer-aided formal analysis of software and hardware systems, broadly known as formal methods. It is one of the highest-ranked conferences in computer science. Among the important results originally published in CAV are breakthrough techniques in model checking, such as Counterexample-Guided Abstraction Refinement (CEGAR) and partial order reduction. The first CAV was held in 1989 in Grenoble, France. The CAV proceedings (1989-present) are published by Springer Science+Business Media and are open access. See also * List of computer science conferences * Symposium on Logic in Computer Science * European Joint Conferences on Theory and Practice of Software External links *bibliography for CAVat DBLP DBLP is a computer science bibliography website. Starting in 1993 at Universität Trier in Germany, it grew from a small co ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Open SystemC Initiative
Accellera Systems Initiative (Accellera) is a standards organization that supports a mix of user and vendor standards and open interfaces development in the area of electronic design automation (EDA) and integrated circuit (IC) design and manufacturing. It is less constrained than the Institute of Electrical and Electronics Engineers (IEEE) and is therefore the starting place for many standards. Once mature and adopted by the broader community, the standards are usually transferred to the IEEE. History In 2000, Accellera was founded from the merger of Open Verilog International (OVI) and VHDL International, the developers of Verilog and VHDL respectively. Both were originally formed nine years earlier in 1991. In June 2009, a merger was announced between Accellera and The SPIRIT Consortium, another major EDA standards organization focused on IP deployment and reuse. The SPIRIT Consortium obtained SystemRDL from the SystemRDL Alliance and then developed IP-XACT. The merger was com ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SystemVerilog
SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since 2008 Verilog is now part of the same IEEE standard. It is commonly used in the semiconductor and electronic design industry as an evolution of Verilog. History SystemVerilog started with the donation of the Superlog language to Accellera in 2002 by the startup company Co-Design Automation. The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005. In 2009, the standard was merged with the base Verilog (IEEE 1364-2005) standard, creating IEEE Standard 1800-2009. The current version is IEEE standard 1800-2017. The feature-set of SystemVerilog can be divided into two distinct roles: # SystemVerilog for register-transfer level (RTL) design is a ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Verilog
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits. In 2009, the Verilog standard (IEEE 1364-2005) was merged into the SystemVerilog standard, creating IEEE Standard 1800-2009. Since then, Verilog is officially part of the SystemVerilog language. The current version is IEEE standard 1800-2017. Overview Hardware description languages such as Verilog are similar to software programming languages because they include ways of describing the propagation time and signal strengths (sensitivity). There are two types of assignment operators; a blocking assignment (=), and a non-blocking (>>. A generate–endgenerate construct (similar to VHDL's generate–endgenerate) allows Verilog ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
VHDL
The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates, for design entry, documentation, and verification purposes. Since 1987, VHDL has been standardized by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE Std 1076; the latest version of which is IEEE Std 1076-2019. To model analog and mixed-signal systems, an IEEE-standardized HDL based on VHDL called VHDL-AMS (officially IEEE 1076.1) has been developed. VHDL is named after the United States Department of Defense program that created it, the Very High-Speed Integrated Circuits Program (VHSIC). In the early 1980s, the VHSIC Program sought a new HDL for use in the design of the integrated circuits it aimed to develop. The product of this effort was VHDL Version 7.2, released in 1985. The effo ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Omega-regular Languages
The ω-regular languages are a class of ω-languages that generalize the definition of regular languages to infinite words. Formal definition An ω-language ''L'' is ω-regular if it has the form * ''A''ω where ''A'' is a regular language not containing the empty string * ''AB'', the concatenation of a regular language ''A'' and an ω-regular language ''B'' (Note that ''BA'' is ''not'' well-defined) * ''A'' ∪ ''B'' where ''A'' and ''B'' are ω-regular languages (this rule can only be applied finitely many times) The elements of ''A''ω are obtained by concatenating words from ''A'' infinitely many times. Note that if ''A'' is regular, ''A''ω is not necessarily ω-regular, since ''A'' could be for example , the set containing only the empty string, in which case ''A''ω=''A'', which is not an ω-language and therefore not an ω-regular language. It is a straightforward consequence of the definition that the ω-regular languages are precisely the ω-languages of the form ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Linear Temporal Logic
In logic, linear temporal logic or linear-time temporal logic (LTL) is a modal temporal logic with modalities referring to time. In LTL, one can encode formulae about the future of paths, e.g., a condition will eventually be true, a condition will be true until another fact becomes true, etc. It is a fragment of the more complex CTL*, which additionally allows branching time and quantifiers. Subsequently, LTL is sometimes called ''propositional temporal logic'', abbreviated ''PTL''. In terms of expressive power, linear temporal logic (LTL) is a fragment of first-order logic. LTL was first proposed for the formal verification of computer programs by Amir Pnueli in 1977. Syntax LTL is built up from a finite set of propositional variables ''AP'', the logical operators ¬ and ∨, and the temporal modal operators X (some literature uses O or N) and U. Formally, the set of LTL formulas over ''AP'' is inductively defined as follows: * if p ∈ ''AP'' then p is an LTL formula; * if Ï ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
