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VHDL
VHDL
( VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL
VHDL
can also be used as a general purpose parallel programming language.

Contents

1 History

1.1 Standardization

1.1.1 Revisions 1.1.2 Related standards

2 Design 3 Advantages 4 Design examples

4.1 Synthesizable constructs and VHDL
VHDL
templates 4.2 MUX template 4.3 Latch template 4.4 D-type flip-flops 4.5 Example: a counter 4.6 Simulation-only constructs

5 VHDL
VHDL
simulators 6 See also 7 References 8 Further reading 9 External links

History[edit] Starting 1983, VHDL
VHDL
was originally developed at the behest of the U.S Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. The standard MIL-STD-454N [1] in Requirement 64 in section 4.5.1 "ASIC documentation in VHDL" explicitly requires documentation of "Microelectronic Devices" in VHDL. The idea of being able to simulate the ASICs from the information in this documentation was so obviously attractive that logic simulators were developed that could read the VHDL
VHDL
files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. Due to the Department of Defense requiring as much of the syntax as possible to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of Ada,[citation needed] VHDL
VHDL
borrows heavily from the Ada programming language in both concepts and syntax. The initial version of VHDL, designed to IEEE
IEEE
standard IEEE 1076-1987,[2] included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character and time, plus arrays of bit called bit_vector and of character called string. A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE
IEEE
standard 1164, which defined the 9-value logic types: scalar std_logic and its vector version std_logic_vector. Being a resolved subtype of its std_Ulogic parent type, std_logic typed signals allow multiple driving for modeling bus structures, whereby the connected resolution function handles conflicting assignments adequately. The updated IEEE
IEEE
1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to allow ISO-8859-1 printable characters, added the xnor operator, etc.[specify] Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules. In addition to IEEE
IEEE
standard 1164, several child standards were introduced to extend functionality of the language. IEEE
IEEE
standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced signed and unsigned types to facilitate arithmetical operations on vectors. IEEE
IEEE
standard 1076.1 (known as VHDL-AMS) provided analog and mixed-signal circuit design extensions. Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASIC Libraries) and microwave circuit design extensions. In June 2006, the VHDL
VHDL
Technical Committee of Accellera
Accellera
(delegated by IEEE
IEEE
to work on the next update of the standard) approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL
VHDL
code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of case and generate statements, incorporation of VHPI ( VHDL
VHDL
Procedural Interface) (interface to C/C++ languages) and a subset of PSL (Property Specification Language). These changes should improve quality of synthesizable VHDL
VHDL
code, make testbenches more flexible, and allow wider use of VHDL
VHDL
for system-level descriptions. In February 2008, Accellera
Accellera
approved VHDL
VHDL
4.0 also informally known as VHDL
VHDL
2008, which addressed more than 90 issues discovered during the trial period for version 3.0 and includes enhanced generic types. In 2008, Accellera
Accellera
released VHDL
VHDL
4.0 to the IEEE
IEEE
for balloting for inclusion in IEEE
IEEE
1076-2008. The VHDL
VHDL
standard IEEE
IEEE
1076-2008[3] was published in January 2009. Standardization[edit] The IEEE
IEEE
Standard 1076 defines the VHSIC Hardware Description Language or VHDL. It was originally developed under contract F33615-83-C-1003 from the United States Air Force
United States Air Force
awarded in 1983 to a team with Intermetrics, Inc. as language experts and prime contractor, with Texas Instruments
Texas Instruments
as chip design experts and IBM
IBM
as computer system design experts. The language has undergone numerous revisions and has a variety of sub-standards associated with it that augment or extend it in important ways. 1076 was and continues to be a milestone in the design of electronic systems.[citation needed] Revisions[edit]

IEEE
IEEE
1076-1987[2] First standardized revision of ver 7.2 of the language from the United States Air Force. IEEE
IEEE
1076-1993[4](also published with ISBN 1-55937-376-8) Significant improvements resulting from several years of feedback. Probably the most widely used version with the greatest vendor tool support. IEEE
IEEE
1076-2000[5] Minor revision. Introduces the use of protected types. IEEE
IEEE
1076-2002[6] Minor revision of 1076-2000. Rules with regard to buffer ports are relaxed.

IEC 61691-1-1:2004[7] IEC adoption of IEEE
IEEE
1076-2002

IEEE
IEEE
1076-2008[8] (previously referred to as 1076-200x) Major revision released on 2009-01-26. Among other changes, this standard incorporates a basic subset of PSL, allows for generics on packages and subprograms and introduces the use of external names.

IEC 61691-1-1:2011[9] IEC adoption of IEEE
IEEE
1076-2008

Related standards[edit]

IEEE
IEEE
1076.1 VHDL
VHDL
Analog and Mixed-Signal (VHDL-AMS) IEEE
IEEE
1076.1.1 VHDL-AMS Standard Packages (stdpkgs) IEEE
IEEE
1076.2 VHDL
VHDL
Math Package IEEE
IEEE
1076.3 VHDL
VHDL
Synthesis Package (vhdlsynth) IEEE
IEEE
1076.3 VHDL
VHDL
Synthesis Package - Floating Point (fphdl) IEEE
IEEE
1076.4 Timing ( VHDL
VHDL
Initiative Towards ASIC Libraries: vital) IEEE
IEEE
1076.6 VHDL
VHDL
Synthesis Interoperability IEEE 1164 VHDL
VHDL
Multivalue Logic (std_logic_1164) Packages

Design[edit] VHDL
VHDL
is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a testbench. A VHDL
VHDL
simulator is typically an event-driven simulator.[10] This means that each transaction is added to an event queue for a specific scheduled time. E.g. if a signal assignment should occur after 1 nanosecond, the event is added to the queue for time +1ns. Zero delay is also allowed, but still needs to be scheduled: for these cases Delta delay is used, which represent an infinitely small time step. The simulation alters between two modes: statement execution, where triggered statements are evaluated, and event processing, where events in the queue are processed. VHDL
VHDL
has constructs to handle the parallelism inherent in hardware designs, but these constructs (processes) differ in syntax from the parallel constructs in Ada (tasks). Like Ada, VHDL
VHDL
is strongly typed and is not case sensitive. In order to directly represent operations which are common in hardware, there are many features of VHDL
VHDL
which are not found in Ada, such as an extended set of Boolean operators including nand and nor. VHDL
VHDL
has file input and output capabilities, and can be used as a general-purpose language for text processing, but files are more commonly used by a simulation testbench for stimulus or verification data. There are some VHDL
VHDL
compilers which build executable binaries. In this case, it might be possible to use VHDL
VHDL
to write a testbench to verify the functionality of the design using files on the host computer to define stimuli, to interact with the user, and to compare results with those expected. However, most designers leave this job to the simulator. It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production of transparent latches rather than D-type flip-flops as storage elements.[11] One can design hardware in a VHDL
VHDL
IDE (for FPGA
FPGA
implementation such as Xilinx
Xilinx
ISE, Altera
Altera
Quartus, Synopsys
Synopsys
Synplify or Mentor Graphics
Mentor Graphics
HDL Designer) to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL
VHDL
code, the inputs have to be defined correctly. For example, for clock input, a loop process or an iterative statement is required.[12] A final point is that when a VHDL
VHDL
model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD
CPLD
or FPGA, then it is the actual hardware being configured, rather than the VHDL
VHDL
code being "executed" as if on some form of a processor chip. Advantages[edit] The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires). Another benefit is that VHDL
VHDL
allows the description of a concurrent system. VHDL
VHDL
is a dataflow language, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time. A VHDL
VHDL
project is multipurpose. Being created once, a calculation block can be used in many other projects. However, many formational and functional block parameters can be tuned (capacity parameters, memory size, element base, block composition and interconnection structure). A VHDL
VHDL
project is portable. Being created for one element base, a computing device project can be ported on another element base, for example VLSI
VLSI
with various technologies. A big advantage of VHDL
VHDL
compared to original Verilog is that VHDL
VHDL
has a full type system. Designers can use the type system to write much more structured code (especially by declaring record types).[13] Design examples[edit]

This section is written like a manual or guidebook. Please help rewrite this section from a descriptive, neutral point of view, and remove advice or instruction. (January 2013) (Learn how and when to remove this template message)

In VHDL, a design consists at a minimum of an entity which describes the interface and an architecture which contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architectures and configurations. A simple AND gate in VHDL
VHDL
would look something like

-- (this is a VHDL
VHDL
comment)

-- import std_logic from the IEEE
IEEE
library library IEEE; use IEEE.std_logic_1164.all;

-- this is the entity entity ANDGATE is port ( I1 : in std_logic; I2 : in std_logic; O : out std_logic); end entity ANDGATE;

-- this is the architecture architecture RTL of ANDGATE is begin O <= I1 and I2; end architecture RTL;

(Notice that RTL stands for Register transfer level
Register transfer level
design.) While the example above may seem verbose to HDL beginners, many parts are either optional or need to be written only once. Generally simple functions like this are part of a larger behavioral module, instead of having a separate module for something so simple. In addition, use of elements such as the std_logic type might at first seem to be an overkill. One could easily use the built-in bit type and avoid the library import in the beginning. However, using this 9-valued logic (U,X,0,1,Z,W,H,L,-) instead of simple bits (0,1) offers a very powerful simulation and debugging tool to the designer which currently does not exist in any other HDL. In the examples that follow, you will see that VHDL
VHDL
code can be written in a very compact form. However, the experienced designers usually avoid these compact forms and use a more verbose coding style for the sake of readability and maintainability. Another advantage to the verbose coding style is the smaller amount of resources used when programming to a Programmable Logic Device such as a CPLD[citation needed]. Synthesizable constructs and VHDL
VHDL
templates[edit] VHDL
VHDL
is frequently used for two different goals: simulation of electronic designs and synthesis of such designs. Synthesis is a process where a VHDL
VHDL
is compiled and mapped into an implementation technology such as an FPGA
FPGA
or an ASIC. Many FPGA
FPGA
vendors have free (or inexpensive) tools to synthesize VHDL
VHDL
for use with their chips, where ASIC tools are often very expensive. Not all constructs in VHDL
VHDL
are suitable for synthesis. For example, most constructs that explicitly deal with timing such as wait for 10 ns; are not synthesizable despite being valid for simulation. While different synthesis tools have different capabilities, there exists a common synthesizable subset of VHDL
VHDL
that defines what language constructs and idioms map into common hardware for many synthesis tools. IEEE
IEEE
1076.6 defines a subset of the language that is considered the official synthesis subset. It is generally considered a "best practice" to write very idiomatic code for synthesis as results can be incorrect or suboptimal for non-standard constructs. MUX template[edit] The multiplexer, or 'MUX' as it is usually called, is a simple construct very common in hardware design. The example below demonstrates a simple two to one MUX, with inputs A and B, selector S and output X. Note that there are many other ways to express the same MUX in VHDL.

X <= A when S = '1' else B;

Latch template[edit] A transparent latch is basically one bit of memory which is updated when an enable signal is raised. Again, there are many other ways this can be expressed in VHDL.

-- latch template 1: Q <= D when Enable = '1' else Q;

-- latch template 2: process(D,Enable) begin if Enable = '1' then Q <= D; end if; end process;

D-type flip-flops[edit] The D-type flip-flop samples an incoming signal at the rising (or falling) edge of a clock. This example has an asynchronous, active-high reset, and samples at the rising clock edge.

DFF : process(RST, CLK) is begin if RST = '1' then Q <= '0'; elsif rising_edge(CLK) then Q <= D; end if; end process DFF;

Another common way to write edge-triggered behavior in VHDL
VHDL
is with the 'event' signal attribute. A single apostrophe has to be written between the signal name and the name of the attribute.

DFF : process(RST, CLK) is begin if RST = '1' then Q <= '0'; elsif CLK'event and CLK = '1' then Q <= D; end if; end process DFF;

VHDL
VHDL
also lends itself to "one-liners" such as

DFF : Q <= '0' when RST = '1' else D when rising_edge(clk);

or

DFF : process(RST, CLK) is begin if rising_edge(CLK) then Q <= D; Q2 <= Q1; end if; if RST = '1' then Q <= '0'; end if; end process DFF;

Which can be useful if not all signals (registers) driven by this process should be reset. Example: a counter[edit] The following example is an up-counter with asynchronous reset, parallel load and configurable width. It demonstrates the use of the 'unsigned' type, type conversions between 'unsigned' and 'std_logic_vector' and VHDL
VHDL
generics. The generics are very close to arguments or templates in other traditional programming languages like C++.

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- for the unsigned type

entity COUNTER is generic ( WIDTH : in natural := 32); port ( RST : in std_logic; CLK : in std_logic; LOAD : in std_logic; DATA : in std_logic_vector(WIDTH-1 downto 0); Q : out std_logic_vector(WIDTH-1 downto 0)); end entity COUNTER;

architecture RTL of COUNTER is signal CNT : unsigned(WIDTH-1 downto 0); begin process(RST, CLK) is begin if RST = '1' then CNT <= (others => '0'); elsif rising_edge(CLK) then if LOAD = '1' then CNT <= unsigned(DATA); -- type is converted to unsigned else CNT <= CNT + 1; end if; end if; end process;

Q <= std_logic_vector(CNT); -- type is converted back to std_logic_vector end architecture RTL;

More complex counters may add if/then/else statements within the rising_edge(CLK) elsif to add other functions, such as count enables, stopping or rolling over at some count value, generating output signals like terminal count signals, etc. Care must be taken with the ordering and nesting of such controls if used together, in order to produce the desired priorities and minimize the number of logic levels needed. Simulation-only constructs[edit] A large subset of VHDL
VHDL
cannot be translated into hardware. This subset is known as the non-synthesizable or the simulation-only subset of VHDL
VHDL
and can only be used for prototyping, simulation and debugging. For example, the following code will generate a clock with a frequency of 50 MHz. It can, for example, be used to drive a clock input in a design during simulation. It is, however, a simulation-only construct and cannot be implemented in hardware. In actual hardware, the clock is generated externally; it can be scaled down internally by user logic or dedicated hardware.

process begin CLK <= '1'; wait for 10 NS; CLK <= '0'; wait for 10 NS; end process;

The simulation-only constructs can be used to build complex waveforms in very short time. Such waveform can be used, for example, as test vectors for a complex design or as a prototype of some synthesizer logic that will be implemented in the future.

process begin wait until START = '1'; -- wait until START is high

for i in 1 to 10 loop -- then wait for a few clock periods... wait until rising_edge(CLK); end loop;

for i in 1 to 10 loop -- write numbers 1 to 10 to DATA, 1 every cycle DATA <= to_unsigned(i, 8); wait until rising_edge(CLK); end loop;

-- wait until the output changes wait on RESULT;

-- now raise ACK for clock period ACK <= '1'; wait until rising_edge(CLK); ACK <= '0';

-- and so on... end process;

VHDL
VHDL
simulators[edit] Commercial:

Aldec
Aldec
Active-HDL Cadence Incisive (Past products: NC-VHDL) Mentor Graphics
Mentor Graphics
ModelSim. Special
Special
versions of this product used by various FPGA
FPGA
vendors e.g. Altera, Lattice Synopsys
Synopsys
VCS-MX Xilinx
Xilinx
Vivado (a.k.a. xsim). Based on iSim from the previous ISE tool-chain. Xilinx
Xilinx
Inc.

Other:

boot. from Free Range VHDL
VHDL
based on GHDL and GTKWave GHDL from ghdl.free.fr, newer versions available on GitHub VHDL
VHDL
Simili Misc EDA Utilities Free VHDL
VHDL
Parser, vhdl2verilog, vhdl2ipxact and many other utilities EDA Playground - Free web browser-based VHDL
VHDL
IDE (uses Riviera-PRO and ModelSim for VHDL
VHDL
simulation) Nick Gasson's VHDL
VHDL
compiler freehdl by Edwin Naroska

See also[edit]

Altera
Altera
Hardware Description Language (AHDL) numeric_std - a standard package which provides arithmetic functions for vectors SystemC

References[edit]

^ Department of Defense (1992). Military Standard, Standard general requirements for electronic equipment. Retrieved November 15, 2017.  ^ a b 1076-1987 – IEEE
IEEE
Standard VHDL
VHDL
Language Reference Manual. 1988. doi:10.1109/IEEESTD.1988.122645. ISBN 0-7381-4324-3.  ^ 1076-2008 – IEEE
IEEE
Standard VHDL
VHDL
Language Reference Manual. 2009. doi:10.1109/IEEESTD.2009.4772740. ISBN 978-0-7381-6854-8.  ^ 1076-1993 – IEEE
IEEE
Standard VHDL
VHDL
Language Reference Manual. 1994. doi:10.1109/IEEESTD.1994.121433. ISBN 0-7381-0986-X.  ^ 1076-2000 – IEEE
IEEE
Standard VHDL
VHDL
Language Reference Manual. 2000. doi:10.1109/IEEESTD.2000.92297. ISBN 0-7381-1948-2.  ^ 1076-2002 – IEEE
IEEE
Standard VHDL
VHDL
Language Reference Manual. 2002. doi:10.1109/IEEESTD.2002.93614. ISBN 0-7381-3247-0.  ^ IEC 61691-1-1 First edition 2004-10; IEEE
IEEE
1076 — IEC/IEEE Behavioural Languages - Part 1-1: VHDL
VHDL
Language Reference Manual (Adoption of IEEE
IEEE
Std 1076-2002). 2004. doi:10.1109/IEEESTD.2004.95752. ISBN 2-8318-7691-5.  ^ 1076c-2007 – IEEE
IEEE
Standard VHDL
VHDL
Language Reference Manual Amendment 1: Procedural Language Application Interface. 2007. doi:10.1109/IEEESTD.2007.4299594. ISBN 0-7381-5523-3.  ^ 61691-1-1-2011 — Behavioural languages - Part 1-1: VHDL
VHDL
Language Reference Manual. 2011. doi:10.1109/IEEESTD.2011.5967868. ISBN 978-0-7381-6605-6.  ^ "ELEC3017 - Simulation" (PDF). University of Southampton. Retrieved 23 February 2017.  ^ "Why should I care about Transparent Latches?". Doulos. Retrieved 22 December 2012.  ^ "Clock Generation". Doulos. Retrieved 22 December 2012.  ^ Jiri Gaisler. "A structured VHDL
VHDL
Design Method" (PDF). Retrieved 15 November 2017. 

Notes

1076/INT-1991 – IEEE
IEEE
Standards Interpretations: IEEE
IEEE
Std 1076-1987, IEEE
IEEE
Standard VHDL
VHDL
Language Reference Manual. 1992. doi:10.1109/IEEESTD.1992.101084. ISBN 0-7381-0987-8. 

Further reading[edit]

Peter J. Ashenden, "The Designer's Guide to VHDL, Third Edition (Systems on Silicon)", 2008, ISBN 0-1208-8785-1. (The VHDL reference book written by one of the lead developers of the language) Bryan Mealy, Fabrizio Tappero (February 2012). Free Range VHDL. The no-frills guide to writing powerful VHDL
VHDL
code for your digital implementations. freerangefactory.org. Johan Sandstrom (October 1995). "Comparing Verilog to VHDL Syntactically and Semantically". Integrated System Design. EE Times.  — Sandstrom presents a table relating VHDL
VHDL
constructs to Verilog constructs. Qualis Design Corporation (2000-07-20). " VHDL
VHDL
quick reference card" (PDF). 1.1. Qualis Design Corporation. Archived from the original (PDF) on 2003-12-10.  Qualis Design Corporation (2000-07-20). "1164 packages quick reference card" (PDF). 1.0. Qualis Design Corporation. Archived from the original (PDF) on 2016-03-14.  Janick Bergeron, "Writing Testbenches: Functional Verification of HDL Models", 2000, ISBN 0-7923-7766-4. (The HDL Testbench Bible)

External links[edit]

Wikimedia Commons has media related to VHDL.

The Wikibook Programmable Logic has a page on the topic of: VHDL

Official website VHDL
VHDL
Analysis and Standardization Group (VASG)

v t e

IEEE
IEEE
standards

Current

488 730 754

Revision

854 828 829 896 1003 1014 1016 1076 1149.1 1154 1164 1275 1278 1284 1355 1394 1451 1497 1516 1541 1547 1584 1588 1596 1603 1613 1666 1667 1675 1685 1800 1801 1815 1850 1900 1901 1902 1904 1905 2030 11073 12207 14764 16085 16326 29148 42010

802 series

802.1

D p Q Qat Qay w X ab ad AE ag ah ak aq ax az

802.11

a b c d e f g h i j k n p r s u v w y ac ad af ah ai ax ay

.2 .3 .4 .5 .6 .7 .8 .9 .10 .12 .14 .15

.1 .4 .4a

.16

d · e

.17 .18 .20 .21 .22

Proposed

P1363 P1619 P1699 P1823 P1906.1

Superseded

754-1985 830 1219 1233 1362 1364 1471

See also IEEE
IEEE
Standards Association Category: IEEE
IEEE
standards

v t e

Programmable logic

Concepts

ASIC SOC FPGA

Logic block

CPLD EPLD PLA PAL GAL PSoC Reconfigurable computing

Xputer

Soft microprocessor Circuit underutilization

Languages

Verilog

A AMS

VHDL

AMS VITAL

SystemVerilog

DPI

SystemC AHDL Handel-C PSL UPF PALASM ABEL CUPL OpenVera C to HDL Flow to HDL MyHDL JHDL ELLA

Companies

Accellera Actel Achronix AMD Aldec Altera Atmel Cadence Cypress Duolog Forte Intel Lattice National Mentor Graphics Microsemi Signetics Synopsys

Magma Virage Logic

Texas Instruments Tabula Xilinx

Products

Hardware

iCE Stratix Virtex

Software

Altera
Altera
Quartus Xilinx
Xilinx
ISE Xilinx
Xilinx
Vivado ModelSim VTR Simulators

IP

Proprietary

ARC LEON LatticeMico8 MicroBlaze PicoBlaze Nios Nios II

Open-source

JOP LatticeMico32 OpenCores OpenRISC

120

.