VHSIC HARDWARE DESCRIPTION LANGUAGE) is a hardware description
language used in electronic design automation to describe digital and
mixed-signal systems such as field-programmable gate arrays and
integrated circuits .
VHDL can also be used as a general purpose
parallel programming language .
* 1 History
* 1.1 Standardization
* 1.1.1 Revisions
* 1.1.2 Related standards
* 2 Design
* 3 Advantages
* 4 Design examples
* 4.1 Synthesizable constructs and
* 4.2 MUX template
* 4.3 Latch template
* 4.4 D-type flip-flops
* 4.5 Example: a counter
* 4.6 Simulation-only constructs
* 6 See also
* 7 References
* 8 Further reading
* 9 External links
VHDL was originally developed at the behest of the U.S Department of
Defense in order to document the behavior of the ASICs that supplier
companies were including in equipment.
The idea of being able to simulate the ASICs from the information in
this documentation was so obviously attractive that logic simulators
were developed that could read the
VHDL files. The next step was the
development of logic synthesis tools that read the VHDL, and output a
definition of the physical implementation of the circuit.
Due to the Department of Defense requiring as much of the syntax as
possible to be based on Ada, in order to avoid re-inventing concepts
that had already been thoroughly tested in the development of Ada,
VHDL borrows heavily from the Ada programming language in both
concepts and syntax .
The initial version of VHDL, designed to
IEEE standard IEEE
1076-1987, included a wide range of data types, including numerical
(integer and real ), logical (bit and boolean ), character and time ,
plus arrays of bit called bit_vector and of character called string .
A problem not solved by this edition, however, was "multi-valued
logic", where a signal's drive strength (none, weak or strong) and
unknown values are also considered. This required
IEEE standard 1164 ,
which defined the 9-value logic types: scalar std_logic and its vector
version std_logic_vector. Being a resolved subtype of its std_Ulogic
parent type, std_logic typed signals allow multiple driving for
modeling bus structures, whereby the connected resolution function
handles conflicting assignments adequately.
IEEE 1076 , in 1993, made the syntax more consistent,
allowed more flexibility in naming, extended the character type to
allow ISO-8859-1 printable characters, added the xnor operator, etc.
Minor changes in the standard (2000 and 2002) added the idea of
protected types (similar to the concept of class in C++) and removed
some restrictions from port mapping rules.
In addition to
IEEE standard 1164, several child standards were
introduced to extend functionality of the language.
1076.2 added better handling of real and complex data types. IEEE
standard 1076.3 introduced signed and unsigned types to facilitate
arithmetical operations on vectors.
IEEE standard 1076.1 (known as
VHDL-AMS ) provided analog and mixed-signal circuit design extensions.
Some other standards support wider use of VHDL, notably VITAL (VHDL
Initiative Towards ASIC Libraries) and microwave circuit design
In June 2006, the
VHDL Technical Committee of
Accellera (delegated by
IEEE to work on the next update of the standard) approved so called
Draft 3.0 of VHDL-2006. While maintaining full compatibility with
older versions, this proposed standard provides numerous extensions
that make writing and managing
VHDL code easier. Key changes include
incorporation of child standards (1164, 1076.2, 1076.3) into the main
1076 standard, an extended set of operators, more flexible syntax of
case and generate statements, incorporation of VHPI (
Interface) (interface to C/C++ languages) and a subset of PSL
Property Specification Language ). These changes should improve
quality of synthesizable
VHDL code, make testbenches more flexible,
and allow wider use of
VHDL for system-level descriptions.
In February 2008,
VHDL 4.0 also informally known
VHDL 2008, which addressed more than 90 issues discovered during
the trial period for version 3.0 and includes enhanced generic types.
VHDL 4.0 to the
IEEE for balloting for
IEEE 1076-2008. The
IEEE 1076-2008 was
published in January 2009.
IEEE Standard 1076 defines the
VHSIC Hardware Description
Language or VHDL. It was originally developed under contract
F33615-83-C-1003 from the
United States Air Force
United States Air Force awarded in 1983 to a
team with Intermetrics, Inc. as language experts and prime contractor,
Texas Instruments as chip design experts and
IBM as computer
system design experts. The language has undergone numerous revisions
and has a variety of sub-standards associated with it that augment or
extend it in important ways.
1076 was and continues to be a milestone in the design of electronic
IEEE 1076-1987 First standardized revision of ver 7.2 of the
language from the United States Air Force.
IEEE 1076-1993 (also published with ISBN 1-55937-376-8 )
Significant improvements resulting from several years of feedback.
Probably the most widely used version with the greatest vendor tool
IEEE 1076-2000 Minor revision. Introduces the use of protected
IEEE 1076-2002 Minor revision of 1076-2000. Rules with regard to
buffer ports are relaxed.
* IEC 61691-1-1:2004 IEC adoption of
IEEE 1076-2008 (previously referred to as 1076-200x) Major
revision released on 2009-01-26. Among other changes, this standard
incorporates a basic subset of PSL, allows for generics on packages
and subprograms and introduces the use of external names.
* IEC 61691-1-1:2011 IEC adoption of
VHDL Analog and Mixed-Signal (
VHDL-AMS Standard Packages (stdpkgs)
VHDL Math Package
VHDL Synthesis Package (vhdlsynth)
VHDL Synthesis Package - Floating Point (fphdl)
IEEE 1076.4 Timing (
VHDL Initiative Towards ASIC Libraries: vital)
VHDL Synthesis Interoperability
VHDL Multivalue Logic (std_logic_1164) Packages
VHDL is commonly used to write text models that describe a logic
circuit. Such a model is processed by a synthesis program, only if it
is part of the logic design. A simulation program is used to test the
logic design using simulation models to represent the logic circuits
that interface to the design. This collection of simulation models is
commonly called a testbench.
VHDL simulator is typically an event-driven simulator . This means
that each transaction is added to an event queue for a specific
scheduled time. E.g. if a signal assignment should occur after 1
nanosecond, the event is added to the queue for time +1ns. Zero delay
is also allowed, but still needs to be scheduled: for these cases
Delta delay is used, which represent an infinitely small time step.
The simulation alters between two modes: statement execution, where
triggered statements are evaluated, and event processing, where events
in the queue are processed.
VHDL has constructs to handle the parallelism inherent in hardware
designs, but these constructs (processes) differ in syntax from the
parallel constructs in Ada (tasks). Like Ada,
VHDL is strongly typed
and is not case sensitive . In order to directly represent operations
which are common in hardware, there are many features of
are not found in Ada, such as an extended set of Boolean operators
including NAND and NOR.
VHDL also allows arrays to be indexed in
either ascending or descending direction; both conventions are used in
hardware, whereas in Ada and most programming languages only ascending
indexing is available.
VHDL has file input and output capabilities, and can be used as a
general-purpose language for text processing, but files are more
commonly used by a simulation testbench for stimulus or verification
data. There are some
VHDL compilers which build executable binaries.
In this case, it might be possible to use
VHDL to write a testbench to
verify the functionality of the design using files on the host
computer to define stimuli, to interact with the user, and to compare
results with those expected. However, most designers leave this job to
It is relatively easy for an inexperienced developer to produce code
that simulates successfully but that cannot be synthesized into a real
device, or is too large to be practical. One particular pitfall is the
accidental production of transparent latches rather than D-type
flip-flops as storage elements.
One can design hardware in a
VHDL IDE (for
FPGA implementation such
Synopsys Synplify or Mentor Graphics
HDL Designer) to produce the RTL schematic of the desired circuit.
After that, the generated schematic can be verified using simulation
software which shows the waveforms of inputs and outputs of the
circuit after generating the appropriate testbench. To generate an
appropriate testbench for a particular circuit or
VHDL code, the
inputs have to be defined correctly. For example, for clock input, a
loop process or an iterative statement is required.
A final point is that when a
VHDL model is translated into the "gates
and wires" that are mapped onto a programmable logic device such as a
FPGA , then it is the actual hardware being configured, rather
VHDL code being "executed" as if on some form of a processor
The key advantage of VHDL, when used for systems design, is that it
allows the behavior of the required system to be described (modeled)
and verified (simulated) before synthesis tools translate the design
into real hardware (gates and wires).
Another benefit is that
VHDL allows the description of a concurrent
VHDL is a dataflow language , unlike procedural computing
languages such as BASIC, C, and assembly code, which all run
sequentially, one instruction at a time.
VHDL project is multipurpose. Being created once, a calculation
block can be used in many other projects. However, many formational
and functional block parameters can be tuned (capacity parameters,
memory size, element base, block composition and interconnection
VHDL project is portable. Being created for one element base, a
computing device project can be ported on another element base, for
VLSI with various technologies.
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In VHDL, a design consists at a minimum of an entity which describes
the interface and an architecture which contains the actual
implementation. In addition, most designs import library modules. Some
designs also contain multiple architectures and configurations.
A simple AND gate in
VHDL would look something like
-- (this is a
VHDL comment) -- import std_logic from the IEEE
library library IEEE; use IEEE.std_logic_1164.all; -- this is the
entity entity ANDGATE is port ( I1 : in std_logic; I2 : in std_logic;
O : out std_logic); end entity ANDGATE; -- this is the architecture
architecture RTL of