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List Of AMD FX Microprocessors
AMD FX is a series of AMD microprocessors for personal computers. The following is a list of AMD FX brand microprocessors. Some APUs also carry an FX model name, but the term "FX" normally only refers to CPUs which are not just APUs with the iGPU disabled. Features overview "Pure" CPUs CPU features table APUs APU features table Desktop "pure" CPUs Athlon 64 Family (90–130 nm) These processors were the first AMD CPUs to use the "FX" designation and identified the chip as being higher-performance. The frequency multiplier was unlocked in these chips. See the comprehensive List of AMD Athlon 64 processors SledgeHammer Core (130 nm) * Socket 940 * L1 cache: 64 kb + 64 kb (data + instruction) * L2 cache: 1024 kb (full speed) * Instruction sets: MMX, SSE, SSE2, Enhanced 3DNow!, NX bit, AMD64 FX-51 (2.2 GHz) and FX-53 (2.4 GHz) ClawHammer Core (130 nm) * Socket 939 * L1 cache: 64 kb + 64 kb (data + instruction) * L2 cache: 1024 kb (full speed) * Instructi ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
List Of AMD Processors
This article gives a list of AMD microprocessors, sorted by generation and release year. If applicable and openly known, the designation(s) of each processor's core (versions) is (are) listed in parentheses. For an overview over concrete product, you then need to consult further articles, like e.g. List of AMD accelerated processing units. Features overview AMD IP x86 CPUs AMD IP x86 CPU features table APUs APU features table AMD-originated architectures Am2900 series (1975) * Am2901 4-bit-slice ALU (1975) * Am2902 Look-Ahead Carry Generator * Am2903 4-bit-slice ALU, with hardware multiply * Am2904 Status and Shift Control Unit * Am2905 Bus Transceiver * Am2906 Bus Transceiver with Parity * Am2907 Bus Transceiver with Parity * Am2908 Bus Transceiver with Parity * Am2909 4-bit-slice address sequencer * Am2910 12-bit address sequencer * Am2911 4-bit-slice address sequencer * Am2912 Bus Transceiver * Am2913 Priority Interrupt Expander * Am2914 Priority Interru ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revision of their Pentium 4 CPU. In April 2005, AMD introduced a subset of SSE3 in revision E (Venice and San Diego) of their Athlon 64 CPUs. The earlier SIMD instruction sets on the x86 platform, from oldest to newest, are MMX, 3DNow! (developed by AMD, but not supported by Intel processors), SSE, and SSE2. SSE3 contains 13 new instructions over SSE2. Changes The most notable change is the capability to work horizontally in a register, as opposed to the more or less strictly vertical operation of all previous SSE instructions. More specifically, instructions to add and subtract the multiple values stored within a single register have been added. These instructions can be used to speed up the implementation of a number of DSP and 3D operati ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SSE4
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more precise details of 47 instructions became available at the Spring 2007 Intel Developer Forum in Beijing, in the presentation. SSE4 is fully compatible with software written for previous generations of Intel 64 and IA-32 architecture microprocessors. All existing software continues to run correctly without modification on microprocessors that incorporate SSE4, as well as in the presence of existing and new applications that incorporate SSE4. SSE4 subsets Intel SSE4 consists of 54 instructions. A subset consisting of 47 instructions, referred to as ''SSE4.1'' in some Intel documentation, is available in Penryn. Additionally, ''SSE4.2'', a second subset consisting of the 7 remaining instructions, is first available in Nehalem-based Core i7 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitecture on June 26, 2006 with the "Woodcrest" Xeons. SSSE3 has been referred to by the codenames Tejas New Instructions (TNI) or Merom New Instructions (MNI) for the first processor designs intended to support it. Functionality SSSE3 contains 16 new discrete instructions. Each instruction can act on 64-bit MMX or 128-bit XMM registers. Therefore, Intel's materials refer to 32 new instructions. They include: * Twelve instructions that perform horizontal addition or subtraction operations. * Six instructions that evaluate absolute values. * Two instructions that perform multiply-and-add operations and speed up the evaluation of dot products. * Two instructions that accelerate packed integer multiply operations and produce integer values with ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Die (integrated Circuit)
A die, in the context of integrated circuits, is a small block of semiconducting material on which a given functional circuit is fabricated. Typically, integrated circuits are produced in large batches on a single wafer of electronic-grade silicon (EGS) or other semiconductor (such as GaAs) through processes such as photolithography. The wafer is cut (diced) into many pieces, each containing one copy of the circuit. Each of these pieces is called a die. There are three commonly used plural forms: ''dice'', ''dies'' and ''die''. To simplify handling and integration onto a printed circuit board, most dies are packaged in various forms. Manufacturing process Most dies are composed of silicon and used for integrated circuits. The process begins with the production of monocrystalline silicon ingots. These ingots are then sliced into disks with a diameter of up to 300 mm. [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
DDR3 SDRAM
Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth (" double data rate") interface, and has been in use since 2007. It is the higher-speed successor to DDR and DDR2 and predecessor to DDR4 synchronous dynamic random-access memory (SDRAM) chips. DDR3 SDRAM is neither forward nor backward compatible with any earlier type of random-access memory (RAM) because of different signaling voltages, timings, and other factors. DDR3 is a DRAM interface specification. The actual DRAM arrays that store the data are similar to earlier types, with similar performance. The primary benefit of DDR3 SDRAM over its immediate predecessor DDR2 SDRAM, is its ability to transfer data at twice the rate (eight times the speed of its internal memory arrays), enabling higher bandwidth or peak data rates. The DDR3 standard permits DRAM chip capacities of up to 8 gigabits (Gbit), and up to four ranks ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
DIMM
A DIMM () (Dual In-line Memory Module), commonly called a RAM stick, comprises a series of dynamic random-access memory integrated circuits. These memory modules are mounted on a printed circuit board and designed for use in personal computers, workstations, printers, and servers. They are the predominant method for adding memory into a computer system. The vast majority of DIMMs are standardized through JEDEC standards, although there are proprietary DIMMs. DIMMs come in a variety of speeds and sizes, but generally are one of two lengths - PC which are and laptop (SO-DIMM) which are about half the size at . History DIMMs (Dual In-line Memory Module) were a 1990s upgrade for SIMMs (Single In-line Memory Modules) as Intel P5-based Pentium processors began to gain market share. The Pentium had a 64-bit bus width, which would require SIMMs installed in matched pairs in order to populate the data bus. The processor would then access the two SIMMs in parallel. DIMMs were i ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Bulldozer (microarchitecture)
The AMD Bulldozer Family 15h is a microprocessor microarchitecture for the FX and Opteron line of processors, developed by AMD for the desktop and server markets. Bulldozer is the codename for this family of microarchitectures. It was released on October 12, 2011, as the successor to the K10 microarchitecture. Bulldozer is designed from scratch, not a development of earlier processors. The core is specifically aimed at computing products with TDPs of 10 to 125 watts. AMD claims dramatic performance-per-watt efficiency improvements in high-performance computing (HPC) applications with Bulldozer cores. The ''Bulldozer'' cores support most of the instruction sets implemented by Intel processors (Sandy Bridge) available at its introduction (including SSE4.1, SSE4.2, AES, CLMUL, and AVX) as well as new instruction sets proposed by AMD; ABM, XOP, FMA4 and F16C. Only Bulldozer GEN4 (Excavator) supports AVX2 instruction sets. Overview According to AMD, Bulldozer-based CPU ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
CPU Socket
In computer hardware, a CPU socket or CPU slot contains one or more mechanical components providing mechanical and electrical connections between a microprocessor and a printed circuit board (PCB). This allows for placing and replacing the central processing unit (CPU) without soldering. Common sockets have retention clips that apply a constant force, which must be overcome when a device is inserted. For chips with many pins, zero insertion force (ZIF) sockets are preferred. Common sockets include Pin Grid Array (PGA) or Land Grid Array (LGA). These designs apply a compression force once either a handle (PGA type) or a surface plate (LGA type) is put into place. This provides superior mechanical retention while avoiding the risk of bending pins when inserting the chip into the socket. Certain devices use Ball Grid Array (BGA) sockets, although these require soldering and are generally not considered user replaceable. CPU sockets are used on the motherboard in desktop and serv ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Socket AM3+
AM3+ is a modification of the AM3 Socket, released in mid-2011, designed for CPUs which use the AMD Bulldozer microarchitecture and retains compatibility with AM3 processors. The Vishera line of AMD CPUs also all use Socket AM3+. It is the last AMD socket for which Windows XP support officially exists. Technical specifications The AM3+ Socket specification contains a few noteworthy design changes over its AM3 predecessor. The 942 pin count for the AM3+ is an increase of one compared to the AM3 Socket layout. The AM3+ Socket has larger pin socket diameter of 0.51 mm compared to 0.45 mm with the AM3 Socket. There is a faster serial link of 3400 kHz from the CPU to the power controller, compared to 400 kHz. The AM3+ Socket offers improved power regulation and power quality specifications, including an increased maximum current support of 145 A versus 110 A. There is also a redesigned CPU cooler retention harness allowing for slightly better airflow for CPU cooli ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Product Binning
Product binning is the categorizing of finished products based on their characteristics. Any mining, harvesting, or manufacturing process will yield products spanning a range of quality and desirability in the marketplace. Binning allows differing quality products to be priced appropriately for various uses and markets. Economic and legal theory Product binning and grading allows a degree of price discrimination which may be easier to defend legally, since it can be based on real or perceived differences in product quality. In order to undergo binning, manufactured products require testing, usually performed by machines in bulk. Binning allows large variances in performance to be condensed into a smaller number of marketed designations. This ensures coherency in the marketplace, with tiers of performance clearly delineated. The immediate result of this practice is that, for legal and reputational reasons, products sold under a certain designation must meet that designation at a ' ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Socket F
Socket F is a CPU socket designed by Advanced Micro Devices, AMD for its Opteron line of Central processing unit, CPUs released on August 15, 2006. In 2010 Socket F was replaced by Socket C32 for entry-level servers and Socket G34 for high-end servers. Technical specifications The socket has 1207 pins on a 1.1mm pitch and employs a land grid array contact mechanism. Socket F is primarily for use in AMD's Server (computing), server line and is considered to be in the same socket generation as Socket AM2, which is used for the Athlon 64 and Athlon 64 X2; as well as Socket S1, which is used for Turion 64 and Turion 64 X2 microprocessors. AMD Quad FX platform Socket F is the base for the AMD Quad FX Platform (referred to as "4x4" or "QuadFather" prior to release), unveiled by AMD on November 30, 2006. This modified version of Socket F, named Socket 1207 FX by AMD, and Socket L1 by NVIDIA, allows for dual-socket, dual-core (four effective cores and eight effective cores in the f ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
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