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45 Nanometer
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007–2008 time frame. Matsushita and Intel started mass-producing 45 nm chips in late 2007, and AMD started production of 45 nm chips in late 2008, while IBM, Infineon, Samsung, and Chartered Semiconductor have already completed a common 45 nm process platform. At the end of 2008, SMIC was the first China-based semiconductor company to move to 45 nm, having licensed the bulk 45 nm process from IBM. In 2008, TSMC moved on to a 40nm process. Many critical feature sizes are smaller than the wavelength of light used for lithography (i.e., 193 nm and 248 nm). A variety of techniques, such as larger lenses, are used to make sub-wavelength features. Double patterning has also been introduced to assist in shrinking distances between features, especially if dry lit ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
International Technology Roadmap For Semiconductors
The International Technology Roadmap for Semiconductors (ITRS) is a set of documents produced by a group of semiconductor industry experts. These experts are representative of the sponsoring organisations which include the Semiconductor Industry Associations of Taiwan, South Korea, the United States, Europe, Japan, and China. As of 2017, ITRS is no longer being updated. Its successor is the International Roadmap for Devices and Systems. The documents carried disclaimer: "The ITRS is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment". The documents represent best opinion on the directions of research and time-lines up to about 15 years into the future for the following areas of technology: History Constructing an integrated circuit, or any semiconductor device, requires a series of operations—photolithography, etching, metal deposition, and so on. As the industry evolved, ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Static Random Access Memory
Static random-access memory (static RAM or SRAM) is a type of random-access memory (RAM) that uses latching circuitry (flip-flop) to store each bit. SRAM is volatile memory; data is lost when power is removed. The term ''static'' differentiates SRAM from DRAM (''dynamic'' random-access memory) — SRAM will hold its data permanently in the presence of power, while data in DRAM decays in seconds and thus must be periodically refreshed. SRAM is faster than DRAM but it is more expensive in terms of silicon area and cost; it is typically used for the cache and internal registers of a CPU while DRAM is used for a computer's main memory. History Semiconductor bipolar SRAM was invented in 1963 by Robert Norman at Fairchild Semiconductor. MOS SRAM was invented in 1964 by John Schmidt at Fairchild Semiconductor. It was a 64-bit MOS p-channel SRAM. The SRAM was the main driver behind any new CMOS-based technology fabrication process since 1959 when CMOS was invented. In 1965 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Nehalem (microarchitecture)
Nehalem is the codename for Intel's 45 nm microarchitecture released in November 2008. It was used in the first-generation of the Intel Core i5 and i7 processors, and succeeds the older Core microarchitecture used on Core 2 processors. The term "Nehalem" comes from the Nehalem River. Nehalem is built on the 45 nm process, is able to run at higher clock speeds, and is more energy-efficient than Penryn microprocessors. Hyper-threading is reintroduced, along with a reduction in L2 cache size, as well as an enlarged L3 cache that is shared among all cores. Nehalem is an architecture that differs radically from Netburst, while retaining some of the latter's minor features. Nehalem later received a die-shrink to 32 nm with Westmere, and was fully succeeded by "second-generation" Sandy Bridge in January 2011. Technology * Cache line block on L2/L3 cache was reduced from 128 bytes in Netburst & Conroe/Penryn to 64 bytes per line in this generation (same size as Yonah and Pe ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel Developer Forum
The Intel Developer Forum (IDF) was a biannual gathering of technologists to discuss Intel products and products based on Intel products. The first IDF was held in 1997. To emphasize the importance of China, the Spring 2007 IDF was held in Beijing instead of San Francisco, and San Francisco and Taipei shared the Fall IDF event in September and October, respectively. Three IDF shows were scheduled in 2008; with the date of IDF San Francisco notably moving to August rather than September. In previous years, events were held in major cities around the world such as San Francisco, Mumbai, Bangalore, Moscow, Cairo, Sao Paulo, Amsterdam, Munich and Tokyo. On April 17, 2017, Intel announced that it would no longer be hosting IDF. As a result of this announcement, IDF17, which was scheduled for August in San Francisco, was canceled. 2007 events * April 17–18, 2007 - Beijing, China * September 18–20, 2007 - San Francisco, United States * October 15–16, 2007 - Taipei, Taiwan 2008 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Xeon
Xeon ( ) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same architecture as regular desktop-grade CPUs, but have advanced features such as support for ECC memory, higher core counts, more PCI Express lanes, support for larger amounts of RAM, larger cache memory and extra provision for enterprise-grade reliability, availability and serviceability (RAS) features responsible for handling hardware exceptions through the Machine Check Architecture. They are often capable of safely continuing execution where a normal processor cannot due to these extra RAS features, depending on the type and severity of the machine-check exception (MCE). Some also support multi-socket systems with two, four, or eight sockets through use of the Ultra Path Interconnect (UPI) bus. Overview The ''Xeon'' brand has been mainta ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
System-on-a-chip
A system on a chip or system-on-chip (SoC ; pl. ''SoCs'' ) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory interfaces, on-chip input/output devices, input/output interfaces, and secondary storage interfaces, often alongside other components such as radio modems and a graphics processing unit (GPU) – all on a single substrate or microchip. It may contain digital, analog, mixed-signal, and often radio frequency signal processing functions (otherwise it is considered only an application processor). Higher-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (such as LPDDR and eUFS or eMMC, respectively) chips, that may be layered on top of the SoC in what's known as a package on package (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may use separate wireless modems. ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Matsushita Electric Industrial Co
Matsushita (written: lit. "below the pine tree") is a Japanese surname. Notable people with the surname include: *Daisuke Matsushita (born 1981), a former Japanese football player *Hiro Matsushita (born 1961), former Japanese Champ Car racing driver, businessman and grandson of Konosuke Matsushita. Chairman of Swift Engineering & Swift Xi *, Japanese handball player *Ko Matsushita, a Japanese conductor and composer * Kohei Matsushita (born 1985), a Japanese football (soccer) player currently playing for Ehime F.C. * Konosuke Matsushita (1894–1989), a Japanese industrialist and founder of Matsushita Electric Industrial Co., Ltd., now known as Panasonic Corporation *Masaharu Matsushita (1912–2012), a Japanese businessman, the second president of Matsushita Electric, and son-in-law of Konosuke Matsushita *Miyuki Matsushita (born 1969), a Japanese voice actress *Moeko Matsushita (born 1982), a Japanese singer and actress *Nao Matsushita (born 1985), a Japanese actress and piani ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
14 Nm Process
The 14 nm process refers to the MOSFET technology node that is the successor to the 22nm (or 20nm) node. The 14nm was so named by the International Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following 22nm was expected to be 16nm. All 14nm nodes use FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology. Samsung Electronics taped out a 14 nm chip in 2014, before manufacturing 10 nm class NAND flash chips in 2013. The same year, SK Hynix began mass-production of 16nm NAND flash, and TSMC began 16nm FinFET production. The following year, Intel began shipping 14nm scale devices to consumers. History Background The basis for sub-20nm fabrication is the FinFET (Fin field-effect transistor), an evolution of the MOSFET transistor. FinFET technology was pioneered by Digh Hisamoto and his team of researchers at Hitachi Central Research Laboratory in 198 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
22 Nm Process
The 22 nm node is the process step following 32 nm in CMOS MOSFET semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22 nm. It was first demonstrated by semiconductor companies for use in RAM memory in 2008. In 2010, Toshiba began shipping 24 nm flash memory chips, and Samsung Electronics began mass-producing 20 nm flash memory chips. The first consumer-level CPU deliveries using a 22 nm process started in April 2012 with the Intel Ivy Bridge processors. The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm (about twice the diameter of a silicon atom), which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point, possibly disturbing Moore's law. The 20-nanometre node is an intermediate half-no ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
32 Nm Process
The 32 nm node is the step following the 45 nm process in CMOS ( MOSFET) semiconductor device fabrication. "32- nanometre" refers to the average half-pitch (i.e., half the distance between identical features) of a memory cell at this technology level. Toshiba produced commercial 32GiB NAND flash memory chips with the 32nm process in 2009. Intel and AMD produced commercial microchips using the 32-nanometre process in the early 2010s. IBM and the Common Platform also developed a 32 nm high-κ metal gate process. Intel began selling its first 32 nm processors using the Westmere architecture on 7 January 2010. The 28-nanometre node was an intermediate half-node die shrink based on the 32-nanometre process. The 32 nm process was superseded by commercial 22 nm technology in 2012. [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Samsung Electronics
Samsung Electronics Co., Ltd. (, sometimes shortened to SEC and stylized as SΛMSUNG) is a South Korean multinational corporation, multinational electronics corporation headquartered in Yeongtong-gu, Suwon, South Korea. It is the pinnacle of the Samsung chaebol, accounting for 70% of the group's revenue in 2012. Samsung Electronics has played a key role in the group's corporate governance due to circular ownership. Samsung Electronics has Assembly line, assembly plants and sales networks in 74 countries and employs around 290,000 people. It is majority-owned by foreign investors. Samsung Electronics is the world's List of largest technology companies by revenue, second-largest technology company by revenue, and its market capitalization stood at US$520.65 billion, the 12th largest in the world. Samsung is a major manufacturer of Electronic component, Electronic Components such as lithium-ion batteries, semiconductors, image sensors, camera modules, and Display device, d ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Low-κ Dielectric
In semiconductor manufacturing, a low-κ is a material with a small relative dielectric constant (κ, kappa) relative to silicon dioxide. Low-κ dielectric material implementation is one of several strategies used to allow continued scaling of microelectronic devices, colloquially referred to as extending Moore's law. In digital circuits, insulating dielectrics separate the conducting parts (wire interconnects and transistors) from one another. As components have scaled and transistors have gotten closer together, the insulating dielectrics have thinned to the point where charge build up and crosstalk adversely affect the performance of the device. Replacing the silicon dioxide with a low-κ dielectric of the same thickness reduces parasitic capacitance, enabling faster switching speeds (in case of synchronous circuits) and lower heat dissipation. In conversation such materials may be referred to as "low-k" (spoken "low-kay") rather than "low-κ" (low-kappa). Low-κ materials In in ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
