Per the
International Technology Roadmap for Semiconductors, the 45 nm process is a
MOSFET
The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which d ...
technology
node referring to the average half-pitch of a memory cell manufactured at around the 2007–2008 time frame.
Matsushita and
Intel started mass-producing 45 nm chips in late 2007, and
AMD started production of 45 nm chips in late 2008, while
IBM,
Infineon,
Samsung, and
Chartered Semiconductor have already completed a common 45 nm process platform. At the end of 2008,
SMIC was the first China-based semiconductor company to move to 45 nm, having licensed the bulk 45 nm process from IBM. In 2008,
TSMC moved on to a 40nm process.
Many critical feature sizes are smaller than the wavelength of light used for
lithography (i.e., 193 nm and 248 nm). A variety of techniques, such as larger lenses, are used to make sub-wavelength features.
Double patterning has also been introduced to assist in shrinking distances between features, especially if dry lithography is used. It is expected that more layers will be patterned with 193 nm wavelength at the 45 nm node. Moving previously loose layers (such as Metal 4 and Metal 5) from 248 nm to 193 nm wavelength is expected to continue, which will likely further drive costs upward, due to difficulties with 193 nm
photoresists.
High-κ dielectric
Chipmakers have initially voiced concerns about introducing new
high-κ materials into the gate stack, for the purpose of reducing
leakage current density. As of 2007, however, both IBM and Intel have announced that they have high-κ dielectric and metal gate solutions, which Intel considers to be a fundamental change in
transistor design.
NEC has also put high-κ materials into production.
Technology demos
* In 2004,
TSMC demonstrated a 0.296-square-micrometre 45 nm
SRAM cell. In 2008, TSMC moved on to a 40 nm process.
* In January 2006, Intel demonstrated a 0.346-square-micrometre 45 nm node
SRAM cell.
* In April 2006, AMD demonstrated a 0.370-square-micrometre 45 nm SRAM cell.
* In June 2006,
Texas Instruments debuted a 0.24-square-micrometre 45 nm SRAM cell, with the help of
immersion lithography
Immersion lithography is a photolithography resolution enhancement technique for manufacturing integrated circuits (ICs) that replaces the usual air gap between the final lens and the wafer surface with a liquid medium that has a refractive inde ...
.
* In November 2006,
UMC announced that it had developed a 45 nm SRAM chip with a cell size of less than 0.25-square-micrometre using immersion lithography and
low-κ dielectrics.
* In 2006, Samsung developed a 40nm process.
The successors to 45 nm technology are
32 nm,
22 nm, and then
14 nm
The 14 nm process refers to the MOSFET technology node that is the successor to the 22nm (or 20nm) node. The 14nm was so named by the International Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following 22nm was expe ...
technologies.
Commercial introduction
Matsushita Electric Industrial Co. started mass production of
system-on-a-chip (SoC) ICs for digital consumer equipment based on 45nm process technology in June 2007.
Intel shipped its first 45nm processor, the
Xeon 5400 series, in November 2007.
Many details about Penryn appeared at the April 2007
Intel Developer Forum. Its successor is called
Nehalem. Important advances include the addition of new instructions (including
SSE4
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, also known as Penryn New Instructions) and new fabrication materials (most significantly a
hafnium-based dielectric).
AMD released its
Sempron II,
Athlon II,
Turion II
AMD Turion is the brand name AMD applies to its x86-64 low-power consumption (''mobile'') processors codenamed ''K8L''. The Turion 64 and Turion 64 X2/Ultra processors compete with Intel's mobile processors, initially the '' Pentium M'' and th ...
and
Phenom II (in generally increasing order of performance), as well as Shanghai
Opteron processors using 45nm process technology in late 2008.
The
Xbox 360 S, released in 2010, has a
Xenon processor fabricated in a 45 nm process.
The
PlayStation 3 Slim model introduced the
Cell Broadband Engine
Cell is a multi-core microprocessor microarchitecture that combines a general-purpose PowerPC core of modest performance with streamlined coprocessing elements which greatly accelerate multimedia and vector processing applications, as well as ma ...
in a 45 nm process.
Example: Intel's 45 nm process
At IEDM 2007, more technical details of Intel's 45 nm process were revealed.
Since immersion lithography is not used here, the lithographic patterning is more difficult. Hence, a line-cutting
double patterning method is used explicitly for this 45 nm process. Also, the use of
high-κ dielectric dielectrics is introduced for the first time, to address gate leakage issues. For the
32 nm node,
immersion lithography
Immersion lithography is a photolithography resolution enhancement technique for manufacturing integrated circuits (ICs) that replaces the usual air gap between the final lens and the wafer surface with a liquid medium that has a refractive inde ...
will begin to be used by Intel.
* 160 nm gate pitch (73% of 65 nm generation)
* 200 nm isolation pitch (91% of 65 nm generation) indicating a slowing of scaling of
isolation distance between transistors
* Extensive use of dummy copper metal and dummy gates
* 35 nm gate length (same as 65 nm generation)
* 1 nm equivalent oxide thickness, with 0.7 nm transition layer
* Gate-last process using dummy polysilicon and damascene metal gate
* Squaring of gate ends using a second photoresist coating
* 9 layers of carbon-doped oxide and
Cu interconnect, the last being a thick "redistribution" layer
* Contacts shaped more like rectangles than circles for
local interconnects In integrated circuits (ICs), interconnects are structures that connect two or more circuit elements (such as transistors) together electrically. The design and layout of interconnects on an IC is vital to its proper function, performance, power eff ...
* Lead-free packaging
* 1.36 mA/μm nFET drive current
* 1.07 mA/μm pFET drive current, 51% faster than 65 nm generation, with higher hole mobility due to increase from 23% to 30% Ge in embedded SiGe stressors
In a 2008 Chipworks reverse-engineering, it was disclosed that the trench contacts were formed as a "Metal-0" layer in tungsten serving as a local interconnect. Most trench contacts were short lines oriented parallel to the gates covering diffusion, while gate contacts where even shorter lines oriented perpendicular to the gates.
It was recently revealed that both the
Nehalem and
Atom microprocessors used
SRAM cells containing eight transistors instead of the conventional six, in order to better accommodate voltage scaling. This resulted in an area penalty of over 30%.
Processors using 45 nm technology
*
Matsushita released the 45 nm
Uniphier in 2007.
*
Wolfdale,
Wolfdale-3M,
Yorkfield
Yorkfield is the code name for some Intel processors sold as Core 2 Quad and Xeon.
In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was Penryn microarchitecture, the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23, repla ...
,
Yorkfield XE and
Penryn Intel processors sold under the
Core 2
Intel Core 2 is the processor family encompassing a range of Intel's consumer 64-bit x86-64 single-, dual-, and quad-core microprocessors based on the Core microarchitecture. The single- and dual-core models are single- die, whereas the quad-cor ...
brand.
*First generation
Intel Core i3, i5 and i7 series processors such as
Clarksfield,
Bloomfield and
Lynnfield.
*
Diamondville,
Pineview are Intel cores with
Hyper-Threading sold under the
Intel Atom brand.
*
AMD Thuban (
Phenom II), Callisto, Heka, Propus, Deneb, Zosma (
Phenom II) and Shanghai (
Opteron) Quad-Core Processors, Regor (
Athlon II) dual core processor
Caspian (
AMD Turion#Turion II Ultra, Turion II) mobile dual core processors.
*The
Xenon processor in the
Xbox 360 S model.
*Sony/Toshiba
Cell Broadband Engine
Cell is a multi-core microprocessor microarchitecture that combines a general-purpose PowerPC core of modest performance with streamlined coprocessing elements which greatly accelerate multimedia and vector processing applications, as well as ma ...
in
PlayStation 3 Slim model – September 2009.
*
Samsung S5PC110, as known as ''Hummingbird''.
*
Texas Instruments OMAP
The OMAP (Open Multimedia Applications Platform) family, developed by Texas Instruments, was a series of image/video processors. They are proprietary system on chips (SoCs) for portable and mobile multimedia applications. OMAP devices generally i ...
3 and 4 series.
*
IBM POWER7 and
z196
*
Fujitsu
is a Japanese multinational information and communications technology equipment and services corporation, established in 1935 and headquartered in Tokyo. Fujitsu is the world's sixth-largest IT services provider by annual revenue, and the la ...
SPARC64 VIIIfx
The SPARC64 V (''Zeus'') is a SPARC V9 microprocessor designed by Fujitsu. The SPARC64 V was the basis for a series of successive processors designed for servers, and later, supercomputers.
The servers series are the SPARC64 V+, VI, VI+, VII, VI ...
series
*The
Wii U "
Espresso" IBM CPU.
References
External links
Panasonic Begins Mass Production of 45-nm Generation SoCIntel 45 nm process is good to goIntel moving to 45nm sooner than expected?An AMD UpdateSlashdot discussion of ''n'' nm process naming
{{sequence
, prev=
65 nm
The 65 nm process is an advanced lithographic node used in volume CMOS (MOSFET) semiconductor fabrication. Printed linewidths (i.e. transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process, while the pitch ...
, next=
32 nm
The 32 nm node is the step following the 45 nm process in CMOS (MOSFET) semiconductor device fabrication. "32-nanometre" refers to the average half-pitch (i.e., half the distance between identical features) of a memory cell (computing), memory cel ...
, list=
CMOS
Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", ) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFE ...
manufacturing processes
*00045
Taiwanese inventions