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An APPLICATION-SPECIFIC INTEGRATED CIRCUIT (ASIC) /ˈeɪsɪk/ , is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. For example, a chip designed to run in a digital voice recorder or a high-efficiency Bitcoin miner is an ASIC. Application-specific standard products (ASSPs) are intermediate between ASICs and industry standard integrated circuits like the 7400 or the 4000 series .

As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC
ASIC
has grown from 5,000 gates to over 100 million. Modern ASICs often include entire microprocessors , memory blocks including ROM , RAM
RAM
, EEPROM , flash memory and other large building blocks. Such an ASIC
ASIC
is often termed a SoC (system-on-chip ). Designers of digital ASICs often use a hardware description language (HDL), such as Verilog or VHDL , to describe the functionality of ASICs.

Field-programmable gate arrays (FPGA) are the modern-day technology for building a breadboard or prototype from standard parts; programmable logic blocks and programmable interconnects allow the same FPGA
FPGA
to be used in many different applications. For smaller designs or lower production volumes, FPGAs may be more cost effective than an ASIC
ASIC
design even in production. The non-recurring engineering (NRE) cost of an ASIC
ASIC
can run into the millions of dollars.

CONTENTS

* 1 History * 2 Standard-cell designs * 3 Gate-array design * 4 Full-custom design * 5 Structured design * 6 Cell libraries, IP-based design, hard and soft macros * 7 Multi-project wafers * 8 See also * 9 References * 10 Sources

HISTORY

The initial ASICs used gate array technology. An early successful commercial application was the gate array circuitry found in the 8-bit ZX81 and ZX Spectrum low-end personal computers, introduced in 1981 and 1982. These were used by Sinclair Research (UK) essentially as a low-cost I/O solution aimed at handling the computer's graphics.

Customization occurred by varying the metal interconnect mask. Gate arrays had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customised by both metal and polysilicon layers. Some base dies include RAM
RAM
elements.

STANDARD-CELL DESIGNS

Main article: Standard cell

In the mid-1980s, a designer would choose an ASIC
ASIC
manufacturer and implement their design using the design tools available from the manufacturer. While third-party design tools were available, there was not an effective link from the third-party design tools to the layout and actual semiconductor process performance characteristics of the various ASIC
ASIC
manufacturers. Most designers ended up using factory-specific tools to complete the implementation of their designs. A solution to this problem, which also yielded a much higher density device, was the implementation of standard cells . Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation delay , capacitance and inductance, that could also be represented in third-party tools. Standard-cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard-cell design fits between Gate Array and Full Custom design in terms of both its non-recurring engineering and recurring component cost.

By the late 1990s, logic synthesis tools became available. Such tools could compile HDL descriptions into a gate-level netlist . Standard-cell integrated circuits (ICs) are designed in the following conceptual stages, although these stages overlap significantly in practice:

* A team of design engineers starts with a non-formal understanding of the required functions for a new ASIC, usually derived from requirements analysis . * The design team constructs a description of an ASIC
ASIC
(application specific integrated circuits) to achieve these goals using an HDL. This process is analogous to writing a computer program in a high-level language. This is usually called the RTL (register-transfer level ) design. * Suitability for purpose is verified by functional verification . This may include such techniques as logic simulation , formal verification , emulation , or creating an equivalent pure software model (see Simics , for example). Each technique has advantages and disadvantages, and often several methods are used. * Logic synthesis transforms the RTL design into a large collection of lower-level constructs called standard cells. These constructs are taken from a standard-cell library consisting of pre-characterized collections of gates (such as 2 input nor, 2 input nand, inverters, etc.). The standard cells are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cells, plus the needed electrical connections between them, is called a gate-level netlist . * The gate-level netlist is next processed by a placement tool which places the standard cells onto a region representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety of specified constraints. * The routing tool takes the physical placement of the standard cells and uses the netlist to create the electrical connections between them. Since the search space is large, this process will produce a “sufficient” rather than “globally optimal” solution. The output is a file which can be used to create a set of photomasks enabling a semiconductor fabrication facility (commonly called a 'fab') to produce physical ICs. * Given the final layout, circuit extraction computes the parasitic resistances and capacitances. In the case of a digital circuit, this will then be further mapped into delay information, from which the circuit performance can be estimated, usually by static timing analysis . This, and other final tests such as design rule checking and power analysis (collectively called signoff) are intended to ensure that the device will function correctly over all extremes of the process, voltage and temperature. When this testing is complete the photomask information is released for chip fabrication.

These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process.

The design steps (or flow) are also common to standard product design. The significant difference is that standard-cell design uses the manufacturer's cell libraries that have been used in potentially hundreds of other design implementations and therefore are of much lower risk than full custom design. Standard cells produce a design density that is cost effective, and they can also integrate IP cores and S RAM
RAM
(Static Random Access Memory) effectively, unlike Gate Arrays.

GATE-ARRAY DESIGN

Microscope photograph of a gate-array ASIC
ASIC
showing the predefined logic cells and custom interconnections. This particular design uses less than 20% of available logic gates.

Gate-array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization —in other words, unconnected. The physical design process then defines the interconnections of the final device. For most ASIC
ASIC
manufacturers, this consists of from two to as many as nine metal layers, each metal layer running perpendicular to the one below it. Non-recurring engineering costs are much lower, as photolithographic masks are required only for the metal layers, and production cycles are much shorter, as metallization is a comparatively quick process.

Gate-array ASICs are always a compromise as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% utilization. Often difficulties in routing the interconnect require migration onto a larger array device with consequent increase in the piece part price. These difficulties are often a result of the layout software used to develop the interconnect.

Pure, logic-only gate-array design is rarely implemented by circuit designers today, having been replaced almost entirely by field-programmable devices, such as field-programmable gate arrays (FPGAs), which can be programmed by the user and thus offer minimal tooling charges non-recurring engineering, only marginally increased piece part cost, and comparable performance. Today, gate arrays are evolving into structured ASICs that consist of a large IP core like a CPU , DSP unit, peripherals , standard interfaces , integrated memories S RAM
RAM
, and a block of reconfigurable, uncommited logic. This shift is largely because ASIC
ASIC
devices are capable of integrating such large blocks of system functionality and "system-on-a-chip" requires far more than just logic blocks.

In their frequent usages in the field, the terms "gate array" and "semi-custom" are synonymous. Process engineers more commonly use the term "semi-custom", while "gate-array" is more commonly used by logic (or gate-level) designers.

FULL-CUSTOM DESIGN

Main article: Full custom Microscope photograph of custom ASIC (486 chipset) showing gate-based design on top and custom circuitry on bottom

By contrast, full-custom ASIC
ASIC
design defines all the photolithographic layers of the device. Full-custom design is used for both ASIC
ASIC
design and for standard product design.

The benefits of full-custom design usually include reduced area (and therefore recurring component cost), performance improvements, and also the ability to integrate analog components and other pre-designed — and thus fully verified — components, such as microprocessor cores that form a system-on-chip.

The disadvantages of full-custom design can include increased manufacturing and design time, increased non-recurring engineering costs, more complexity in the computer-aided design (CAD) system, and a much higher skill requirement on the part of the design team.

For digital-only designs, however, "standard-cell" cell libraries, together with modern CAD systems, can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to "hand-tweak" or manually optimize any performance-limiting aspect of the design.

This is designed by using basic logic gates, circuits or layout specially for a design.

STRUCTURED DESIGN

Main article: Structured ASIC platform

Structured ASIC
ASIC
design (also referred to as "platform ASIC
ASIC
design"), is a relatively new term in the industry, resulting in some variation in its definition. However, the basic premise of a structured ASIC
ASIC
is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC, by virtue of there being pre-defined metal layers (thus reducing manufacturing time) and pre-characterization of what is on the silicon (thus reducing design cycle time). One definition states that In a "structured ASIC" design, the logic mask-layers of a device are predefined by the ASIC vendor (or in some cases by a third party). Design differentiation and customization is achieved by creating custom metal layers that create custom connections between predefined lower-layer logic elements. "Structured ASIC" technology is seen as bridging the gap between field-programmable gate arrays and "standard-cell" ASIC
ASIC
designs. Because only a small number of chip layers must be custom-produced, "structured ASIC" designs have much smaller non-recurring expenditures (NRE) than "standard-cell" or "full-custom" chips, which require that a full mask set be produced for every design.

This is effectively the same definition as a gate array. What makes a structured ASIC
ASIC
different is that in a gate array, the predefined metal layers serve to make manufacturing turnaround faster. In a structured ASIC, the use of predefined metallization is primarily to reduce cost of the mask sets as well as making the design cycle time significantly shorter. For example, in a cell-based or gate-array design the user must often design power, clock, and test structures themselves; these are predefined in most structured ASICs and therefore can save time and expense for the designer compared to gate-array. Likewise, the design tools used for structured ASIC
ASIC
can be substantially lower cost and easier (faster) to use than cell-based tools, because they do not have to perform all the functions that cell-based tools do. In some cases, the structured ASIC
ASIC
vendor requires that customized tools for their device (e.g., custom physical synthesis) be used, also allowing for the design to be brought into manufacturing more quickly.

CELL LIBRARIES, IP-BASED DESIGN, HARD AND SOFT MACROS

Cell libraries of logical primitives are usually provided by the device manufacturer as part of the service. Although they will incur no additional cost, their release will be covered by the terms of a non-disclosure agreement (NDA) and they will be regarded as intellectual property by the manufacturer. Usually their physical design will be pre-defined so they could be termed "hard macros".

What most engineers understand as "intellectual property " are IP cores , designs purchased from a third-party as sub-components of a larger ASIC. They may be provided as an HDL description (often termed a "soft macro"), or as a fully routed design that could be printed directly onto an ASIC's mask (often termed a hard macro). Many organizations now sell such pre-designed cores — CPUs, Ethernet, USB or telephone interfaces — and larger organizations may have an entire department or division to produce cores for the rest of the organization. Indeed, the wide range of functions now available is a result of the phenomenal improvement in electronics in the late 1990s and early 2000s; as a core takes a lot of time and investment to create, its re-use and further development cuts product cycle times dramatically and creates better products. Additionally, organizations such as OpenCores are collecting free IP cores, paralleling the open source software movement in hardware design.

Soft macros are often process-independent (i.e. they can be fabricated on a wide range of manufacturing processes and different manufacturers). Hard macros are process-limited and usually further design effort must be invested to migrate (port) to a different process or manufacturer.

MULTI-PROJECT WAFERS

Some manufacturers offer multi-project wafers (MPW) as a method of obtaining low cost prototypes. Often called shuttles, these MPW, containing several designs, run at regular, scheduled intervals on a "cut and go" basis, usually with very little liability on the part of the manufacturer. The contract involves the assembly and packaging of a handful of devices. The service usually involves the supply of a physical design database (i.e. masking information or pattern generation (PG) tape). The manufacturer is often referred to as a "silicon foundry" due to the low involvement it has in the process.

SEE ALSO

* Application-specific instruction-set processor (ASIP) * Complex programmable logic device (CPLD) * Electronic design automation (EDA or ECAD) * Field-programmable gate array (FPGA) * Multi-project chip (MPC) * Very-large-scale integration (VLSI) * System-on-a-chip (SoC)

REFERENCES

* Smith, Michael John Sebastian (1997). _Application-Specific Integrated Circuits_. Addison-Wesley Professional. ISBN 9780201500226 .

SOURCES

* Barr, Keith (2007). _ ASIC
ASIC
Design in the Silicon Sandbox: A Complete Guide to Building Mixed-Signal Integrated Circuits_. McGraw Hill Professional. ISBN 9780071481618 . * Kevin Morris (23 November 2003). "Cost-Reduction Quagmire: Structured ASIC
ASIC
and Other Options". _ FPGA
FPGA
and Programmable Logic Journal_. * Anthony Cataldo (26 March 2002). " Xilinx
Xilinx
looks to ease path to custom FPGAs". _EE Times_. CMP Media, LLC. * " Xilinx
Xilinx
intros next-gen EasyPath FPGAs priced below structured ASICs". _EDP Weekly's IT Monitor_. Millin Publishing, Inc. 18 October 2004. * Golshan, K. (2007). _Physical design essentials: an ASIC
ASIC
design implementation perspective._ New York: Springer. ISBN 0-387-36642-3 .

* v * t * e

CPU technologies

ARCHITECTURE

* Turing machine * Post– Turing machine * Universal Turing machine * Quantum Turing machine * Belt machine * Stack machine * Register machine * Counter machine * Pointer machine * Random access machine * Random access stored program machine * Finite-state machine * Queue automaton * Von Neumann * Harvard (Modified ) * Dataflow * TTA * Cellular

* Artificial neural network
Artificial neural network

* Machine learning * Deep learning
Deep learning
* Neural processing unit (NPU)

* Convolutional neural network
Convolutional neural network
* Load/store architecture * Register memory architecture * Register register architecture * Endianness * FIFO * Zero-copy * NUMA * HUMA * HSA * Heterogeneous computing * Parallel computing * Amorphous computing * Reconfigurable computing * Cognitive computing * DNA computing
DNA computing
* Peptide computing * Chemical computing * Organic computing * Wetware computer * Quantum computing * Neuromorphic computing * Optical computing * Reversible computing * Unconventional computing * Hypercomputation * Ternary computer * Symmetric multiprocessing (SMP) * Asymmetric multiprocessing (AMP) * Cache hierarchy * Memory
Memory
hierarchy

ISA TYPES

* ASIP * CISC * RISC * EDGE (TRIPS ) * VLIW (EPIC ) * MISC * OISC * NISC * ZISC * Comparison

ISAS

* x86 * z/Architecture * ARM * MIPS * Power Architecture
Power Architecture
( PowerPC ) * SPARC
SPARC
* VISC * Mill * Itanium
Itanium
( IA-64 ) * Alpha * Prism * SuperH * Clipper * VAX
VAX
* Unicore * PA-RISC
PA-RISC
* MicroBlaze

WORD SIZE

* 1-bit * 2-bit * 4-bit * 8-bit * 9-bit * 10-bit * 12-bit * 15-bit * 16-bit * 1 8-bit * 22-bit * 2 4-bit * 25-bit * 26-bit * 27-bit * 31-bit * 32-bit * 33-bit * 3 4-bit * 36-bit * 39-bit * 40-bit * 4 8-bit * 50-bit * 60-bit * 6 4-bit * 12 8-bit * 256-bit * 5 12-bit * Variable

EXECUTION

* Instruction pipelining
Instruction pipelining

* Bubble * Operand forwarding

* Out-of-order execution

* Register renaming

* Speculative execution

* Branch predictor * Memory
Memory
dependence prediction

* Hazards

PARALLEL LEVEL

* Bit

* Bit-serial * Word

* Instruction

* Pipelining

* Scalar * Superscalar

* Task

* Thread * Process

* Data

* Vector

* Memory
Memory

MULTITHREADING

* Temporal * Simultaneous (SMT) ( Hyper-threading ) * Speculative (SpMT) * Preemptive * Cooperative * Clustered Multi-Thread (CMT) * Hardware scout

FLYNN\\'S TAXONOMY

* SISD
SISD
* SIMD
SIMD
( SWAR ) * SIMT * MISD
MISD

* MIMD
MIMD

* SPMD

* Addressing mode

CPU PERFORMANCE

* Instructions per second (IPS) * Instructions per clock (IPC) * Cycles per instruction (CPI) * Floating-point operations per second (FLOPS) * Transactions per second (TPS) * SUPS * Performance per watt
Performance per watt
* Orders of magnitude (computing) * Cache performance measurement and metric

CORE COUNT

* Single-core processor * Multi-core processor * Manycore processor

TYPES

* Central processing unit
Central processing unit
(CPU) * GPGPU * AI accelerator * Vision processing unit (VPU) * Vector processor * Barrel processor * Stream processor * Digital signal processor (DSP) * I/O processor/DMA controller * Network processor
Network processor
* Baseband processor * Physics processing unit (PPU) * Coprocessor * Secure cryptoprocessor
Secure cryptoprocessor
* ASIC
ASIC
* FPGA
FPGA
* FPOA * CPLD * Microcontroller * Microprocessor * Mobile processor * Notebook processor * Ultra-low-voltage processor * Multi-core processor * Manycore processor * Tile processor * Multi-chip module (MCM) * Chip stack multi-chip modules * System on a chip
System on a chip
(SoC) * Network on a chip (NoC) * Multiprocessor system-on-chip (MPSoC) * Programmable System-on-Chip ( PSoC
PSoC
)

COMPONENTS

* Execution unit (EU) * Arithmetic logic unit (ALU) * Address generation unit (AGU) * Floating-point unit (FPU) * Load-store unit (LSU) * Fixed-point unit (FXU) * Vector unit (VU) * Branch predictor * Branch execution unit (BEU) * Instruction Decoder * Instruction Scheduler * Instruction Fetch Unit * Instruction Dispatch Unit * Instruction Sequencing Unit * Unified Reservation Station * Barrel shifter
Barrel shifter
* Uncore * Sum addressed decoder (SAD) * Front-side bus
Front-side bus
* Back-side bus * Northbridge (computing) * Southbridge (computing) * Adder (electronics)
Adder (electronics)
* Binary multiplier * Binary decoder
Binary decoder
* Address decoder * Multiplexer * Demultiplexer
Demultiplexer
* Registers * Cache * Memory
Memory
management unit (MMU) * Input–output memory management unit (IOMMU) * Integrated Memory
Memory
Controller (IMC) * Power Management Unit (PMU) * Translation lookaside buffer (TLB) * Stack engine * Register file * Processor register * Hardware register * Memory
Memory
buffer register (MBR) * Program counter
Program counter
* Microcode ROM * Datapath * Control unit * Instruction unit * Re-order buffer * Data buffer * Write buffer * Coprocessor * Electronic switch * Electronic circuit * Integrated circuit * Three-dimensional integrated circuit * Boolean circuit * Digital circuit * Analog circuit * Mixed-signal integrated circuit * Power management integrated circuit * Quantum circuit
Quantum circuit

* Logic gate

* Combinational logic * Sequential logic * Emitter-coupled logic (ECL) * Transistor–transistor logic
Transistor–transistor logic
(TTL) * Glue logic

* Quantum gate * Gate array
Gate array
* Counter (digital) * Bus (computing) * Semiconductor device
Semiconductor device
* Clock rate * CPU multiplier * Vision chip * Memristor

Power management

* APM * ACPI * Dynamic frequency scaling * Dynamic voltage scaling * Clock gating

Hardware security

* Non-executable memory (NX bit) * Bounds checking ( Intel
Intel
MPX) * Intel Secure Key * Hardware restriction (firmware ) * Software Guard Extensions ( Intel
Intel
SGX) * Trusted Execution Technology * OmniShield * Trusted Platform Module (TPM) * Secure cryptoprocessor
Secure cryptoprocessor
* Hardware security module * Hengzhi chip

RELATED

* History of general-purpose CPUs

* v * t * e

Programmable logic

CONCEPTS

* ASIC * SOC

* FPGA
FPGA

* Logic block

* CPLD * EPLD * PLA * PAL * GAL * PSoC
PSoC

* Reconfigurable computing

* Xputer

* Soft microprocessor * Circuit underutilization

LANGUAGES

* Verilog

* A * AMS

* VHDL

* AMS * VITAL

* System Verilog

* DPI

* SystemC * AHDL * Handel-C * PSL * UPF * PALASM * ABEL * CUPL * OpenVera * C to HDL * Flow to HDL * MyHDL * JHDL * ELLA

COMPANIES

* Accellera
Accellera
* Actel
Actel
* Achronix * AMD * Aldec * Altera
Altera
* Atmel * Cadence * Cypress * Duolog * Forte * Intel
Intel
* Lattice * National * Mentor Graphics * Microsemi * Signetics

* Synopsys

* Magma * Virage Logic

* Texas Instruments * Tabula * Xilinx
Xilinx

PRODUCTS

HARDWARE

* iCE * Stratix * Virtex

SOFTWARE

* Altera
Altera
Quartus * Xilinx
Xilinx
ISE * Xilinx
Xilinx
Vivado * ModelSim * VTR * Simulators

IP

PROPRIETARY

* ARC * LEON
LEON
* LatticeMico8 * MicroBlaze * PicoBlaze * Nios * Nios II

OPEN-SOURCE

* JOP * LatticeMico32 * OpenCores

* OpenRISC
OpenRISC

* 1200

* RISC-V * Zet

AUTHORITY CONTROL

* GND : 4122250-7

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