Zen 4 is the
codename
A code name, call sign or cryptonym is a Code word (figure of speech), code word or name used, sometimes clandestinely, to refer to another name, word, project, or person. Code names are often used for military purposes, or in espionage. They may ...
for a
CPU microarchitecture by
AMD
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactur ...
, released on September 27, 2022.
It is the successor to
Zen 3
Zen 3 is the codename for a CPU microarchitecture by AMD, released on November 5, 2020. It is the successor to Zen 2 and uses TSMC's 7 nm process, 7 nm process for the chiplets and GlobalFoundries's 14 nm process, 14 nm process for the I/O die on ...
and uses
TSMC
Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational corporation, multinational semiconductor contract manufacturing and design company. It is the world's most valuable semicon ...
's
N5 process for CCDs.
Zen 4 powers
Ryzen 7000
Ryzen ( ) is a brand of multi-core x86-64 microprocessors designed and marketed by AMD for desktop, mobile, server, and embedded platforms based on the Zen microarchitecture. It consists of central processing units (CPUs) marketed for mainst ...
mainstream desktop processors (codenamed "Raphael") and will be used in high-end mobile processors (codenamed "Dragon Range"), thin & light mobile processors (codenamed "Phoenix"), as well as
Epyc
Epyc is a brand of multi-core x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets. Epyc processors share ...
9004 server processors (codenamed "Genoa" and "Bergamo").
Features
Like its predecessor, Zen 4 in its Desktop Ryzen variants features one or two Core Complex Dies (CCDs) built on TSMC's 5 nm process and one I/O die built on 6 nm.
Previously, the I/O die on Zen 3 was built on
GlobalFoundries
GlobalFoundries Inc. (GF or GloFo) is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, th ...
'
14 nm process. Zen 4's I/O die includes integrated
RDNA 2
RDNA ( Radeon DNA) is a graphics processing unit (GPU) microarchitecture and accompanying instruction set architecture developed by Advanced Micro Devices (AMD). It is the successor to their Graphics Core Next (GCN) microarchitecture/instructi ...
graphics for the first time on any Zen architecture. Zen 4 marks the first utilization of the 5 nm process for x86-based desktop processors.
On desktop and server platforms, Zen 4 has moved from
DDR4
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth (" double data rate") interface.
Released to the market in 2014, it is a variant of dynamic ra ...
to
DDR5
Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) ...
memory; DDR4 is not supported. Additionally, Zen 4 supports new
AMD EXPO SPD profiles for more comprehensive memory tuning and overclocking by the RAM manufacturers. Unlike
Intel XMP, AMD EXPO is marketed as an open, license and royalty-free standard for describing memory kit parameters, such as operating frequency, timings and voltages. It allows to encode a wider set of timings to achieve better performance and compatibility. However, XMP memory profiles are still supported.
EXPO can also support Intel processors.
All Ryzen desktop processors feature 28 (24 + 4)
PCIe 5.0 lanes. This means that a discrete GPU can be connected by 16 PCIe lanes or two GPUs by 8 PCIe lanes each. Additionally, there are now 2 x 4 lane PCIe interfaces, most often used for M.2 storage devices. Whether the lanes connecting the GPUs in the mechanical x16 slots are executed as PCIe 4.0 or PCIe 5.0 can be configured by the mainboard manufacturers. Finally, 4 PCIe 5.0 lanes are reserved for connecting the south bridge chip or chipset.
Zen 4 is the first AMD microarchitecture to support
AVX-512 AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and implemented in Intel's Xeon Phi x200 (Knights Landing) and Skylake-X CPUs; thi ...
instruction set extension. Most 512-bit vector instructions are split in two and executed by the 256-bit
SIMD
Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal (part of the hardware design) and it can be directly accessible through an instruction set architecture (ISA), but it should ...
execution units internally. The two halves execute in parallel on a pair of execution units and are still tracked as a single micro-OP (except for stores), which means the execution latency isn't doubled compared to 256-bit vector instructions. There are four 256-bit execution units, which gives a maximum throughput of two 512-bit vector instructions per clock cycle, e.g. one multiplication and one addition. The maximum number of instructions per clock cycle is doubled for vectors of 256 bits or less. Load and store units are also 256 bits each, retaining the throughput of up to two 256-bit loads or one store per cycle that was supported by
Zen 3
Zen 3 is the codename for a CPU microarchitecture by AMD, released on November 5, 2020. It is the successor to Zen 2 and uses TSMC's 7 nm process, 7 nm process for the chiplets and GlobalFoundries's 14 nm process, 14 nm process for the I/O die on ...
. This translates to up to one 512-bit load per cycle or one 512-bit store per two cycles.
Other features and improvements, compared to
Zen 3
Zen 3 is the codename for a CPU microarchitecture by AMD, released on November 5, 2020. It is the successor to Zen 2 and uses TSMC's 7 nm process, 7 nm process for the chiplets and GlobalFoundries's 14 nm process, 14 nm process for the I/O die on ...
, include:
* L1 Branch Target Buffer (BTB) size increased by 50%, to 1.5K entries. Each entry is now able to store up to two branch targets, provided that the first branch is a conditional branch and the second branch is located within the same aligned 64-byte cache line as the first one.
* L2 BTB increased to 7K entries.
* Improved direct and indirect branch predictors.
* OP cache size increased by 68%, to 6.75K OPs. The OP cache is now able to produce up to 9 macro-OPs per cycle (up from 6).
* Reorder buffer (ROB) is increased by 25%, to 320 instructions.
* Integer register file increased to 224 registers, FP/vector register file increased to 192 registers. FP/vector register file widened to 512 bits to support AVX-512. Added a new mask register file, capable of storing 68 mask registers.
* Load queue size increased by 22%, to 88 pending loads.
*
L2 cache
A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, whic ...
is doubled, from 512 KiB to 1 MiB per core, 8-way.
* Automatic IBRS, where indirect branch restricted speculation mode is automatically enabled and disabled when control enters and leaves
Ring 0 (kernel mode). This reduces the cost of user/kernel mode transitions.
* ~13%
IPC increase on average.
* Up to 5.7 GHz max core frequency.
* Memory speeds up to DDR5-5200 are officially supported.
* In
Ryzen 7000
Ryzen ( ) is a brand of multi-core x86-64 microprocessors designed and marketed by AMD for desktop, mobile, server, and embedded platforms based on the Zen microarchitecture. It consists of central processing units (CPUs) marketed for mainst ...
desktop processors, the integrated GPU contains two RDNA 2 Compute Units running at up to 2.2 GHz.
Products
Desktop
On August 29, 2022, AMD announced four Zen 4-based Ryzen 7000 series desktop processors. The four Ryzen 7000 processors set to be launched on September 27, 2022 consists of one Ryzen 5, one Ryzen 7, and two Ryzen 9 CPUs and they feature between 6 and 16 cores.
Server
Genoa
On November 10, 2022, AMD launched the fourth generation of Epyc server and data center processors based on the Zen 4 microarchitecture, codenamed Genoa. Genoa features between 16 and 96 Zen 4 cores, alongside
PCIe 5.0 and
DDR5
Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) ...
, designed for enterprise and cloud datacenter clients.
Zen 4c
Zen 4c is variant on Zen 4 featuring smaller Zen 4 cores with lower clock frequencies, power usage, reduced
L3 cache
A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, whic ...
, and is intended to fit a greater number of cores in a given space. Zen 4c cores will feature in
AMD
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactur ...
's
Epyc
Epyc is a brand of multi-core x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets. Epyc processors share ...
server processors codenamed Bergamo coming in 2023. Bergamo will feature up to 128 cores and 256 threads. Zen 4c's smaller cores and higher core counts are designed for heavily multi-threaded workloads such as cloud computing.
References
{{AMD processor roadmap
AMD microarchitectures
AMD x86 microprocessors
Computer-related introductions in 2022
x86 microarchitectures