x86 instruction set

The x86 instruction set refers to the set of instructions that x86-compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.

The x86 instruction set has been extended several times, introducing wider registers and datatypes as well as new functionality.

x86 integer instructions

Below is the full 8086/ 8088 instruction set of Intel (81 instructions total). These instructions are also available in 32-bit mode, in which they operate on 32-bit registers (eax, ebx, etc.) and values instead of their 16-bit (ax, bx, etc.) counterparts. The updated instruction set is grouped according to architecture ( i186, i286, i386, i486, i586/ i686) and is referred to as (32-bit) x86 and (64-bit) x86-64 (also known as AMD64).

Original 8086/8088 instructions

This is the original instruction set. In the 'Notes' column, ''r'' means ''register'', ''m'' means ''memory address'' and ''imm'' means ''immediate'' (i.e. a value).

Added in specific processors

Added with 80186/ 80188

Added with 80286

The new instructions added in 80286 add support for x86 protected mode. Some but not all of the instructions are available in real mode as well.

Added with 80386

The 80386 added support for 32-bit operation to the x86 instruction set. This was done by widening the general-purpose registers to 32 bits and introducing the concepts of ''OperandSize'' and ''AddressSize'' – most instruction forms that would previously take 16-bit data arguments were given the ability to take 32-bit arguments by setting their OperandSize to 32 bits, and instructions that could take 16-bit address arguments were given the ability to take 32-bit address arguments by setting their AddressSize to 32 bits. (Instruction forms that work on 8-bit data continue to be 8-bit regardless of OperandSize. Using a data size of 16 bits will cause only the bottom 16 bits of the 32-bit general-purpose registers to be modified – the top 16 bits are left unchanged.)

The default OperandSize and AddressSize to use for each instruction is given by the D bit of the segment descriptor of the current code segment - D=0 makes both 16-bit, D=1 makes both 32-bit. Additionally, they can be overridden on a per-instruction basis with two new instruction prefixes that were introduced in the 80386:
* 66h: OperandSize override. Will change OperandSize from 16-bit to 32-bit if CS.D=0, or from 32-bit to 16-bit if CS.D=1.
* 67h: AddressSize override. Will change AddressSize from 16-bit to 32-bit if CS.D=0, or from 32-bit to 16-bit if CS.D=1.

The 80386 also introduced the two new segment registers FS and GS as well as the x86 control, debug and test registers.

The new instructions introduced in the 80386 can broadly be subdivided into two classes:
* Pre-existing opcodes that needed new mnemonics for their 32-bit OperandSize variants (e.g. CWDE, LODSD)
* New opcodes that introduced new functionality (e.g. SHLD, SETcc)
For instruction forms where the operand size can be inferred from the instruction's arguments (e.g. ADD EAX,EBX can be inferred to have a 32-bit OperandSize due to its use of EAX as an argument), new instruction mnemonics are not needed and not provided.

,
, In-circuit emulation breakpoint.

Performs software interrupt #1 if executed when not using in-circuit emulation.
, rowspan="7"
, -
,
,
, rowspan="4" , User Move – perform data moves that can access user memory while in In-circuit emulation HALT mode.

Performs same operation as MOV if executed when not doing in-circuit emulation.
, -
,
,
, -
,
,
, -
,
,

, -
,
,
, Bitfield extract (early 386 only).
, -
,
,
, Bitfield insert (early 386 only).
, -
,
,
, Load all CPU registers from a 296-byte data structure starting at ES:EDI, including "hidden" part of segment descriptor registers.
,

Added with 80486

Added in P5/ P6-class processors

Integer/system instructions that were not present in the basic 80486 instruction set, but were added in various x86 processors prior to the introduction of SSE. ( Discontinued instructions are not included.)

Added as instruction set extensions

Added with

x86-64

These instructions can only be encoded in 64 bit mode. They fall in four groups:

* original instructions that reuse existing opcodes for a different purpose (MOVSXD replacing ARPL)
* original instructions with new opcodes (SWAPGS)
* existing instructions extended to a 64 bit address size (JRCXZ)
* existing instructions extended to a 64 bit operand size (remaining instructions)

Most instructions with a 64 bit operand size encode this using a REX.W prefix; in the absence of the REX.W prefix,
the corresponding instruction with 32 bit operand size is encoded. This mechanism also applies to most other instructions with 32 bit operand
size. These are not listed here as they do not gain a new mnemonic in Intel syntax when used with a 64 bit operand size.

Bit manipulation extensions

Bit manipulation instructions. For all of the VEX-encoded instructions defined by BMI1 and BMI2, the operand size may be 32 or 64 bits, controlled by the VEX.W bit – none of these instructions are available in 16-bit variants. The VEX-encoded instructions are not available in Real Mode and Virtual-8086 mode - other than that, the bit manipulation instructions are available in all operating modes on supported CPUs.

Added with Intel TSX

Added with Intel CET

Intel CET (Control-Flow Enforcement Technology) adds two distinct features to help protect against security exploits such as return-oriented programming: a shadow stack (CET_SS), and indirect branch tracking (CET_IBT).

Added with XSAVE

The XSAVE instruction set extensions are designed to save/restore CPU extended state (typically for the purpose of context switching) in a manner that can be extended to cover new instruction set extensions without the OS context-switching code needing to understand the specifics of the new extensions. This is done by defining a series of ''state-components'', each with a size and offset within a given save area, and each corresponding to a subset of the state needed for one CPU extension or another. The EAX=0Dh CPUID leaf is used to provide information about which state-components the CPU supports and what their sizes/offsets are, so that the OS can reserve the proper amount of space and set the associated enable-bits.

Added with other cross-vendor extensions

Added with other Intel-specific extensions

Added with other AMD-specific extensions

x87 floating-point instructions

The x87 coprocessor, if present, provides support for floating-point arithmetic. The coprocessor provides eight data registers, each holding one 80-bit floating-point value (1 sign bit, 15 exponent bits, 64 mantissa bits) – these registers are organized as a stack, with the top-of-stack register referred to as "st" or "st(0)", and the other registers referred to as st(1), st(2), ...st(7). It additionally provides a number of control and status registers, including "PC" (precision control, to control whether floating-point operations should be rounded to 24, 53 or 64 mantissa bits) and "RC" (rounding control, to pick rounding-mode: round-to-zero, round-to-positive-infinity, round-to-negative-infinity, round-to-nearest-even) and a 4-bit condition code register "CC", whose four bits are individually referred to as C0, C1, C2 and C3). Not all of the arithmetic instructions provided by x87 obey PC and RC.

Original

8087 instructions

, -
, }
, -
! colspan="3" , x87 Integer Load/Store Instructions , , precision
control , , rounding
control
, -
, rowspan="3" , Load signed integer value onto stack from memory, with conversion to floating-point
, FILD m16 , , DF /0 , , rowspan="3" , , rowspan="3"
, -
, FILD m32 , , DB /0
, -
, FILD m64 , , DF /5
, -
, rowspan="2" , Store top-of-stack value to memory, with conversion to signed integer
, FIST m16 , , DF /2 , , rowspan="2" , , rowspan="2"
, -
, FIST m32 , , DB /2
, -
, rowspan="3" , Store top-of-stack value to memory, with conversion to signed integer, then pop stack
, FISTP m16 , , DF /3 , , rowspan="3" , , rowspan="3"
, -
, FISTP m32 , , DB /3
, -
, FISTP m64 , , DF /7
, -
, Load 18-digit Binary-Coded-Decimal integer value onto stack from memory, with conversion to floating-point
, FBLD m80
, DF /4 , , , ,
, -
, Store top-of-stack value to memory, with conversion to 18-digit Binary-Coded-Decimal integer, then pop stack
, FBSTP m80 , , DF /6 , , , ,
, -
! colspan="3" , x87 Basic Arithmetic Instructions , , precision
control , , rounding
control
, -
, rowspan="4" , Floating-point add
:
, FADD m32 , , D8 /0 , , rowspan="4" , , rowspan="4"
, -
, FADD m64 , , DC /0
, -
, FADD st,st(i) , , D8 C0+i
, -
, FADD st(i),st , , DC C0+i
, -
, rowspan="4" , Floating-point multiply
:
, FMUL m32 , , D8 /1 , , rowspan="4" , , rowspan="4"
, -
, FMUL m64 , , DC /1
, -
, FMUL st,st(i) , , D8 C8+i
, -
, FMUL st(i),st , , DC C8+i
, -
, rowspan="4" , Floating-point subtract
:
, FSUB m32 , , D8 /4 , , rowspan="4" , , rowspan="4"
, -
, FSUB m64 , , DC /4
, -
, FSUB st,st(i) , , D8 E0+i
, -
, FSUB st(i),st , , DC E8+i
, -
, rowspan="4" , Floating-point reverse subtract
:
, FSUBR m32 , , D8 /5 , , rowspan="4" , , rowspan="4"
, -
, FSUBR m64 , , DC /5
, -
, FSUBR st,st(i) , , D8 E8+i
, -
, FSUBR st(i),st , , DC E0+i
, -
, rowspan="4" , Floating-point divide
:
, FDIV m32 , , D8 /6 , , rowspan="4" , , rowspan="4"
, -
, FDIV m64 , , DC /6
, -
, FDIV st,st(i) , , D8 F0+i
, -
, FDIV st(i),st , , DC F8+i
, -
, rowspan="4" , Floating-point reverse divide
:
, FDIVR m32 , , D8 /7 , , rowspan="4" , , rowspan="4"
, -
, FDIVR m64 , , DC /7
, -
, FDIVR st,st(i) , , D8 F8+i
, -
, FDIVR st(i),st , , DC F0+i
, -
, rowspan="4" , Floating-point compare
:
Same operation as subtract, except that it updates the x87 CC status register instead of any of the FPU stack registers
, FCOM m32 , , D8 /2 , , rowspan="4" , , rowspan="4"
, -
, FCOM m64 , , DC /2
, -
, rowspan="2" , FCOM st(i)
, D8 D0+i
, -
, }
, -
! colspan="3" , x87 Basic Arithmetic Instructions with Stack Pop , , precision
control , , rounding
control
, -
, Floating-point add and pop
, FADDP st(i),st , , DE C0+i , , , ,
, -
, Floating-point multiply and pop
, FMULP st(i),st , , DE C8+i , , , ,
, -
, Floating-point subtract and pop
, FSUBP st(i),st , , DE E8+i , , , ,
, -
, Floating-point reverse-subtract and pop
, FSUBRP st(i),st , , DE E0+i , , , ,
, -
, Floating-point divide and pop
, FDIVP st(i),st , , DE F8+i , , , ,
, -
, Floating-point reverse-divide and pop
, FDIVRP st(i),st , , DE F0+i , , , ,
, -
, rowspan="5" , Floating-point compare and pop
, FCOMP m32 , , D8 /3 , , rowspan="5" , , rowspan="5"
, -
, FCOMP m64 , , DC /3
, -
, rowspan="3" , FCOMP st(i)
, D8 D8+i
, -
, }
, -
, }
, -
, Floating-point compare to st(1), then pop twice
, FCOMPP , , DE D9 , , , ,
, -
! colspan="3" , x87 Basic Arithmetic Instructions with Integer Source Argument , , precision
control , , rounding
control
, -
, rowspan="2" , Floating-point add by integer
, FIADD m16 , , DA /0 , , rowspan="2" , , rowspan="2"
, -
, FIADD m32 , , DE /0
, -
, rowspan="2" , Floating-point multiply by integer
, FIMUL m16 , , DA /1 , , rowspan="2" , , rowspan="2"
, -
, FIMUL m32 , , DE /1
, -
, rowspan="2" , Floating-point subtract by integer
, FISUB m16 , , DA /4 , , rowspan="2" , , rowspan="2"
, -
, FISUB m32 , , DE /4
, -
, rowspan="2" , Floating-point reverse-subtract by integer
, FISUBR m16 , , DA /5 , , rowspan="2" , , rowspan="2"
, -
, FISUBR m32 , , DE /5
, -
, rowspan="2" , Floating-point divide by integer
, FIDIV m16 , , DA /6 , , rowspan="2" , , rowspan="2"
, -
, FIDIV m32 , , DE /6
, -
, rowspan="2" , Floating-point reverse-divide by integer
, FIDIVR m16 , , DA /7 , , rowspan="2" , , rowspan="2"
, -
, FIDIVR m32 , , DE /7
, -
, rowspan="2" , Floating-point compare to integer
, FICOM m16 , , DA /2 , , rowspan="2" , , rowspan="2"
, -
, FICOM m32 , , DE /2
, -
, rowspan="2" , Floating-point compare to integer, and stack pop
, FICOMP m16
, DA /3 , , rowspan="2" , , rowspan="2"
, -
, FICOMP m32
, DE /3
, -
! colspan="3" , x87 Additional Arithmetic Instructions , , precision
control , , rounding
control
, -
, Floating-point change sign
, FCHS , , D9 E0 , , , ,
, -
, Floating-point absolute value
, FABS , , D9 E1 , , , ,
, -
, Floating-point compare top-of-stack value to 0
, FTST , , D9 E4 , , , ,
, -
, Classify top-of-stack st(0) register value.
The classification result is stored in the x87 CC register.
, FXAM , , D9 E5 , , , ,
, -
, Split the st(0) value into two values and representing the exponent and mantissa of st(0).
The split is done such that $M*2^=st(0)$, where is an integer and is a number whose absolute value is within the range $1\leq\left, M\<2$.  
st(0) is then replaced with , after which is pushed onto the stack.
, FXTRACT , , D9 F4 , , , ,
, -
, Floating-point partial remainder (not IEEE 754 compliant):$Q \leftarrow \mathtt\left(\frac\right)$$st(0) \leftarrow st(0) - st(1)*Q$

, FPREM , , D9 F8 , , , ,
, -
, Floating-point square root
, FSQRT , , D9 FA , , , ,
, -
, Floating-point round to integer
, FRNDINT , , D9 FC , , , ,
, -
, Floating-point power-of-2 scaling. Rounds the value of st(1) to integer with round-to-zero, then uses it as a scale factor for st(0):$st(0) \leftarrow st(0)*2^$
, FSCALE , , D9 FD , , , ,
, -
! colspan="3" , !! colspan="2" ,
, -
! colspan="3" , x87 Transcendental Instructions !! colspan="2" , Source operand
range restriction
, -
, Base-2 exponential minus 1, with extra precision for st(0) close to 0:$st(0) \leftarrow 2^ - 1$
, F2XM1 , , D9 F0
, colspan="2" , 8087: $0\leq st(0)\leq\frac$
80387: $-1\leq st(0)\leq1$
, -
, Base-2 Logarithm and multiply:
$st(1) \leftarrow st(1)*\log_\left(st(0)\right)$followed by stack pop
, FYL2X
, D9 F1 , , colspan="2" , no restrictions
, -
, Partial Tangent: Computes from st(0) a pair of values and , such that$\tan\left(st(0)\right)=\frac$The value replaces the top-of-stack value, and then is pushed onto the stack.
On 80387 and later x87, but not original 8087, is always 1.0
, FPTAN , , D9 F2
, colspan="2" , 8087: $0\leq\left, st(0)\\leq\frac$
80387: $0\leq\left, st(0)\<2^$
, -
, Two-argument arctangent with quadrant adjustment:$st(1) \leftarrow \arctan\left(\frac\right)$ followed by stack pop
, FPATAN , , D9 F3
, colspan="2" , 8087: $\left, st(1)\\leq\left, st(0)\<\infty$
80387: no restrictions
, -
, Base-2 Logarithm plus 1 with extra precision for st(0) close to 0, followed by multiply:
$st(1) \leftarrow st(1)*\log_\left(st(0)+1\right)$followed by stack pop
, FYL2XP1 , , D9 F9
, colspan="2" , Intel: $\left, st(0)\<\left(1-\sqrt\right)$
AMD: \left(\sqrt-1\right)
, -
! colspan="3" , !! colspan="2" ,
, -
! colspan="3" , Other x87 Instructions !! colspan="2" ,
, -
, No operation
, FNOP , , D9 D0
, rowspan="7" colspan="2" ,
, -
, Decrement x87 FPU Register Stack Pointer
, FDECSTP , , D9 F6
, -
, Increment x87 FPU Register Stack Pointer
, FINCSTP , , D9 F7
, -
, Free x87 FPU Register
, FFREE st(i)
,
, -
, Check and handle pending unmasked x87 FPU exceptions
, WAIT,
FWAIT , , 9B
, -
, Floating-point store and pop, without stack underflow exception
, }
,
, -
, Free x87 register, then stack pop
, }
,

x87 instructions added in later processors

SIMD instructions

Cryptographic instructions

Virtualization instructions

Other instructions

x86 also includes discontinued instruction sets which are no longer supported by Intel and AMD, and undocumented instructions which execute but are not officially documented.

Undocumented x86 instructions

The x86 CPUs contain undocumented instructions which are implemented on the chips but not listed in some official documents. They can be found in various sources across the Internet, such as Ralf Brown's Interrupt List and a
sandpile.org

Some of these instructions are widely available across many/most x86 CPUs, while others are specific to a narrow range of CPUs.

Undocumented instructions that are widely available across many x86 CPUs include

Undocumented instructions that appear only in a limited subset of x86 CPUs include

Undocumented x87 instructions

See also

* CLMUL
* RDRAND
* Advanced Vector Extensions 2
* AVX-512
* x86 Bit manipulation instruction set
* CPUID
* List of discontinued x86 instructions

References

*

External links

Free IA-32 and x86-64 documentation
provided by Intel

AMD64 Architecture Programmer's Manual, Volumes 1-5
provided by AMD

x86 Opcode and Instruction Reference



Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs


(from Netwide Assembler)

{{x86 assembly topics

Instruction set listings