The
Western Design Center
The Western Design Center (WDC), located in Mesa, Arizona, is a company which develops intellectual property for, and licenses manufacture of, MOS Technology 65xx based microprocessors, microcontrollers (µCs), and related support devices. W ...
(WDC) 65C02
microprocessor
A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circ ...
is an enhanced
CMOS
Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", ) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSF ...
version of the popular
nMOS-based
8-bit
In computer architecture, 8-bit integers or other data units are those that are 8 bits wide (1 octet). Also, 8-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers or data buses ...
MOS Technology 6502
The MOS Technology 6502 (typically pronounced "sixty-five-oh-two" or "six-five-oh-two") William Mensch and the moderator both pronounce the 6502 microprocessor as ''"sixty-five-oh-two"''. is an 8-bit microprocessor that was designed by a small te ...
. The 65C02 fixed several problems in the original 6502 and added some new instructions, but its main feature was greatly lowered power usage, on the order of 10 to 20 times less than the original 6502 running at the same speed. The reduced power consumption made the 65C02 useful in
portable computer
A portable computer is a computer designed to be easily moved from one place to another and included a display and keyboard together, with a single plug, much like later desktop computers called '' all-in-ones'' (AIO), that integrate the s ...
roles and
microcontroller
A microcontroller (MCU for ''microcontroller unit'', often also MC, UC, or μC) is a small computer on a single VLSI integrated circuit (IC) chip. A microcontroller contains one or more CPUs ( processor cores) along with memory and programmabl ...
systems in industrial settings. It has been used in some
home computers, as well as in
embedded applications, including medical-grade implanted devices.
Development of the WDC 65C02 began in 1981 with samples released in early 1983. The 65C02
was officially released sometime shortly after. WDC licensed the design to
Synertek
Synertek, Inc. was an American semiconductor manufacturer founded in 1973. The initial staff consisted of Bob Schreiner (the CEO), Dan Floyd, Jack Balletto, and Gunnar Wetlesen and Zvi Grinfas. Schreiner, Floyd, Balletto and Wetlesen were all forme ...
,
NCR,
GTE, and
Rockwell Semiconductor Rockwell may refer to:
Arts, entertainment, and media
* ''Rockwell'' (album), a 2009 mini-album by Anni Rossi
* Rockwell, a fictional town and setting of ''They Hunger''
* ''Rockwell'', a 1994 film about Porter Rockwell
* Rockwell, Maine, a f ...
. Rockwell's primary interest was in the embedded market and asked for several new commands to be added to aid in this role. These were later copied back into the baseline version, at which point WDC added two new commands of their own to create the W65C02.
Sanyo
, stylized as SANYO, is a Japanese electronics company and formerly a member of the ''Fortune'' Global 500 whose headquarters was located in Moriguchi, Osaka prefecture, Japan. Sanyo had over 230 subsidiaries and affiliates, and was founded by ...
later licensed the design as well, and
Seiko Epson
Seiko Epson Corporation, or simply known as Epson, is a Japanese multinational electronics company and one of the world's largest manufacturers of computer printers and information- and imaging-related equipment. Headquartered in Suwa, Nagano ...
produced a further modified version as the
HuC6280.
Early versions used 40-pin DIP packaging, and were available in 1, 2 and 4 MHz versions, matching the speeds of the original nMOS versions. Later versions were produced in
PLCC and
QFP packages, as well as PDIP, and with much higher clock speed ratings. The current version from WDC, the W65C02S-14 has a fully static core and officially runs at speeds up to 14 MHz when powered at 5 volts.
Introduction and features
The 65C02 is a low cost, general-purpose
8-bit
In computer architecture, 8-bit integers or other data units are those that are 8 bits wide (1 octet). Also, 8-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers or data buses ...
microprocessor (8-bit
register
Register or registration may refer to:
Arts entertainment, and media Music
* Register (music), the relative "height" or range of a note, melody, part, instrument, etc.
* ''Register'', a 2017 album by Travis Miller
* Registration (organ), th ...
s and
data bus
In computer architecture, a bus (shortened form of the Latin '' omnibus'', and historically also called data highway or databus) is a communication system that transfers data between components inside a computer, or between computers. This ...
) with a
16-bit
16-bit microcomputers are microcomputers that use 16-bit microprocessors.
A 16-bit register can store 216 different values. The range of integer values that can be stored in 16 bits depends on the integer representation used. With the two ...
program counter
The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR), the instruction counter, or just part of the instruction sequencer, i ...
and
address bus
In computer architecture, a bus (shortened form of the Latin '' omnibus'', and historically also called data highway or databus) is a communication system that transfers data between components inside a computer, or between computers. This e ...
. The register set is small, with a single 8-bit
accumulator (A), two 8-bit
index register
An index register in a computer's CPU is a processor register (or an assigned memory location) used for pointing to operand addresses during the run of a program. It is useful for stepping through strings and arrays. It can also be used for hol ...
s (X and Y), an 8-bit status register (P), and a 16-bit program counter (PC). In addition to the single accumulator, the first 256 bytes of RAM, the "zero page" (
$0000
to
$00FF
), allow faster access through addressing modes that use an 8-bit memory address instead of a 16-bit address. The
stack
Stack may refer to:
Places
* Stack Island, an island game reserve in Bass Strait, south-eastern Australia, in Tasmania’s Hunter Island Group
* Blue Stack Mountains, in Co. Donegal, Ireland
People
* Stack (surname) (including a list of people ...
lies in the next 256 bytes, page one ($0100 to $01FF), and cannot be moved or extended. The stack grows backwards with the
stack pointer (S) starting at $01FF and decrementing as the stack grows. It has a variable-length
instruction set
In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ...
, varying between one and three bytes per instruction.
The basic architecture of the 65C02 is identical to the original 6502, and can be considered a low-power implementation of that design. At 1 MHz, the most popular speed for the original 6502, the 65C02 requires only 20 mW, while the original uses 450 mW, a reduction of over twenty times. The manually optimized core and low power use is intended to make the 65C02 well suited for low power
system-on-chip
A system on a chip or system-on-chip (SoC ; pl. ''SoCs'' ) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memor ...
(SoC) designs.
A
Verilog
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is als ...
hardware description model is available for designing the W65C02S core into an
application-specific integrated circuit
An application-specific integrated circuit (ASIC ) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-effici ...
(ASIC) or a
field-programmable gate array
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturinghence the term ''Field-programmability, field-programmable''. The FPGA configuration is generally specifi ...
(FPGA). As is common in the semiconductor industry, WDC offers a development system, which includes a
developer board, an
in-circuit emulator
In-circuit emulation (ICE) is the use of a hardware device or in-circuit emulator used to debug the software of an embedded system. It operates by using a processor with the additional ability to support debugging operations, as well as to carr ...
(ICE) and a software development system.
The W65C02S–14 is the production version , and is available in
PDIP
In microelectronics, a dual in-line package (DIP or DIL), is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through-hole mounted to a printed circuit board ...
,
PLCC and
QFP packages. The maximum officially supported Ø2 (primary) clock speed is 14
MHz when operated at 5 volts, indicated by the –14 part number suffix (hobbyists have developed 65C02
homebrew systems that run faster than the official rating). The "S" designation indicates that the part has a fully
static core
Static core generally refers to a microprocessor (MPU) entirely implemented in static logic. A static core MPU may be halted by stopping the system clock oscillator that is driving it, maintaining its state and resume processing at the poin ...
, a feature that allows Ø2 to be slowed down or fully stopped in either the high or low state with no loss of data. Typical microprocessors not implemented in CMOS have dynamic cores and will lose their internal register contents (and thus crash) if they are not continuously clocked at a rate between some minimum and maximum specified values.
General logic features
* 8-bit
data bus
In computer architecture, a bus (shortened form of the Latin '' omnibus'', and historically also called data highway or databus) is a communication system that transfers data between components inside a computer, or between computers. This ...
* 16-bit
address bus
In computer architecture, a bus (shortened form of the Latin '' omnibus'', and historically also called data highway or databus) is a communication system that transfers data between components inside a computer, or between computers. This e ...
(providing an address space of 64 KB)
* 8-bit
arithmetic logic unit
In computing, an arithmetic logic unit (ALU) is a combinational digital circuit that performs arithmetic and bitwise operations on integer binary numbers. This is in contrast to a floating-point unit (FPU), which operates on floating point num ...
(ALU)
* 8-bit
processor register
A processor register is a quickly accessible location available to a computer's processor. Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. ...
s:
**
accumulator
**
stack pointer
In computer science, a call stack is a stack data structure that stores information about the active subroutines of a computer program. This kind of stack is also known as an execution stack, program stack, control stack, run-time stack, or mach ...
**
index register
An index register in a computer's CPU is a processor register (or an assigned memory location) used for pointing to operand addresses during the run of a program. It is useful for stepping through strings and arrays. It can also be used for hol ...
s
**
status register
A status register, flag register, or condition code register (CCR) is a collection of status flag bits for a processor. Examples of such registers include FLAGS register in the x86 architecture, flags in the program status word (PSW) register in ...
* 16-bit
program counter
The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR), the instruction counter, or just part of the instruction sequencer, i ...
* 69
instructions, implemented by 212
operation codes
* 16
addressing mode
Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions i ...
s, including
zero page
The zero page or base page is the block of memory at the very beginning of a computer's address space; that is, the page whose starting address is zero. The size of a page depends on the context, and the significance of zero page memory versus h ...
addressing
Logic features
* Vector pull (
VPB
) output indicates when
interrupt vector
An interrupt vector table (IVT) is a data structure that associates a list of interrupt handlers with a list of interrupt requests in a table of interrupt vectors. Each entry of the interrupt vector table, called an interrupt vector, is the addre ...
s are being addressed
* Memory lock (
MLB
) output indicates to other
bus masters when a
read-modify-write instruction is being processed
* WAit-for-Interrupt (
WAI
) and SToP (
STP
) instructions reduce power consumption, decrease
interrupt latency
In computing, interrupt latency refers to the delay between the start of an Interrupt Request (IRQ) and the start of the respective Interrupt Service Routine (ISR). For many operating systems, devices are serviced as soon as the device's interrup ...
and enable synchronization with external events
Electrical features
* Supply
voltage
Voltage, also known as electric pressure, electric tension, or (electric) potential difference, is the difference in electric potential between two points. In a static electric field, it corresponds to the work needed per unit of charge to ...
specified at 1.71 V to 5.25 V
* Current consumption (core) of 0.15 and 1.5
mA per
MHz at 1.89 V and 5.25 V respectively
* Variable length instruction set, enabling code size optimization over fixed length instruction set processors, results in power savings
* Fully
static circuitry allows stopping the clock to conserve power
Clocking features
The W65C02S may be operated at any convenient supply voltage (V
DD) between 1.8 and 5 volts (±5%). The
data sheet AC characteristics table lists operational characteristics at 5 V at 14 MHz, 3.3 V or 3 V at 8 MHz, 2.5 V at 4 MHz, and 1.8 V at 2 MHz. This information may be an artifact of an earlier data sheet, as a graph indicates that typical devices are capable of operation at higher speeds than suggested by the AC characteristics table, and that reliable operation at 20 MHz should be readily attainable with V
DD at 5 volts, assuming the supporting hardware will allow it.
The W65C02S support for arbitrary clock rates allows it to use a clock that runs at a rate ideal for some other part of the system, such as 13.5 MHz (digital SDTV luma sampling rate), 14.31818 MHz (NTSC colour carrier frequency × 4), 14.75 MHz (PAL square pixels), 14.7456 (baud rate crystal), etc., as long as V
DD is sufficient to support the frequency. Designer
Bill Mensch
William David Mensch, Jr. (born February 9, 1945) is an American electrical engineer born in Quakertown, Pennsylvania. He was a major contributor to the design of the Motorola 6800 8-bit microprocessor and was part of the team led by Chuck Pedd ...
has pointed out that F
MAX is affected by off-chip factors, such as the capacitive load on the microprocessor's pins. Minimizing load by using short signal tracks and fewest devices helps raise F
MAX. The PLCC and QFP packages have less pin-to-pin capacitance than the PDIP package, and are more economical in the use of
printed circuit board
A printed circuit board (PCB; also printed wiring board or PWB) is a medium used in electrical and electronic engineering to connect electronic components to one another in a controlled manner. It takes the form of a laminated sandwich str ...
space.
WDC has reported that FPGA realizations of the W65C02S have been successfully operated at 200 MHz.
Comparison with the NMOS 6502
Basic architecture
Although the 65C02 can mostly be thought of as a low-power 6502, it also fixes several bugs found in the original and adds new instructions, addressing modes and features that can assist the programmer in writing smaller and faster-executing programs. It is estimated that the average 6502 assembly language program can be made 10 to 15 percent smaller on the 65C02 and see a similar improvement in performance, largely through avoided memory accesses through the use of fewer instructions to accomplish a given task.
Undocumented instructions removed
The original 6502 has 56 instructions, which, when combined with different addressing modes, produce a total of 151
opcode
In computing, an opcode (abbreviated from operation code, also known as instruction machine code, instruction code, instruction syllable, instruction parcel or opstring) is the portion of a machine language instruction that specifies the operat ...
s of the possible 256 8-bit opcode patterns. The remaining 105 unused opcodes are undefined, with the set of codes with low-order 4-bits with 3, 7, B or F left entirely unused, the code with low-order 2 having only a single opcode.
On the 6502, some of these leftover codes actually perform computation. Due to the way the 6502's instruction decoder works, simply setting certain bits in the opcode cause parts of the instruction processing to take place. Some of these opcodes immediately crash the processor, while other perform useful functions and were even given unofficial assembler mnemonics by some programmers.
The 65C02 adds new opcodes that use some of these previously undocumented instruction slots. For example, $FF is used for the new
BBS
instruction. Those which remain truly unused are equivalent to
NOP
s. 6502 programs using those opcodes will not work on the 65C02.
Bug fixes
The original 6502 had several errata when initially launched. Early versions of the processor had a defective
ROR
(rotate right) instruction, which MOS Technology addressed by not documenting the instruction.
ROR
was fixed very early in the production run and was not an issue for the vast majority of machines using the processor.
A bug that is present in all NMOS variants of the 6502 involves the jump instruction when using
indirect addressing
Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions i ...
. In this addressing mode, the target address of the
JMP
instruction is fetched from memory, the jump vector, rather than being an operand to the
JMP
instruction. For example,
JMP ($1234)
would fetch the value in memory locations (least significant byte) and (most significant byte) and load those values into the
program counter
The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR), the instruction counter, or just part of the instruction sequencer, i ...
, which would then cause the processor to continue execution at the address stored in the vector.
The bug appears when the vector address ends in , which is the boundary of a
memory page
A page, memory page, or virtual page is a fixed-length contiguous block of virtual memory, described by a single entry in the page table. It is the smallest unit of data for memory management in a virtual memory operating system. Similarly, a p ...
. In this case,
JMP
will fetch the most significant byte of the target address from of the original page rather than $00 of the new page. Hence
JMP ($12FF)
would get the least significant byte of the target address at and the most significant byte of the target address from rather than . The 65C02 corrected this issue.
More of an oversight than a bug, the state of the (D)ecimal flag in the NMOS 6502's status register is undefined after a
reset or
interrupt
In digital computers, an interrupt (sometimes referred to as a trap) is a request for the processor to ''interrupt'' currently executing code (when permitted), so that the event can be processed in a timely manner. If the request is accepted, ...
. This means programmers have to set the flag to a known value in order to avoid any bugs related to arithmetic operations. As a result, one finds a
CLD
instruction (CLear Decimal) in almost all 6502
interrupt handler
In computer systems programming, an interrupt handler, also known as an interrupt service routine or ISR, is a special block of code associated with a specific interrupt condition. Interrupt handlers are initiated by hardware interrupts, softw ...
s, as well as early in the reset code. The 65C02 automatically clears this flag after pushing the status register onto the stack in response any interrupt or in response to a hardware reset, thus placing the processor back into binary arithmetic mode.
[
During decimal mode arithmetic, the NMOS 6502 will update the (N)egative, o(V)erflow and (Z)ero flags to reflect the result of underlying binary arithmetic, that is, the flags are reflecting a result computed prior to the processor performing decimal correction. In contrast, the 65C02 sets these flags according to the result of decimal arithmetic, at the cost of an extra clock cycle per arithmetic instruction.]
When executing a read-modify-write (R-M-W) instruction, such as INC ''addr''
, all NMOS variants will do a double write on ''addr'', first rewriting the current value found at ''addr'' and then writing the modified value. This behavior can result in difficult-to-resolve bugs if ''addr'' is a hardware register. This may occur if the hardware is watching for changes to the value in the register and then performs an action, in this case, it will perform two actions, one with the original value and then again with the new value. The 65C02 instead performs a double read of ''addr'', followed by a single write.
When performing indexed addressing, if indexing crosses a page boundary all NMOS variants will read from an invalid address before accessing the correct address. As with a R-M-W instruction, this behavior can cause problems when accessing hardware registers via indexing. The 65C02 fixed this problem by performing a dummy read of the instruction opcode when indexing crosses a page boundary. However, this fix introduced a new bug that occurs when the base address is on an even page boundary (which means indexing will never cross into the next page). With the new bug, a dummy read is performed on the base address prior to indexing, such that LDA $1200,X
will do a dummy read on prior to the value of X being added to . Again, if indexing on hardware register addresses, this bug can result in undefined behavior.
If an NMOS 6502 is fetching a BRK (software interrupt) opcode at the same time a hardware interrupt occurs, the BRK will be ignored as the processor reacts to the hardware interrupt. The 65C02 correctly handles this situation by servicing the interrupt and then executing BRK.
New addressing modes
The 6502 has two indirect addressing modes which dereference through 16-bit addresses stored in page zero:
* Indexed indirect, e.g. LDA ($10,X)
, adds the X register to the given page zero address before reading the 16-bit vector. In this example, if X is 5, it reads the 16-bit address from location $15/$16. This is useful when there is an array of pointers in page zero.
* Indirect indexed LDA ($10),Y
adds the Y register to the 16-bit vector read from the given page zero address. For instance, if Y is 5, and contains the vector , This reads the value from . This performs pointer-offset addressing.
A downside of this model is that if indexing is not needed but the address is in the zero page, one of the index registers must still be set to zero and used in one of these instructions. The 65C02 added a non-indexed indirect addressing mode LDA ($10)
to all instructions that used indexed indirect and indirect indexed modes, freeing up the index registers.
The 6502's instruction had a unique (among 6502 instructions) addressing mode known as "absolute indirect" that read a 16-bit value from a given memory address and then jumped to the address in that 16-bit value. For instance, if memory location holds $34 and holds $12, JMP ($A000)
would read those two bytes, construct the value , and then jump to that location.
One common use for indirect addressing is to build branch table
In computer programming, a branch table or jump table is a method of transferring program control ( branching) to another part of a program (or a different program that may have been dynamically loaded) using a table of branch or jump instruction ...
s, a list of entry points for subroutine
In computer programming, a function or subroutine is a sequence of program instructions that performs a specific task, packaged as a unit. This unit can then be used in programs wherever that particular task should be performed.
Functions may ...
s that can be accessed using an index. For instance, a device driver
In computing, a device driver is a computer program that operates or controls a particular type of device that is attached to a computer or automaton. A driver provides a software interface to hardware devices, enabling operating systems and o ...
might list the entry points for , , , etc in a table at . is the third entry, zero indexed, and each address requires 16-bits, so to call one would use something similar to JMP ($A004)
. If the driver is updated and the subroutine code moves in memory, any existing code will still work as long as the table of pointers remains at .
The 65C02 added the new "indexed absolute indirect" mode which eased the use of branch tables. This mode added the value of the X register to the absolute address and took the 16-bit address from the resulting location. For instance, to access the function from the table above, one would store 4 in X, then JMP ($A000,X)
. This style of access makes accessing branch tables simpler as a single base address is used in conjunction with an 8-bit offset.[ The same could be achieved in the NMOS version using indexed indirect mode, but only if the table was in the zero page, a limited resource. Allowing these to be constructed outside zero page not only lessened the demand for this resource, but also allowed the tables to be constructed in ROM.
]
New and modified instructions
In addition to the new addressing modes, the "base model" 65C02 also added a set of new instructions.
* INC
and DEC
with no parameters now increment or decrement the accumulator. This was an odd oversight in the original instruction set, which only included INX
/DEX
,INY
/DEY
and INC ''addr''
/DEC ''addr''
. Some assemblers use the alternate forms INA
/DEA
or INC A
/DEC A
.
* STZ ''addr''
, STore Zero in ''addr''. Replaces the need to LDA #0;STA ''addr''
and doesn't require changing the value of the accumulator. As this task is common in most programs, using STZ can reduce code size, both by eliminating the LDA as well as any code needed to save the value of the accumulator, typically a PHA
PLA
pair.
* PHX
,PLX
,PHY
,PLY
, push and pull the X and Y registers to/from the stack. Previously, only the accumulator and status register had push and pull instructions. X and Y could only be stacked by moving them to the accumulator first with TXA
or TYA
, thereby changing the accumulator contents, then using PHA
.
* BRA
, branch always. Operates like a JMP
but uses a 1-byte relative address like other branches, saving a byte. The speed is often the same as the 3 cycle absolute JMP
unless a page is crossed which would make the BRA
version 1 cycle longer (4 cycles). As the address is relative, it is also useful when writing relocatable code, a common task in the era before memory management unit
A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware unit having all memory references passed through itself, primarily performing the translation of virtual memory addresses to physical a ...
s.
Bit manipulation instructions
Both WDC and Rockwell contributed improvements to the bit testing and manipulation functions in the 65C02. WDC added new addressing modes to the BIT instruction that was present in the 6502, as well two new instructions for convenient manipulation of bit fields, a common activity in device drivers.
BIT in the 65C02 adds immediate mode, zero page indexed by X and absolute indexed by X addressing. Immediate mode addressing is particularly convenient in that it is completely non-destructive. For example:
:LDA $1234
:BIT #%00010000
may be used in place of:
:LDA $1234
:AND #%00010000
The operation changes the value in the accumulator, so the original value loaded from $1234 is lost. Using leaves the value in the accumulator unchanged, so subsequent code can make additional tests against the original value, avoiding having to re-load the value from memory.
In addition to the enhancements of the BIT instruction, WDC added two instructions designed to conveniently manipulate bit fields:
* TSB ''addr''
and TRB ''addr''
, Test and Set Bits and Test and Reset Bits.
:A mask in the accumulator (.A
) is logically ANDed with memory at ''addr'', which location may be zero page or absolute. The Z flag in the status register is conditioned according to the result of the logical AND—no other status register flags are affected. Furthermore, bits in ''addr'' are set (TSB) or cleared (TRB) according to the mask in .A
. Succinctly, TSB performs a logical OR after the logical AND and stores the result of the logical OR at ''addr'', whereas TRB stores the results of the logical AND at ''addr''. In both cases, the Z flag in the status register indicates the result of .A AND ''addr''
before the content of ''addr'' is changed. TRB and TSB thus replace a sequence of instructions, essentially combining the BIT instruction with additional steps to save the computational changes, but in a way that reports the status of the affected value before it is changed.
Rockwell's changes added more bit manipulation instructions for directly setting and testing any bit, and combining the test, clear and branch into a single opcode. The new instructions were available from the start in Rockwell's R65C00 family, but was not part of the original 65C02 specification and not found in versions made by WDC or its other licensees. These were later copied back into the baseline design, and were available in later WDC versions.
Rockwell-specific instructions are:
* SMB''bit#'' ''zp''
/RMB''bit#'' ''zp''
. Set or Reset (clear) bit number ''bit#'' in zero page byte ''zp''.
:RMB and SMB are used to clear (RMB) or set (SMB) individual bits in a bit field, each replacing a sequence of three instructions. As RMB and SMB are zero page addressing only, these instructions are limited in usefulness and are primarily of value in systems in which device registers are present in zero page. The ''bit#'' component of the instruction is often written as part of the mnemonic, such as SMB1 $12
which sets bit 1 in zero-page address $12. Some assemblers treat ''bit#'' as part of the instruction's operand, e.g., SMB 1,$12
, which has the advantage of allowing it to be replaced by a variable name or calculated number.
* BBR ''bit#'',''offset'',''addr''
and BBS ''bit#'',''offset'',''addr''
, Branch on Bit Set/Reset.
:Same zero-page addressing and limitations as RMB and SMB, but branches to ''addr'' if the selected bit is clear (BBR) or set (BBS). As is the case with RMB and SMB, BBR and BBS replace a sequence of three instructions.
Low-power modes
In addition to the new commands above, WDC also added the STP
and WAI
instructions for supporting low-power modes.
, STop the Processor, halted all processing until a hardware reset was issued. This could be used to put a system to "sleep" and then rapidly wake it with a reset. Normally this would require some external system to maintain main memory, and it was not widely used.
t had a similar effect, entering low-power mode, but this instruction woke the processor up again on the reception of an interrupt. Previously, handling an interrupt generally involved running a loop to check if an interrupt has been received, sometimes known as "spinning
Spin or spinning most often refers to:
* Spinning (textiles), the creation of yarn or thread by twisting fibers together, traditionally by hand spinning
* Spin, the rotation of an object around a central axis
* Spin (propaganda), an intentionally ...
", checking the type when one is received, and then jumping to the processing code. This meant the processor was running during the entire process, even when no interrupts were occurring.
In contrast, in the 65C02, interrupt code could be written by having a followed immediately by a or to the handler. When the was encountered, processing stopped and the processor went into low-power mode. When the interrupt was received, it immediately processed the and handled the request.
This had the added advantage of slightly improving performance. In the spinning case, the interrupt might arrive in the middle of one of the loop's instructions, and to allow it to restart after returning from the handler, the processor spends one cycle to save its location. With , the processor enters the low-power state in a known location where all instructions are guaranteed to be complete, so when the interrupt arrives it cannot possibly interrupt an instruction and the processor can safely continue without spending a cycle saving state.
65SC02
The 65SC02 is a variant of the WDC 65C02 without bit instructions.
Notable uses of the 65C02
Home computers
* Apple IIc
The Apple IIc, the fourth model in the Apple II series of personal computers, is Apple Computer's first endeavor to produce a portable computer. The result was a notebook-sized version of the Apple II that could be transported from place to ...
portable by Apple Computer
Apple Inc. is an American multinational technology company headquartered in Cupertino, California, United States. Apple is the largest technology company by revenue (totaling in 2021) and, as of June 2022, is the world's biggest company ...
(NCR 1.023 MHz)
* Enhanced Apple IIe by Apple Computer (1.023 MHz)
* BBC Master home/educational computer, by Acorn Computers Ltd
The acorn, or oaknut, is the nut of the oaks and their close relatives (genera ''Quercus'' and ''Lithocarpus'', in the family Fagaceae). It usually contains one seed (occasionally
two seeds), enclosed in a tough, leathery shell, and borne ...
(2 MHz 65SC12 plus optional 4 MHz 65C102 second processor)
* Replica 1
The Replica 1 is a clone of the historic Apple I of 1976. It was designed by Vince Briel in 2003. It was the first Apple 1 clone to take advantage of more modern components, enabling the clone to be produced with cheaper and more widely availab ...
by Briel Computers, a replica of the Apple I
The Apple Computer 1, originally released as the Apple Computer and known later as the Apple I or Apple-1, is an 8-bit desktop computer released by the Apple Computer Company (now Apple Inc.) in 1976. It was designed by Steve Wozniak. The i ...
hobbyist computer (1 MHz)
* Laser 128 series clones of Apple II
The Apple II (stylized as ) is an 8-bit home computer and one of the world's first highly successful mass-produced microcomputer products. It was designed primarily by Steve Wozniak; Jerry Manock developed the design of Apple II's foam-m ...
* KIM-1
The KIM-1, short for ''Keyboard Input Monitor'', is a small 6502-based single-board computer developed and produced by MOS Technology, Inc. and launched in 1976. It was very successful in that period, due to its low price (thanks to the inexp ...
Modern Replica of the MOS/CBM KIM-1 by Briel Computing
Video game consoles
* Atari Lynx
The Atari Lynx is a hybrid 8/16-bit fourth generation handheld game console released by Atari Corporation in September 1989 in North America and 1990 in Europe and Japan. It was the first handheld game console with a color liquid-crystal disp ...
handheld (65SC02 @ ~4 MHz)
* NEC PC Engine
The TurboGrafx-16, known as the outside North America, is a home video game console designed by Hudson Soft and sold by NEC Home Electronics. It was the first console marketed in the fourth generation, commonly known as the 16-bit era, thoug ...
aka TurboGrafx-16 ( HuC6280 @ 7.16 MHz)
* GameKing
GameKing is a brand of handheld game consoles, designed and developed by Timetop in 2003, for the Hong Kong consumer market. The brand has three consoles, the GameKing I, the GameKing II and the GameKing III. A fourth console, the Handy Game, ...
handhelds (6 MHz) by Timetop
* Watara Supervision
The Watara Supervision, also known as the QuickShot Supervision in the UK, is a monochrome handheld game console, originating from Asia, and introduced in 1992 as a cut-price competitor for Nintendo's Game Boy. It came packaged with a game calle ...
handhelds (65SC02 @ 4 MHz)
Other products
* TurboMaster accelerator cartridge for the Commodore 64
The Commodore 64, also known as the C64, is an 8-bit home computer introduced in January 1982 by Commodore International (first shown at the Consumer Electronics Show, January 7–10, 1982, in Las Vegas). It has been listed in the Guinness W ...
home computer (65C02 @ 4.09 MHz)
* Tube-connected second processor for the Acorn BBC Micro home computer (65C02 @ 3 MHz)
* many dedicated chess computers
In computer chess, a chess engine is a computer program that analyzes chess or chess variant positions, and generates a move or list of moves that it regards as strongest.
A chess engine is usually a back end with a command-line interface with n ...
i.e.: Mephisto MMV, Novag Super Constellation, Fidelity Elite and many more (4–20 MHz)
See also
* Interrupts in 65xx processors
The 65xx family of microprocessors, consisting of the MOS Technology 6502 and its derivatives, the WDC 65C02, WDC 65C802 and WDC 65C816, and CSG 65CE02, all handle interrupts in a similar fashion. There are three hardware interrupt signals com ...
* CSG 65CE02
The CSG 65CE02 is an 8/16-bit microprocessor developed by Commodore Semiconductor Group in 1988. It is a member of the MOS Technology 6502 family, developed from the CMOS WDC 65C02 released by the Western Design Center in 1983.
Like the 65C02, t ...
, a further enhanced version of the 65C02
Notes
References
Citations
Bibliography
*
*
Further reading
*
65C02 Datasheet
'; Western Design Center; 32 pages; 2018.
* ''Programming the 65816 - including the 6502, 65C02, 65802''; 1st Ed; David Eyes and Ron Lichty; Prentice Hall; 636 pages; 1986; . (archive)
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External links
65C02 webpage
- Western Design Center
- CPU World
– From Neil Parker's Apple II page
{{MOS CPU
65xx microprocessors
8-bit microprocessors