Universal Chiplet Interconnect Express (UCIe) is an
open specification
An open standard is a standard that is openly accessible and usable by anyone. It is also a prerequisite to use open license, non-discrimination and extensibility. Typically, anybody can participate in the development. There is no single definition ...
for a
die
Die, as a verb, refers to death, the cessation of life.
Die may also refer to:
Games
* Die, singular of dice, small throwable objects used for producing random numbers
Manufacturing
* Die (integrated circuit), a rectangular piece of a semicondu ...
-to-die
interconnect and
serial bus
In telecommunication and data transmission, serial communication is the process of sending data one bit at a time, sequentially, over a communication channel or computer bus. This is in contrast to parallel communication, where several bits are ...
between
chiplet
A chiplet is a tiny integrated circuit (IC) that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an interposer in a single package. A set of chiplets can be implemented in a mix-and-match "LEGO ...
s. It is co-developed by
AMD,
Arm,
ASE Group,
Google Cloud,
Intel,
Meta
Meta (from the Greek μετά, '' meta'', meaning "after" or "beyond") is a prefix meaning "more comprehensive" or "transcending".
In modern nomenclature, ''meta''- can also serve as a prefix meaning self-referential, as a field of study or ende ...
,
Microsoft,
Qualcomm
Qualcomm () is an American multinational corporation headquartered in San Diego, California, and incorporated in Delaware. It creates semiconductors, software, and services related to wireless technology. It owns patents critical to the 5G, 4 ...
,
Samsung, and
TSMC.
In August 2022,
Alibaba Group and
NVIDIA joined as board members.
Overview
A common chiplet interconnect specification enables construction of large
System-on-Chip (SoC) packages that exceed maximum
reticle size. It allows intermixing components from different silicon vendors within the same package and improves manufacturing yields by using smaller dies. Each chiplet can use different
silicon manufacturing process suitable for a specific device type or computing performance and power draw requirements.
Specifications
The UCIe 1.0 specification was released on March 2, 2022. It defines physical layer
In the seven-layer OSI model of computer networking, the physical layer or layer 1 is the first and lowest layer; The layer most closely associated with the physical connection between devices. This layer may be implemented by a PHY chip.
The ...
, protocol stack and software model, as well as procedures for compliance testing. The physical layer supports up to 32 GT/s with 16 to 64 lanes and uses a 256 byte Flow Control Unit (FLIT) for data, similar to PCIe 6.0; the protocol layer is based on Compute Express Link
Compute Express Link (CXL) is an open standard for high-speed central processing unit (CPU)-to-device and CPU-to-memory connections, designed for high performance data center computers. CXL is built on the PCI Express (PCIe) physical and electrica ...
with CXL.io (PCIe), CXL.mem and CXL.cache protocols.
Various on-die interconnect technologies are defined, like organic substrate for a 'standard' 2D package, or embedded silicon bridge (EMIB), silicon interposer, and fanout embedded bridge for 'advanced' 2.5D/3D packages.[ Physical specifications are based on Intel's Advanced Interface Bus (AIB).]SerDes
{{Use American English, date = March 2019
A Serializer/Deserializer (SerDes) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and paral ...
, with bandwidth density up to 1.35 TByte/s per mm2 for a common bump pitch of 45 μm
The micrometre ( international spelling as used by the International Bureau of Weights and Measures; SI symbol: μm) or micrometer (American spelling), also commonly known as a micron, is a unit of length in the International System of Unit ...
, and 3.24× higher density with a bump pitch of 25 μm.[
Future versions may include additional protocols, wider data links, and higher density connections.][https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf ]
References
External links
*
Open standards
Serial buses
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