TILE''Pro''64 is a

VLIW Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP). Whereas conventional central processing units (CPU, processor) mostly allow programs to specify instructions to exe ...

ISA

multicore processor A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions (such a ...

( Tile processor) manufactured by

Tilera Tilera Corporation was a fabless semiconductor company focusing on manycore embedded processor design. The company shipped multiple processors, including the TILE64, TILE''Pro''64, and the TILE''Pro''36, TILE-Gx72, TILE-Gx36, TILE-Gx16 and TILE- ...

. It consists of a cache-coherent

mesh network A mesh network is a local area network topology in which the infrastructure nodes (i.e. bridges, switches, and other infrastructure devices) connect directly, dynamically and non-hierarchically to as many other nodes as possible and cooperate wit ...

of 64 "tiles", where each tile houses a general purpose

processor Processor may refer to: Computing Hardware * Processor (computing) **Central processing unit (CPU), the hardware within a computer that executes a program *** Microprocessor, a central processing unit contained on a single integrated circuit (I ...

cache Cache, caching, or caché may refer to: Places United States * Cache, Idaho, an unincorporated community * Cache, Illinois, an unincorporated community * Cache, Oklahoma, a city in Comanche County * Cache, Utah, Cache County, Utah * Cache Count ...

, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor. The short-

pipeline Pipeline may refer to: Electronics, computers and computing * Pipeline (computing), a chain of data-processing stages or a CPU optimization found on ** Instruction pipelining, a technique for implementing instruction-level parallelism within a s ...

, in-order, three-issue cores implement a

instruction set In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ' ...

. Each core has a

register Register or registration may refer to: Arts entertainment, and media Music * Register (music), the relative "height" or range of a note, melody, part, instrument, etc. * ''Register'', a 2017 album by Travis Miller * Registration (organ), the ...

file and three functional units: two integer

arithmetic logic unit In computing, an arithmetic logic unit (ALU) is a Combinational logic, combinational digital circuit that performs arithmetic and bitwise operations on integer binary numbers. This is in contrast to a floating-point unit (FPU), which operates on ...

s and a load-store unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches. A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system. TILE''Pro''64 has four DDR2 controllers at up to 800MT/s, two 10-gigabit

Ethernet Ethernet () is a family of wired computer networking technologies commonly used in local area networks (LAN), metropolitan area networks (MAN) and wide area networks (WAN). It was commercially introduced in 1980 and first standardized in 198 ...

XAUI interfaces, two four-lane

PCIe PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common mo ...

interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 866 MHz. According to the company, Tilera targets the chip at networking equipment, digital video, and wireless infrastructure markets where the demands for computing processing are high. More recently, Tilera has positioned this processor in the cloud computing space with an 8-processor (512-core) 2U server built by Quanta Computer. TILE''Pro'' was supported by the

Linux kernel The Linux kernel is a free and open-source, monolithic, modular, multitasking, Unix-like operating system kernel. It was originally authored in 1991 by Linus Torvalds for his i386-based PC, and it was soon adopted as the kernel for the GNU ope ...

from version 2.6.36 to version 4.16.

Technology

Various sources have stated the specifications of processors in the TILE''Pro'' family: * 64 RISC processor cores ** 16 KB L1 instruction and 8 KB L1 data cache per core ** 64 KB L2 cache per core * 4MB L3 cache is achieved through the sharing of other tiles L2 caches with hardware-managed coherency *

90 nm The 90 nm process refers to the level of MOSFET (CMOS) fabrication process technology that was commercialized by the 2003–2005 timeframe, by leading semiconductor companies like Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpid ...

manufacturing process at TSMC * 4 integrated

memory controller The memory controller is a digital circuit that manages the flow of data going to and from the computer's main memory. A memory controller can be a separate chip or integrated into another chip, such as being placed on the same die or as an int ...

s supporting

DDR2 SDRAM Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DDR3 ...

at up to 800MT/s ** supports up to 64GB of attached DDR2 memory * Integrated high-speed I/O ** Two 4-lane

PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...

Gen1 interfaces, with root or endpoint capability ** Two 10Gbit/s Ethernet

XAUI 10 Gigabit Attachment Unit Interface (XAUI ) is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of 10 Gigabit Ethernet (10GbE) defined in Clause 47 of the IEEE 802.3 standard. The name i ...

interfaces ** Two 10/100/1000 Mbit/s Ethernet

RGMII The media-independent interface (MII) was originally defined as a standard interface to connect a Fast Ethernet (i.e., ) media access control (MAC) block to a PHY chip. The MII is standardized by IEEE 802.3u and connects different types of PHYs ...

interfaces * Power consumption in the range of 19 - 23 Watts The TILE''Pro'' family incorporates a number of enhancements over Tilera's first generation

TILE64 TILE64 is a VLIW ISA multicore processor manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the o ...

family: * "Distributed Dynamic Cache" (DDC) system that uses a separate mesh network to manage cache-coherency * "TileDirect" I/O enables direct transfer of network data coherently into the processor caches * Double the L1 instruction cache (from 8KB to 16KB), double the L2 associativity * Memory "striping" on the DDR2 interfaces to balance the loading * Instruction set enhancements for multimedia, unaligned data access, offset load/store instructions and memory access hints The networking software company

6WIND 6WIND is a virtual networking software company delivering disaggregated and cloud-native solutions to CSPs and enterprises globally. The company is privately held and headquartered in the West Paris area, in Montigny-le-Bretonneux. 6WIND has a gl ...

provides high-performance packet processing software for the TILE''Pro''64 platform.http://www.6wind.com/wp-content/uploads/PDF/press/2011/6WIND-announces-availability-of-Tilera-TilePro64-support.pdf {{Bare URL PDF, date=March 2022

References

External links

Tilera Website
*https://www.theregister.co.uk/2008/09/23/tilera_cpu_upgrade/

Manycore processors Very long instruction word computing Computer-related introductions in 2008