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SuperH (or SH) is a 32-bit
reduced instruction set computing In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set compu ...
(RISC) instruction set architecture (ISA) developed by
Hitachi () is a Japanese multinational corporation, multinational Conglomerate (company), conglomerate corporation headquartered in Chiyoda, Tokyo, Japan. It is the parent company of the Hitachi Group (''Hitachi Gurūpu'') and had formed part of the Ni ...
and currently produced by
Renesas is a Japanese semiconductor manufacturer headquartered in Tokyo, Japan, initially incorporated in 2002 as Renesas Technology, the consolidated entity of the semiconductor units of Hitachi and Mitsubishi excluding their dynamic random-access memo ...
. It is implemented by microcontrollers and
microprocessor A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circ ...
s for
embedded system An embedded system is a computer system—a combination of a computer processor, computer memory, and input/output peripheral devices—that has a dedicated function within a larger mechanical or electronic system. It is ''embedded'' as ...
s. At the time of introduction, SuperH was notable for having fixed-length 16-bit instructions in spite of its 32-bit architecture. This was a novel approach; at the time, RISC processors always used an instruction size that was the same as the internal data width, typically 32 bits. Using smaller instructions had consequences: the register file was smaller and instructions were generally two-operand format. But for the market the SuperH was aimed at, this was a small price to pay for the improved memory and
processor cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which ...
efficiency. Later versions of the design, starting with SH-5, included both 16- and 32-bit instructions, with the 16-bit versions mapping onto the 32-bit version inside the CPU. This allowed the
machine code In computer programming, machine code is any low-level programming language, consisting of machine language instructions, which are used to control a computer's central processing unit (CPU). Each instruction causes the CPU to perform a ve ...
to continue using the shorter instructions to save memory, while not demanding the amount of instruction decoding logic needed if they were completely separate instructions. This concept is now known as a
compressed instruction set A compressed instruction set, or simply compressed instructions, are a variation on a microprocessor's instruction set architecture (ISA) that allows instructions to be represented in a more compact format. In most real-world examples, compressed ...
and is also used by other companies, the most notable example being
ARM In human anatomy, the arm refers to the upper limb in common usage, although academically the term specifically means the upper arm between the glenohumeral joint (shoulder joint) and the elbow joint. The distal part of the upper limb between th ...
for its Thumb instruction set. , many of the original
patent A patent is a type of intellectual property that gives its owner the legal right to exclude others from making, using, or selling an invention for a limited period of time in exchange for publishing an enabling disclosure of the invention."A ...
s for the SuperH architecture expired and the SH-2 CPU was reimplemented as
open source hardware Open-source hardware (OSH) consists of physical artifacts of technology designed and offered by the open-design movement. Both free and open-source software (FOSS) and open-source hardware are created by this open-source culture movement and ...
under the name J2.


History


SH-1 and SH-2

The SuperH processor core family was first developed by
Hitachi () is a Japanese multinational corporation, multinational Conglomerate (company), conglomerate corporation headquartered in Chiyoda, Tokyo, Japan. It is the parent company of the Hitachi Group (''Hitachi Gurūpu'') and had formed part of the Ni ...
in the early 1990s. The design concept was for a single instruction set (ISA) that would be
upward compatible Upward may refer to: Music * ''Upwards'' (album), a 2003 album British hip-hop artist Ty Organizations * Upward Bound, a federally funded educational program within the United States * Upward Bound High School, a school in Hartwick, New York * ...
across a series of
CPU core A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, and ...
s. In the past, this sort of design problem would have been solved using microcode, with the low-end models in the series performing non-implemented instructions as a series of more basic instructions. For instance, a "long multiply" (multiplying two 32-bit registers to produce a 64-bit product) might be implemented in hardware on high-end models but instead be performed as a series of additions on low-end models. One of the key realizations during the development of the RISC concept was that the microcode had a finite decoding time, and as processors became faster, this represented an unacceptable performance overhead. To address this, Hitachi instead developed a single ISA for the entire line, with unsupported instructions causing traps on those implementations that didn't include hardware support. For instance, the initial models in the line, the SH-1 and SH-2, differed only in their support for 64-bit multiplication; the SH-2 supported , and , whereas the SH-1 would cause a trap if these were encountered. The SH-1 was the basic model, supporting a total of 56 instructions. The SH-2 added 64-bit multiplication and a few additional commands for branching and other duties, bringing the total to 62 supported instructions. The SH-1 and the SH-2 were used in the Sega Saturn,
Sega 32X The 32X is an add-on for the Sega Genesis video game console. Codenamed "Project Mars", it was designed to expand the power of the Genesis and serve as a transitional console into the 32-bit era until the release of the Sega Saturn. The 32X us ...
and
Capcom CPS-3 The or CPS-3 is an arcade system board that was first used by Capcom in 1996 with the arcade game '' Red Earth''. It was the second successor to the CP System arcade hardware, following the CP System II. It would be the last proprietary system ...
. The ISA uses 16-bit instructions for better code density than 32-bit instructions, which was a great benefit at the time, due to the high cost of main memory. The downsides to this approach were that there were fewer bits available to encode a register number or a constant value. In the SuperH ISA, there were only 16 registers, requiring four bits for the source and another four for the destination. The instruction itself was also four bits, leaving another four bits unaccounted. Some instructions used these last four bits for offsets in array accesses, while others combined the second register slot and last four bits to produce an 8-bit constant.


SH-3

A few years later, the SH-3 core was added to the family; new features included another interrupt concept, a
memory management unit A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware unit having all memory references passed through itself, primarily performing the translation of virtual memory addresses to physical a ...
(MMU), and a modified cache concept. These features required an extended instruction set, adding six new instructions for a total of 68. The SH-3 was
bi-endian In computing, endianness, also known as byte sex, is the order or sequence of bytes of a word of digital data in computer memory. Endianness is primarily expressed as big-endian (BE) or little-endian (LE). A big-endian system stores the most si ...
, running in either big-endian or little-endian byte ordering. The SH-3 core also added a
DSP DSP may refer to: Computing * Digital signal processing, the mathematical manipulation of an information signal * Digital signal processor, a microprocessor designed for digital signal processing * Yamaha DSP-1, a proprietary digital signal ...
extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine, this core unified the DSP and the RISC processor world. A derivative of the DSP was also used with the original SH-2 core. Between 1994 and 1996, 35.1 million SuperH devices were shipped worldwide.


SH-4

In 1997, Hitachi and
STMicroelectronics STMicroelectronics N.V. commonly referred as ST or STMicro is a Dutch multinational corporation and technology company of French-Italian origin headquartered in Plan-les-Ouates near Geneva, Switzerland and listed on the French stock market. ST ...
(STM) started collaborating on the design of the SH-4 for the
Dreamcast The is a home video game console released by Sega on November 27, 1998, in Japan; September 9, 1999, in North America; and October 14, 1999, in Europe. It was the first sixth-generation video game console, preceding Sony's PlayStation 2, N ...
. SH-4 featured superscalar (2-way) instruction execution and a
vector Vector most often refers to: *Euclidean vector, a quantity with a magnitude and a direction *Vector (epidemiology), an agent that carries and transmits an infectious pathogen into another living organism Vector may also refer to: Mathematic ...
floating-point unit In computing, floating-point arithmetic (FP) is arithmetic that represents real numbers approximately, using an integer with a fixed precision, called the significand, scaled by an integer exponent of a fixed base. For example, 12.345 can b ...
(particularly suited to 3D graphics). Standard chips based on the SH-4 were introduced around 1998.


Licensing

In early 2001, Hitachi and STM formed the IP company SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. The earlier SH-1 through 3 remained the property of Hitachi. In 2003, Hitachi and Mitsubishi Electric formed a joint-venture called
Renesas Technology is a Japanese semiconductor manufacturer headquartered in Tokyo, Japan, initially incorporated in 2002 as Renesas Technology, the consolidated entity of the semiconductor units of Hitachi and Mitsubishi excluding their dynamic random-access memo ...
, with Hitachi controlling 55% of it. In 2004, Renesas Technology bought STMicroelectronics's share of ownership in the SuperH Inc. and with it the licence to the SH cores. Renesas Technology later became Renesas Electronics, following their merger with
NEC Electronics is a Japanese multinational information technology and electronics corporation, headquartered in Minato, Tokyo. The company was known as the Nippon Electric Company, Limited, before rebranding in 1983 as NEC. It provides IT and network solut ...
. The SH-5 design supported two modes of operation: SHcompact mode, which is equivalent to the user-mode instructions of the SH-4 instruction set; and SHmedia mode, which is very different in that it uses 32-bit instructions with sixty-four 64-bit integer registers and
SIMD Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal (part of the hardware design) and it can be directly accessible through an instruction set architecture (ISA), but it shoul ...
instructions. In SHmedia mode the destination of a
branch A branch, sometimes called a ramus in botany, is a woody structural member connected to the central trunk (botany), trunk of a tree (or sometimes a shrub). Large branches are known as boughs and small branches are known as twigs. The term '' ...
(jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5;
ARM In human anatomy, the arm refers to the upper limb in common usage, although academically the term specifically means the upper arm between the glenohumeral joint (shoulder joint) and the elbow joint. The distal part of the upper limb between th ...
processors have a 16-bit Thumb mode (ARM licensed several patents from SuperH for Thumb) and MIPS processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding. The last evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which formed a kind of instruction set superset of the previous architectures, and added support for symmetric multiprocessing.


Continued availability

Since 2010, the SuperH CPU cores, architecture and products are with
Renesas Electronics is a Japanese semiconductor manufacturer headquartered in Tokyo, Japan, initially incorporated in 2002 as Renesas Technology, the consolidated entity of the semiconductor units of Hitachi and Mitsubishi excluding their dynamic random-access ...
and the architecture is consolidated around the SH-2, SH-2A, SH-3, SH-4 and SH-4A platforms. The system-on-chip products based on SH-3, SH-4 and SH-4A microprocessors were subsequently replaced by newer generations based on licensed CPU cores from Arm Ltd., with many of the existing models still marketed and sold until March 2025 through the Renesas Product Longevity Program. As of 2021, the SH72xx microcontrollers based on the SH-2A continue to be marketed by Renesas with guaranteed availability until February 2029, along with newer products based on several other architectures including
Arm In human anatomy, the arm refers to the upper limb in common usage, although academically the term specifically means the upper arm between the glenohumeral joint (shoulder joint) and the elbow joint. The distal part of the upper limb between th ...
, RX, and RH850.


J Core

The last of the SH-2 patents expired in 2014. At
LinuxCon Open Source Summit (formerly LinuxCon) is a name for a series of annual conventions organized each year since 2009 by the Linux Foundation. The first LinuxCon took place in North America. Linux Foundation started organizing similar events in Eur ...
Japan 2015, j-core developers presented a cleanroom reimplemention of the SH-2 ISA with extensions (known as the "J2 core" due to the unexpired
trademarks A trademark (also written trade mark or trade-mark) is a type of intellectual property consisting of a recognizable sign, design, or expression that identifies products or services from a particular source and distinguishes them from othe ...
). Subsequently, a design walkthrough was presented at ELC 2016. The open source
BSD The Berkeley Software Distribution or Berkeley Standard Distribution (BSD) is a discontinued operating system based on Research Unix, developed and distributed by the Computer Systems Research Group (CSRG) at the University of California, Berk ...
-licensed
VHDL The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gate ...
code for the J2 core has been proven on
Xilinx Xilinx, Inc. ( ) was an American technology and semiconductor company that primarily supplied programmable logic devices. The company was known for inventing the first commercially viable field-programmable gate array (FPGA) and creating the ...
FPGAs and on ASICs manufactured on
TSMC Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational semiconductor contract manufacturing and design company. It is the world's most valuable semiconductor company, the world' ...
's 180 nm process, and is capable of booting
µClinux μClinux is a variation of the Linux kernel, previously maintained as a fork, that targets microcontrollers without a memory management unit (MMU). It was integrated into the mainline kernel as of 2.5.46; the project continues to develop patch ...
. J2 is backwards ISA compatible with SH-2, implemented as a 5-stage pipeline with separate Instruction and Data memory interfaces, and a machine-generated Instruction Decoder supporting the densely packed and complex (relative to other RISC machines) ISA. Additional instructions are easy to add. J2 implements instructions for dynamic shift (using the SH-3 and later instruction patterns), extended atomic operations (used for threading primitives) and locking/interfaces for symmetric multiprocessor support. Plans to implement the SH-2A (as "J2+") and SH-4 (as "J4") instruction sets as the relevant patents expire in 2016–2017. Several features of SuperH have been cited as motivations for designing new cores based on this architecture: * High code density compared to other 32-bit RISC ISAs such as
ARM In human anatomy, the arm refers to the upper limb in common usage, although academically the term specifically means the upper arm between the glenohumeral joint (shoulder joint) and the elbow joint. The distal part of the upper limb between th ...
or MIPS important for cache and memory bandwidth performance * Existing
compiler In computing, a compiler is a computer program that translates computer code written in one programming language (the ''source'' language) into another language (the ''target'' language). The name "compiler" is primarily used for programs that ...
and
operating system An operating system (OS) is system software that manages computer hardware, software resources, and provides common services for computer programs. Time-sharing operating systems schedule tasks for efficient use of the system and may also in ...
support (
Linux Linux ( or ) is a family of open-source Unix-like operating systems based on the Linux kernel, an operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically packaged as a Linux distribution, which ...
,
Windows Embedded Windows IoT, formerly Windows Embedded, is a family of operating systems from Microsoft designed for use in embedded systems. Microsoft currently has three different subfamilies of operating systems for embedded devices targeting a wide market, ...
,
QNX QNX ( or ) is a commercial Unix-like real-time operating system, aimed primarily at the embedded systems market. QNX was one of the first commercially successful microkernel operating systems. The product was originally developed in the early ...
) * Extremely low ASIC fabrication costs now that the patents are expiring (around for a dual-core J2 core on TSMC's 180 nm process). * Patent- and royalty-free (BSD-licensed) implementation * Full and vibrant community support * Availability of low cost hardware development platform for zero cost FPGA tools * CPU and SoC RTL generation and integration tools, producing FPGA and ASIC portable RTL and documentation * Clean, modern design with open source design, generation, simulation and verification environment


Models

The family of SuperH CPU cores includes: * SH-1 – used in microcontrollers for deeply embedded applications (
CD-ROM A CD-ROM (, compact disc read-only memory) is a type of read-only memory consisting of a pre-pressed optical compact disc that contains data. Computers can read—but not write or erase—CD-ROMs. Some CDs, called enhanced CDs, hold both comput ...
drives,
major appliance A major appliance, also known as a large domestic appliance or large electric appliance or simply a large appliance, large domestic, or large electric, is a non-portable or semi-portable machine used for routine housekeeping tasks such as cookin ...
s, etc.) * SH-2 – used in microcontrollers with higher performance requirements, also used in automotive such as engine control units or in networking applications, and also in video game consoles, like the Sega Saturn and
Sega 32X The 32X is an add-on for the Sega Genesis video game console. Codenamed "Project Mars", it was designed to expand the power of the Genesis and serve as a transitional console into the 32-bit era until the release of the Sega Saturn. The 32X us ...
add-on. The SH-2 has also found home in many automotive engine control unit applications, including Subaru, Mitsubishi, and
Mazda , commonly referred to as simply Mazda, is a Japanese multinational automotive manufacturer headquartered in Fuchū, Hiroshima, Japan. In 2015, Mazda produced 1.5 million vehicles for global sales, the majority of which (nearly one m ...
. * SH-2A – The SH-2A core is an extension of the SH-2 core including a few extra instructions but most importantly moving to a superscalar architecture (it is capable of executing more than one instruction in a single cycle) and two five-stage pipelines. It also incorporates 15 register banks to facilitate an interrupt latency of 6 clock cycles. It is also strong in motor control application but also in multimedia, car audio, powertrain, automotive body control and office + building automation * SH-DSP – initially developed for the
mobile phone A mobile phone, cellular phone, cell phone, cellphone, handphone, hand phone or pocket phone, sometimes shortened to simply mobile, cell, or just phone, is a portable telephone that can make and receive calls over a radio frequency link whil ...
market, used later in many consumer applications requiring DSP performance for JPEG compression etc. * SH-3 – used for mobile and handheld applications such as the Jornada, strong in
Windows CE Windows Embedded Compact, formerly Windows Embedded CE, Windows Powered and Windows CE, is an operating system subfamily developed by Microsoft as part of its Windows Embedded family of products. Unlike Windows Embedded Standard, which is base ...
applications and market for many years in the car navigation market. The Cave CV1000, similar to the
Sega NAOMI Sega is a video game developer, publisher, and hardware development company headquartered in Tokyo, Japan, with multiple offices around the world. The company's involvement in the arcade game industry began as a Japan-based distributor of coin-o ...
hardware's CPU, also made use of this CPU. The Korg Electribe EMX and ESX music production units also use the SH-3. * SH-3-DSP – used mainly in multimedia terminals and networking applications, also in printers and fax machines * SH-4 – used whenever high performance is required such as car multimedia terminals,
video game console A video game console is an electronic device that outputs a video signal or image to display a video game that can be played with a game controller. These may be home consoles, which are generally placed in a permanent location connected to ...
s, or
set-top box A set-top box (STB), also colloquially known as a cable box and historically television decoder, is an information appliance device that generally contains a TV-tuner input and displays output to a television set and an external source of sign ...
es * SH-5 – used in high-end 64-bit multimedia applications * SH-X – mainstream core used in various flavours (with/without DSP or FPU unit) in engine control unit, car multimedia equipment, set-top boxes or mobile phones * SH-Mobile – SuperH Mobile Application Processor; designed to offload application processing from the baseband LSI


SH-2

The SH-2 is a 32-bit RISC architecture with a 16-bit fixed instruction length for high code density and features a hardware multiply–accumulate (MAC) block for DSP algorithms and has a five-stage pipeline. The SH-2 has a cache on all
ROM Rom, or ROM may refer to: Biomechanics and medicine * Risk of mortality, a medical classification to estimate the likelihood of death for a patient * Rupture of membranes, a term used during pregnancy to describe a rupture of the amniotic sac * ...
-less devices. It provides 16 general-purpose registers, a vector-base register, global-base register, and a procedure register. Today the SH-2 family stretches from 32 KB of on-board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others.


SH-2A

The SH-2A is an upgrade to the SH-2 core that added some 32-bit instructions. It was announced in early 2006. New features on the SH-2A core include: * Superscalar architecture: execution of 2 instructions simultaneously *
Harvard architecture The Harvard architecture is a computer architecture with separate storage and signal pathways for instructions and data. It contrasts with the von Neumann architecture, where program instructions and data share the same memory and pathways. ...
* Two 5-stage pipelines * Mixed 16-bit and 32-bit instructions * 15 register banks for interrupt response in 6 cycles. * Optional FPU The SH-2A family today spans a wide memory field from 16 KB up to and includes many ROM-less variations. The devices feature standard peripherals such as CAN,
Ethernet Ethernet () is a family of wired computer networking technologies commonly used in local area networks (LAN), metropolitan area networks (MAN) and wide area networks (WAN). It was commercially introduced in 1980 and first standardized in 198 ...
,
USB Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply (interfacing) between computers, peripherals and other computers. A broad ...
and more as well as more application-specific peripherals such as motor control timers, TFT controllers and peripherals dedicated to automotive powertrain applications.


SH-4

The SH-4 is a 32-bit RISC CPU and was developed for primary use in multimedia applications, such as Sega's
Dreamcast The is a home video game console released by Sega on November 27, 1998, in Japan; September 9, 1999, in North America; and October 14, 1999, in Europe. It was the first sixth-generation video game console, preceding Sony's PlayStation 2, N ...
and
NAOMI Naomi or Naomie may refer to: People and biblical figures * Naomi (given name), a female given name and a list of people with the name * Naomi (biblical figure), Ruth's mother-in-law in the Old Testament Book of Ruth * Naomi (Romanian singer) (bor ...
game systems. It includes a much more powerful floating-point unit and additional built-in functions, along with the standard 32-bit integer processing and 16-bit instruction size. SH-4 features include: * FPU with four floating-point multipliers, supporting 32-bit single-precision and 64-bit double-precision floats * 4D floating-point
dot-product operation In mathematics, the dot product or scalar productThe term ''scalar product'' means literally "product with a scalar as a result". It is also used sometimes for other symmetric bilinear forms, for example in a pseudo-Euclidean space. is an algeb ...
and
matrix–vector multiplication In mathematics, particularly in linear algebra, matrix multiplication is a binary operation that produces a matrix (mathematics), matrix from two matrices. For matrix multiplication, the number of columns in the first matrix must be equal to the n ...
* 128-bit floating-point bus allowing 3.2 GB/sec transfer rate from the data cache * 64-bit external data bus with 32-bit memory addressing, allowing a maximum of 4 GB addressable memory (see
Byte addressing Byte addressing in hardware architectures supports accessing individual bytes. Computers with byte addressing are sometimes called ''byte machines,'' in contrast to '' word-addressable'' architectures, ''word machines'', that access data by word ...
) with a transfer rate of 800 MB/sec * Built-in interrupt, DMA, and power management controllers There is no FPU in the custom SH4 made for Casio, the SH7305.


SH-5

The SH-5 is a 64-bit RISC CPU. Almost no non-simulated SH-5 hardware was ever released, and, unlike the still-live SH-4, support for SH-5 was dropped from GCC and Linux.


References


Citations


Bibliography

* *


External links


Renesas SuperH
Products, Tools, Manuals, App.Notes, Information
J-core Open Processor
*

*
in-progress Debian port for SH4
{{DEFAULTSORT:Superh SuperH architecture Embedded microprocessors Instruction set architectures Japanese inventions Renesas microcontrollers Open-source hardware 32-bit microprocessors