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Stream Processors, Inc. (SPI), was a
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–based fabless semiconductor company specializing in the design and manufacture of high-performance digital signal processors for applications including video surveillance, multi-function printers and
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. The company ceased operations in 2009.


Company history

Foundational work in
stream processing In computer science, stream processing (also known as event stream processing, data stream processing, or distributed stream processing) is a programming paradigm which views Stream (computing), streams, or sequences of events in time, as the centr ...
was initiated in 1995 by a research team led by MIT professor Bill Dally. In 1996, he moved to
Stanford University Leland Stanford Junior University, commonly referred to as Stanford University, is a Private university, private research university in Stanford, California, United States. It was founded in 1885 by railroad magnate Leland Stanford (the eighth ...
where he continued this work, receiving a multimillion-dollar grant from
DARPA The Defense Advanced Research Projects Agency (DARPA) is a research and development agency of the United States Department of Defense responsible for the development of emerging technologies for use by the military. Originally known as the Adva ...
with additional resources from
Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and Delaware General Corporation Law, incorporated in Delaware. Intel designs, manufactures, and sells computer compo ...
and
Texas Instruments Texas Instruments Incorporated (TI) is an American multinational semiconductor company headquartered in Dallas, Texas. It is one of the top 10 semiconductor companies worldwide based on sales volume. The company's focus is on developing analog ...
to fund the development of a project called "Imagine" - the first stream processor chip and accompanying
compiler In computing, a compiler is a computer program that Translator (computing), translates computer code written in one programming language (the ''source'' language) into another language (the ''target'' language). The name "compiler" is primaril ...
tools.


The Imagine Project

The goal of the Imagine project was to develop a C-programmable signal and image processor intended to provide both the performance density and efficiency of a special-purpose processor (such as a hard-wired ASIC). The project successfully demonstrated the advantages of stream processing. Details on the Imagine project and its results are posted o
the Stanford Imagine project page
The work also showed that a number of applications ranging from wireless baseband processing, 3D graphics,
encryption In Cryptography law, cryptography, encryption (more specifically, Code, encoding) is the process of transforming information in a way that, ideally, only authorized parties can decode. This process converts the original representation of the inf ...
, IP forwarding to video processing could take advantage of the efficiency of stream processing. This research inspired other designs such as GPUs from ATI Technologies as well as the Cell microprocessor from
Sony is a Japanese multinational conglomerate (company), conglomerate headquartered at Sony City in Minato, Tokyo, Japan. The Sony Group encompasses various businesses, including Sony Corporation (electronics), Sony Semiconductor Solutions (i ...
,
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, and
IBM International Business Machines Corporation (using the trademark IBM), nicknamed Big Blue, is an American Multinational corporation, multinational technology company headquartered in Armonk, New York, and present in over 175 countries. It is ...
. The main deliverables from the Imagine program included: * The Imagine Stream Architecture * The Stream programming model * Software development tools * Programmable graphics and real-time media applications * VLSI prototype (fabricated by TI) * Stream processor development platform (a prototype development board)


SPI established

Dally, together with other team members, obtained a license from Stanford to commercialize the resulting technology. Stream Processors, Incorporated (SPI) was incorporated in California in 2004. Professor Dally remained at Stanford and the company hired industry veteran Chip Stearns to become the President and CEO in December of that year. Through June, 2006 SPI has been able to raise a total of $26M from a trio of notable
venture capital Venture capital (VC) is a form of private equity financing provided by firms or funds to start-up company, startup, early-stage, and emerging companies, that have been deemed to have high growth potential or that have demonstrated high growth in ...
firms – Austin Ventures,
Norwest Venture Partners Norwest Venture Partners (Norwest) is an American venture and growth equity investment firm. The firm targets early to late-stage venture and growth equity investments across several sectors, including cloud computing and information technology, ...
and the Woodside Fund. The company launched its first two products concurrently with the International Solid State Circuits Conference ( ISSCC) in February, 2006 and has introduced two others since. SPI has headquarters located in
Sunnyvale, California Sunnyvale () is a city located in the Santa Clara Valley in northwestern Santa Clara County, California, United States. Sunnyvale lies along the historic El Camino Real (California), El Camino Real and U.S. Route 101 in California, Highway 1 ...
, as well as a software development group (SPI Software Technologies Pvt. Ltd) located in Bangalore, India. In January 2009 Co-Founder Prof. Bill Dally accepted a position as Chief Scientist with
NVIDIA Nvidia Corporation ( ) is an American multinational corporation and technology company headquartered in Santa Clara, California, and incorporated in Delaware. Founded in 1993 by Jensen Huang (president and CEO), Chris Malachowsky, and Curti ...
Corporation. At the same time he resigned as chairman. In an interview Dally reflected on his experiences with startups: " I have done several chip startups myself. It’s getting hard. The ante is very high. If you do a chip startup, you need patient investors with very deep pockets. It’s many tens of millions of dollars to get to a first product and $50 million to get to profits. That’s very difficult to do because investors want an exit some multiple over that investment. I am hoping we return to the days of frequent IPOs and get beyond the fire-sale acquisitions. That’s not what you can see right now. If it’s a programmable chip, the cost is even more." In the summer of 2009 CEO Stearns left the company and was replaced by Mike Fister, an executive with senior level experience at
Cadence Design Systems Cadence Design Systems, Inc. (stylized as cādence)Investor's Business DailCEO Lip-Bu Tan Molds Troubled Cadence Into Long-Term LeaderRetrieved November 12, 2020 is an American multinational corporation, multinational technology and computational ...
and
Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and Delaware General Corporation Law, incorporated in Delaware. Intel designs, manufactures, and sells computer compo ...
. In September 2009 the company ceased operations.


Technology

Similar to graphics and scientific computing, media and signal processing are characterized by available data-parallelism, locality and a high computation to global memory access ratio.
Stream processing In computer science, stream processing (also known as event stream processing, data stream processing, or distributed stream processing) is a programming paradigm which views Stream (computing), streams, or sequences of events in time, as the centr ...
exploits these characteristics using data- parallel processing fed by a
distributed memory In computer science, distributed memory refers to a Multiprocessing, multiprocessor computer system in which each Central processing unit, processor has its own private Computer memory, memory. Computational tasks can only operate on local data ...
hierarchy managed by the compiler. The main challenge for next generation massively parallel processors is data bandwidth, not computational resources. Unlike most conventional processors, the technology does not rely on a hardware cache – instead data movement is explicitly managed by the compiler and hardware. The execution model is based on accelerating performance-critical functions (kernels) that process and produce data records (streams). Kernels and streams are scheduled at compile-time and moved to on-chip memory at runtime via a scoreboard. The compiler analyses data live times of streams to optimize allocation and minimize external memory bandwidth needs. Streams and kernels loads can overlap with execution to improve latency tolerance and the explicit data movement provides predictable performance. There are no
CPU cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, whi ...
misses and the design presents a single-core model to the programmer – data-parallelism is within the kernels.


Architecture

The architecture includes a host CPU (System MIPS) for system-level tasks and a DSP Coprocessor Subsystem where the DSP MIPS runs the main threads that make kernel
function call In computer programming, a function (also procedure, method, subroutine, routine, or subprogram) is a callable unit of software logic that has a well-defined interface and behavior and can be invoked multiple times. Callable units provide a p ...
s to the Data Parallel Unit (DPU). For users that use libraries, and don't intend to develop DSP code, the architecture is a MIPS-based system-on-a-chip with an
API An application programming interface (API) is a connection between computers or between computer programs. It is a type of software interface, offering a service to other pieces of software. A document or standard that describes how to build ...
to a “black box” coprocessor. The DPU Dispatcher receives kernel function calls to manage runtime kernel and stream loads. One kernel at a time is executed across the lanes, operating on local stream data stored in the Lane Register File of each lane. Each lane has a set of VLIW ALUs and distributed operand register files (ORF) allow for a large working data set and processing bandwidth exceeding 1 TeraByte/s. The Stream Load/Store Unit provides gather/scatter with a wide variety of access patterns. The InterLane Switch is a
compiler In computing, a compiler is a computer program that Translator (computing), translates computer code written in one programming language (the ''source'' language) into another language (the ''target'' language). The name "compiler" is primaril ...
-scheduled, full crossbar for high-speed access between lanes.


Tools

SPI's RapiDev Tools Suite leverages the predictability of
stream processing In computer science, stream processing (also known as event stream processing, data stream processing, or distributed stream processing) is a programming paradigm which views Stream (computing), streams, or sequences of events in time, as the centr ...
to provide a fast path to optimized results using C programming. Starting with C reference code, the Fast Functional Debugger (FFD) library plugs into standard tools, such as
Microsoft Visual Studio Visual Studio is an integrated development environment (IDE) developed by Microsoft. It is used to develop computer programs including websites, web apps, web services and mobile apps. Visual Studio uses Microsoft software development platforms ...
and GNU, and simulates the DPU to support re-structuring code to kernels and streams. Because kernels are statically scheduled and data movement is explicit, DPU cycle-accuracy can be obtained even at this functional high level. This is one source of the predictability of the architecture. For targeting code to the device, the Stream Processor Compiler (SPC) generates the VLIW executable and pre-processed C code that is compiled/ linked via standard GCC for MIPS. SPC allocates streams in the Lane Register Files and provides dependency information for the kernel function calls. Software pipelining and
loop unrolling Loop unrolling, also known as loop unwinding, is a loop transformation technique that attempts to optimize a program's execution speed at the expense of its binary size, which is an approach known as space–time tradeoff. The transformation c ...
are supported. Branch penalties are avoided by predicated selects and larger conditionals use conditional streams. Running under Eclipse, the Target Code Simulator provides comprehensive Host or Device binary code simulation with breakpoint and single-stepping capabilities with bandwidth and load statistics. A kernel view shows the VLIW pipeline for kernel optimizations, and a stream view shows kernel execution and stream loads to review global data movement for system profiling.


Products

SPI currently markets its Storm-1 family, that includes four fully software programmable DSPs of varying performance levels. Note: GMACS stands for Giga (billions of) Multiply-Accumulate operations per Second, a common measure of DSP performance.


Support hardware and software

* The RapiDev tools suite delivers a fast, predictable path to optimized results, eliminating the complexities of assembly coding or manual cache management * The Storm-1 DevKit is a PCI-based software development platform * IP Camera Reference Design runs standard Linux 2.6 and supports multiple simultaneous
codec A codec is a computer hardware or software component that encodes or decodes a data stream or signal. ''Codec'' is a portmanteau of coder/decoder. In electronic communications, an endec is a device that acts as both an encoder and a decoder o ...
s (e.g. H.264,
MPEG-4 MPEG-4 is a group of international standards for the compression of digital audio and visual data, multimedia systems, and file storage formats. It was originally introduced in late 1998 as a group of audio and video coding formats and related ...
and MJPEG), arbitrary resolutions,
CMOS Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss ", , ) is a type of MOSFET, metal–oxide–semiconductor field-effect transistor (MOSFET) semiconductor device fabrication, fabrication process that uses complementary an ...
and CCD sensor processing as well as video analytics in a fully software-programmable platform * Video Streamer Reference Design supports eight 4CIF input channels of video compressed to H.264 and a
Gigabit Ethernet In computer networking, Gigabit Ethernet (GbE or 1 GigE) is the term applied to transmitting Ethernet frames at a rate of a gigabit per second. The most popular variant, 1000BASE-T, is defined by the IEEE 802.3ab standard. It came into use in ...
output


References


External links


The Imagine Project (Stanford) website
{{Coord, 37, 22, 59.48, N, 122, 04, 42.08, W, type:landmark_region:US-CA, display=title Fabless semiconductor companies Electronics companies established in 2004 Companies based in Sunnyvale, California Defunct semiconductor companies of the United States Defunct computer companies of the United States Defunct computer hardware companies