The PowerPC e200 is a family of

32-bit In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculation ...

Power ISA Power ISA is a reduced instruction set computer (RISC) instruction set architecture (ISA) currently developed by the OpenPOWER Foundation, led by IBM. It was originally developed by IBM and the now-defunct Power.org industry group. Power IS ...

microprocessor A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circu ...

cores developed by

Freescale Freescale Semiconductor, Inc. was an American semiconductor manufacturer. It was created by the divestiture of the Semiconductor Products Sector of Motorola in 2004. Freescale focused their integrated circuit products on the automotive, embed ...

for primary use in automotive and industrial control systems. The cores are designed to form the CPU part in

system-on-a-chip A system on a chip or system-on-chip (SoC ; pl. ''SoCs'' ) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory ...

(SoC) designs with speed ranging up to 600 MHz, thus making them ideal for embedded applications. The e200 core is developed from the

MPC5xx The MPC5xx family of processors such as the MPC555 and MPC565 are 32-bit PowerPC embedded microprocessors that operate between 40 and 66 MHz and are frequently used in automotive applications including engine and transmission controllers. Delp ...

family processors, which in turn is derived from the MPC8xx core in the

PowerQUICC PowerQUICC is the name for several PowerPC- and Power ISA-based microcontrollers from Freescale Semiconductor. They are built around one or more PowerPC cores and the Communications Processor Module ( QUICC Engine) which is a separate RISC core sp ...

SoC processors. e200 adheres to the Power ISA v.2.03 as well as the previous ''Book E'' specification. All e200 core based microprocessors are named in the MPC55xx and MPC56xx/JPC56x scheme, not to be confused with the MPC52xx processors which is based on the

PowerPC e300 The PowerPC e300 is a family of 32-bit PowerPC microprocessor cores developed by Freescale for primary use in system-on-a-chip (SoC) designs with speed ranging up to 800 MHz, thus making them ideal for embedded applications. The e300 is ...

core. In April 2007 Freescale and IPextreme opened up the e200 cores for licensing to other manufacturers.

Continental AG Continental AG, commonly known as Continental or colloquially as Conti, is a German multinational automotive parts manufacturing company specializing in tires, brake systems, interior electronics, automotive safety, powertrain and chassis compo ...

and Freescale are developing SPACE, a tri-core e200 based processor designed for electronic brake systems in cars.

STMicroelectronics STMicroelectronics N.V. commonly referred as ST or STMicro is a Dutch multinational corporation and technology company of French-Italian origin headquartered in Plan-les-Ouates near Geneva, Switzerland and listed on the French stock market. ST ...

and Freescale have jointly developed

microcontrollers A microcontroller (MCU for ''microcontroller unit'', often also MC, UC, or μC) is a small computer on a single VLSI integrated circuit (IC) chip. A microcontroller contains one or more CPUs ( processor cores) along with memory and programmabl ...

for automotive applications based on e200 in the MPC56xx/SPC56x family.

Cores

The e200 family consists of six cores, from simple low-end to complex high-end in nature.

e200z0

The simplest core, e200z0 features an in order, four stage

pipeline Pipeline may refer to: Electronics, computers and computing * Pipeline (computing), a chain of data-processing stages or a CPU optimization found on ** Instruction pipelining, a technique for implementing instruction-level parallelism within a s ...

. It has no MMU, no cache, and no FPU. It uses the variable bit length (VLE) part of the Power ISA, which uses 16-bit versions of the otherwise standard 32-bit PowerPC Book E ISA, thus reducing code footprint by up to 30%. It has a single 32-bit

AMBA Amba or AMBA may refer to: Title * Amba Hor, alternative name for Abhor and Mehraela, Christian martyrs * Amba Sada, also known as Psote, Christian bishop and martyr in Upper Egypt Given name * Amba, the traditional first name given to the first ...

2.0v6 bus interface. The load/store unit is pipelined, has a 1-cycle load latency and supports throughput of one load or store operation per cycle. The e200z0 is used in the MPC5510 as an optional co-processor alongside an e200z1 core, making that chip a

multicore A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions (such ...

processor. e200z0 is available as co-processors to other e200 based processors as well as very low end stand alone processors.

e200z1

The e200z1 has a four-stage, single-issue pipeline with a branch prediction unit and an 8 entry MMU, no cache and no FPU. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a dual 32-bit AMBA 2.0v6 bus interface. The load/store unit is pipelined, has a 1-cycle load latency and supports throughput of one load or store operation per cycle.

e200z3

The e200z3 has a four-stage, single-issue pipeline with a branch prediction unit, a 16 entry MMU and a

SIMD Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal (part of the hardware design) and it can be directly accessible through an instruction set architecture (ISA), but it shoul ...

capable FPU. It has no cache. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a dual 64-bit AMBA 2.0v6 bus interface. The load/store unit is pipelined, has a 1-cycle load latency and supports throughput of one load or store operation per cycle.

e200z4

The e200z4 has a five-stage, dual-issue pipeline with a branch prediction unit, a 16 entry MMU, signal processing extension (SPE), a SIMD capable single precision FPU and a 4 Kilobyte 2/4-way set associative instruction L1 cache (Pseudo round-robin replacement algorithm). It has no data cache. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a dual 64-bit bus AMBA 2.0v6 interface. The load/store unit is pipelined, has a 2-cycle load latency and supports throughput of one load or store operation per cycle. Depending on the derivative may support SPE or LSP.

e200z6

The e200z6 has a seven-stage, single-issue pipeline with a branch prediction unit, a 32 entry MMU, signal processing extensions (SPE), a SIMD capable single-precision FPU and an 8-way set associative 32 KiB unified data/instruction L1 cache. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a single 64-bit bus AMBA 2.0v6 interface. The load/store unit is pipelined, has a 3-cycle load latency and supports throughput of one load or store operation per cycle.

e200z7

The e200z7 has a ten-stage, dual-issue pipeline with a branch prediction unit, a 32 entry MMU, a SIMD capable single-precision FPU and 16-KB, 4 way set-associative Harvard instruction and data L1 caches. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a 32-bit bus AMBA 2.0v6 interface for the address bus, and a 64-bit data bus (plus attributes and control on each bus). The load/store unit is pipelined, has a 3-cycle load latency and supports throughput of one load or store operation per cycle. Depending on the derivative may support SPE, SPE v1.1 or SPE v2.

References

Freescale's MPC55xx page

ST's SPC5 page

IPextremes e200 licensing page

Freescale’s e200 Core Family, Overview and Licensing Model, White paper

Multi-Core Design: Key Challenges and Opportunities – Power.org
* Halfhill, Tom R. (2 April 2007). "Freescale Licenses Power Cores". ''

Microprocessor Report ''Microprocessor Report'' is a newsletter covering the microprocessor industry. The publication is accessible only to paying subscribers. To avoid bias, it does not take advertisements. The publication provides extensive analysis of new high-perfo ...

''. {{Motorola_processors E200 E200 E200 Power microprocessors