Moscow Center Of SPARC Technologies (MCST)
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MCST (russian: МЦСТ, acronym for Moscow Center of SPARC Technologies) is a Russian
microprocessor A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circ ...
company that was set up in 1992. Different types of processors made by MCST were used in personal computers, servers and computing systems. MCST develops microprocessors based on two different instruction set architecture (ISA): '' Elbrus'' and ''
SPARC SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system develope ...
''. MCST is a direct descendant of the
Lebedev Institute of Precision Mechanics and Computer Engineering Lebedev Institute of Precision Mechanics and Computer Engineering (IPMCE) is a Russian research institution. It used to be a Soviet Academy of Sciences organization in Soviet times. The institute specializes itself in the development of: * Computer ...
. MCST is the base organization of the Department of Informatics and Computer Engineering of the
Moscow Institute of Physics and Technology Moscow Institute of Physics and Technology (MIPT; russian: Московский Физико-Технический институт, also known as PhysTech), is a public research university located in Moscow Oblast, Russia. It prepares speciali ...
. MCST develops the Elbrus processor architecture and the eponymous family of universal
VLIW Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP). Whereas conventional central processing units (CPU, processor) mostly allow programs to specify instructions to exe ...
microprocessors based on it with the participation of . The name "Elbrus" has been given the
backronym A backronym is an acronym formed from an already existing word by expanding its letters into the words of a phrase. Backronyms may be invented with either serious or humorous intent, or they may be a type of false etymology or folk etymology. The ...
"ExpLicit Basic Resources Utilization Scheduling".


Products

* '' Elbrus 1'' (1973) was the fourth generation Soviet computer, developed by Vsevolod Burtsev. Implements tag-based architecture and
ALGOL ALGOL (; short for "Algorithmic Language") is a family of imperative computer programming languages originally developed in 1958. ALGOL heavily influenced many other languages and was the standard method for algorithm description used by the ...
as system language like the
Burroughs large systems The Burroughs Large Systems Group produced a family of large 48-bit mainframes using stack machine instruction sets with dense syllables.E.g., 12-bit syllables for B5000, 8-bit syllables for B6500 The first machine in the family was the B5000 in ...
. A side development was an update of the 1965
BESM-6 BESM-6 (russian: БЭСМ-6, short for ''Большая электронно-счётная машина'', i.e. 'Large Electronic Calculating Machine') was a Soviet electronic computer of the BESM series. It was the first Soviet second-generation ...
as Elbrus-1K2. * '' Elbrus 2'' (1977) was a 10-processor computer, considered the first Soviet supercomputer, with superscalar RISC processors. Re-implementation of the Elbrus 1 architecture with faster ECL chips. * ''
Elbrus 3 Mount Elbrus ( rus, links=no, Эльбрус, r=Elbrus, p=ɪlʲˈbrus; kbd, Ӏуащхьэмахуэ, 'uaşhəmaxuə; krc, Минги тау, Mingi Taw) is the highest and most prominent peak in Russia and Europe. It is situated in the we ...
'' (1986) was a 16-processor computer developed by Boris Babayan. Differing completely from the architecture of both Elbrus 1 and Elbrus 2, it employed a
VLIW Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP). Whereas conventional central processing units (CPU, processor) mostly allow programs to specify instructions to exe ...
architecture. * '' Elbrus-90micro'' (1998–2010) is a computer line based on
SPARC SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system develope ...
instruction set architecture (ISA) microprocessors: MCST R80, R150, R500, R500S,
MCST-4R The MCST R1000 (russian: МЦСТ R1000) is a 64-bit microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC. During development this microprocessor was designated as MCST-4R. MCST R1000 Highlights *implement ...
(MCST-R1000) and
MCST-R2000 The MCST R2000 (russian: МЦСТ R2000) is a 64-bit microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC. MCST R2000 Highlights *implements the SPARC V9 instruction set architecture (ISA) * octa-core *co ...
working at 80, 150, 500, 1000 and 2000 MHz. * '' Elbrus-3M1'' (2005) is a two-processor computer based on the
Elbrus 2000 The Elbrus 2000, E2K (russian: Эльбрус 2000) is a Russian 512-bit wide VLIW microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC. It supports two instruction set architectures (ISA): * Elbrus VLIW ...
microprocessor employing
VLIW Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP). Whereas conventional central processing units (CPU, processor) mostly allow programs to specify instructions to exe ...
architecture working at 300 MHz. It is a further development of the ''Elbrus 3'' (1986). * ''
Elbrus МВ3S1/C Mount Elbrus ( rus, links=no, Эльбрус, r=Elbrus, p=ɪlʲˈbrus; kbd, Ӏуащхьэмахуэ, 'uaşhəmaxuə; krc, Минги тау, Mingi Taw) is the highest and most prominent peak in Russia and Europe. It is situated in the we ...
'' (2009) is a ccNUMA 4-processor computer based on Elbrus-S microprocessor working at 500 MHz. * '' Elbrus-2S+'' (2011) is a dual-core
Elbrus 2000 The Elbrus 2000, E2K (russian: Эльбрус 2000) is a Russian 512-bit wide VLIW microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC. It supports two instruction set architectures (ISA): * Elbrus VLIW ...
based microprocessor working at 500 MHz, with capacity to calculate 16 GFlops. * ''
Elbrus-2SM Elbrus-2S+ (russian: Эльбрус-2С+) is a multi-core microprocessor based on the Elbrus 2000 architecture developed by Moscow Center of SPARC Technologies (MCST). There are multiple reports regarding the evolution of this technology for the ...
'' (2014) is a dual-core
Elbrus 2000 The Elbrus 2000, E2K (russian: Эльбрус 2000) is a Russian 512-bit wide VLIW microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC. It supports two instruction set architectures (ISA): * Elbrus VLIW ...
based microprocessor working at 300 MHz, with capacity to calculate 9.6 GFlops. * '' Elbrus-4S'' (2014) is a quad-core
Elbrus 2000 The Elbrus 2000, E2K (russian: Эльбрус 2000) is a Russian 512-bit wide VLIW microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC. It supports two instruction set architectures (ISA): * Elbrus VLIW ...
based microprocessor working at 800 MHz, with capacity to calculate 50 GFlops. * ''
Elbrus-8S The Elbrus-8S (russian: Эльбрус-8С) is a Russian 28 nanometer 8-core microprocessor developed by Moscow Center of SPARC Technologies (MCST). The first prototypes were produced by the end of 2014 and serial production started in 2016. The ...
'' (2014–2015) is an octa-core
Elbrus 2000 The Elbrus 2000, E2K (russian: Эльбрус 2000) is a Russian 512-bit wide VLIW microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC. It supports two instruction set architectures (ISA): * Elbrus VLIW ...
based microprocessor working at 1300 MHz, with capacity to calculate 250 GFlops. * '' Elbrus-8SV'' (2018) is an octa-core
Elbrus 2000 The Elbrus 2000, E2K (russian: Эльбрус 2000) is a Russian 512-bit wide VLIW microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC. It supports two instruction set architectures (ISA): * Elbrus VLIW ...
based microprocessor working at 1500 MHz, with capacity to calculate 576 GFlops. * '' Elbrus-16S'' (2021) is 16-core
Elbrus 2000 The Elbrus 2000, E2K (russian: Эльбрус 2000) is a Russian 512-bit wide VLIW microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC. It supports two instruction set architectures (ISA): * Elbrus VLIW ...
based microprocessor working at 2000 MHz, with capacity to calculate 750 GFlops at double precision and 1.5 TFlops at single precision operations. * ''Elbrus-32S'' (2021) is a dual-core
Elbrus 2000 The Elbrus 2000, E2K (russian: Эльбрус 2000) is a Russian 512-bit wide VLIW microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC. It supports two instruction set architectures (ISA): * Elbrus VLIW ...
based microprocessor working at 2000 MHz.


See also

*
History of computing in the Soviet Union The history of computing in the Soviet Union began in the late 1940s, when the country began to develop its Small Electronic Calculating Machine (MESM) at the Kiev Institute of Electrotechnology in Feofaniya. Initial ideological opposition to ...
*
Information technology in Russia The Information technology sector in Russia employed around 300,000 people in 2012, and contributed 1.2% of the country's GDP in 2015. The sector is concentrated in the cities of Moscow and Saint Petersburg. History The Russian IT sector drew comp ...


References


External links


Elbrus website in Russian
Computer companies established in 1992 Russian companies established in 1992 Computer companies of Russia Russian brands Companies based in Moscow Information technology in Russia {{Russia-company-stub