MCST-R500S
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MCST-R500S
The MCST R500S (russian: МЦСТ R500S) is a 32-bit system-on-a-chip, developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC. MCST R500S Highlights *implements the SPARC V8 instruction set architecture (ISA) *dual-core *the two cores can work in redundancy to increase reliability of the system. *core specifications: **in-order, single-issue **5-stage integer pipeline **7-stage floating-point pipeline **16 KB L1 instruction cache **32 KB L1 data cache *shared 512KB L2 cache *integrated controllers: **memory **PCI **RDMA (to connect with other MCST R500S) **MSI ( Mbus and SBus) **EBus **PS/2 **Ethernet 100 **SCSI-2 **RS-232 *500 МHz clock rate *130 nm process The 130 nanometer (130 nm) process refers to the level of semiconductor process technology that was reached in the 2000–2001 timeframe, by most leading semiconductor companies, like Intel, Texas Instruments, IBM, and TSMC. The origin of the 1 ... *die size 100 mm2 *~45 million transi ...
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130 Nanometer
The 130 nanometer (130 nm) process refers to the level of semiconductor process technology that was reached in the 2000–2001 timeframe, by most leading semiconductor companies, like Intel, Texas Instruments, IBM, and TSMC. The origin of the 130 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS). Some of the first CPUs manufactured with this process include Intel Tualatin family of Pentium III processors. Processors using 130 nm manufacturing technology * Motorola PowerPC 7447 and 7457 2002 * IBM Gekko (Nintendo GameCube) * IBM PowerPC G5 970 - October 2002 - June 2003 * Intel Pentium III Tualatin - 2001-06 * Intel Celeron Tualatin-256 - 2001-10-02 * Intel Pentium M Banias - 2003-03-12 * Intel Pentium 4 Northwood - 2002-01-07 * Intel Celeron Northwood-128 - 2002-09-18 * Intel Xeon Prestonia and Gallatin - 2002-02-25 * VIA C3 - 2001 * AMD ...
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Moscow Center Of SPARC Technologies (MCST)
MCST (russian: МЦСТ, acronym for Moscow Center of SPARC Technologies) is a Russian microprocessor company that was set up in 1992. Different types of processors made by MCST were used in personal computers, servers and computing systems. MCST develops microprocessors based on two different instruction set architecture (ISA): '' Elbrus'' and ''SPARC''. MCST is a direct descendant of the Lebedev Institute of Precision Mechanics and Computer Engineering. MCST is the base organization of the Department of Informatics and Computer Engineering of the Moscow Institute of Physics and Technology. MCST develops the Elbrus processor architecture and the eponymous family of universal VLIW microprocessors based on it with the participation of . The name "Elbrus" has been given the backronym "ExpLicit Basic Resources Utilization Scheduling". Products * '' Elbrus 1'' (1973) was the fourth generation Soviet computer, developed by Vsevolod Burtsev. Implements tag-based architecture and ...
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TSMC
Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational corporation, multinational semiconductor contract manufacturing and design company. It is the world's most valuable semiconductor company, the world's largest dedicated independent (Pure-play semiconductor foundry, pure-play) Foundry (electronics), semiconductor foundry, and one of Taiwan's largest companies, with its headquarters and main operations located in the Hsinchu Science Park in Hsinchu. It is majority owned by foreign investors. Founded in Taiwan in 1987 by Morris Chang, TSMC was the world's first dedicated semiconductor foundry and has long been the leading company in its field. When Chang retired in 2018, after 31 years of TSMC leadership, Mark Liu became chairman and C. C. Wei became Chief Executive. It has been listed on the Taiwan Stock Exchange (TWSE: 2330) since 1993; in 1997 it became the first Taiwanese company to be listed on the New York ...
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SPARC V8
SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s. The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 computer workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors. SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992. SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995. Later, SPARC processors were used in sym ...
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System-on-a-chip
A system on a chip or system-on-chip (SoC ; pl. ''SoCs'' ) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory interfaces, on-chip input/output devices, input/output interfaces, and secondary storage interfaces, often alongside other components such as radio modems and a graphics processing unit (GPU) – all on a single substrate or microchip. It may contain digital, analog, mixed-signal, and often radio frequency signal processing functions (otherwise it is considered only an application processor). Higher-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (such as LPDDR and eUFS or eMMC, respectively) chips, that may be layered on top of the SoC in what's known as a package on package (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may use separate wireless modems. ...
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Dual-core
A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions (such as add, move data, and branch) but the single processor can run instructions on separate cores at the same time, increasing overall speed for programs that support multithreading or other parallel computing techniques. Manufacturers typically integrate the cores onto a single integrated circuit die (known as a chip multiprocessor or CMP) or onto multiple dies in a single chip package. The microprocessors currently used in almost all personal computers are multi-core. A multi-core processor implements multiprocessing in a single physical package. Designers may couple cores in a multi-core device tightly or loosely. For example, cores may or may not share caches, and they may implement message passing or shared-memory inter-core communicat ...
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Redundancy (engineering)
In engineering, redundancy is the intentional duplication of critical components or functions of a system with the goal of increasing reliability of the system, usually in the form of a backup or fail-safe, or to improve actual system performance, such as in the case of GNSS receivers, or multi-threaded computer processing. In many safety-critical systems, such as fly-by-wire and hydraulic systems in aircraft, some parts of the control system may be triplicated, which is formally termed triple modular redundancy (TMR). An error in one component may then be out-voted by the other two. In a triply redundant system, the system has three sub components, all three of which must fail before the system fails. Since each one rarely fails, and the sub components are expected to fail independently, the probability of all three failing is calculated to be extraordinarily small; it is often outweighed by other risk factors, such as human error. Redundancy may also be known by the terms "m ...
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Instruction Pipeline
In computer engineering, instruction pipelining or ILP is a technique for implementing instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps (the eponymous "pipeline") performed by different processor units with different parts of instructions processed in parallel. Concept and motivation In a pipelined computer, instructions flow through the central processing unit (CPU) in stages. For example, it might have one stage for each step of the von Neumann cycle: Fetch the instruction, fetch the operands, do the instruction, write the results. A pipelined computer usually has "pipeline registers" after each stage. These store information from the instruction and calculations so that the logic gates of the next stage can do the next step. This arrangement lets the CPU complete an instruction on each clock cycle. It is common for ...
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MBus (SPARC)
MBus is a computer bus designed and implemented by Sun Microsystems for communication between high speed computer system components, such as the central processing unit, motherboard and main memory. SBus is used in the same machines to connect add-on cards to the motherboard. MBus was first used in Sun's first multiprocessor SPARC-based system, the SPARCserver 600MP series (launched in 1991), and later found use in the SPARCstation 10 and SPARCstation 20 workstations. The bus permits the integration of several microprocessors on a single motherboard, in a multiprocessing configuration with up to eight CPUs packaged in detachable MBus modules. In practice, the number of processors per MBus is limited to four. Single processor systems were also sold that use the MBus protocol internally, but with the CPUs permanently attached to the motherboard to lower manufacturing costs. MBus specifies a 64-bit datapath, which uses 36-bit physical addressing, giving an address space of 64 ...
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SBus
SBus is a computer bus system that was used in most SPARC-based computers (including all SPARCstations) from Sun Microsystems and others during the 1990s. It was introduced by Sun in 1989 to be a high-speed bus counterpart to their high-speed SPARC processors, replacing the earlier (and by this time, outdated) VMEbus used in their Motorola 68020- and 68030-based systems and early SPARC boxes. When Sun moved to open the SPARC definition in the early 1990s, SBus was likewise standardized and became IEEE-1496. In 1997 Sun started to migrate away from SBus to the Peripheral Component Interconnect (PCI) bus, and today SBus is no longer used. The industry's first third-party SBus cards were announced in 1989 by Antares Microsystems; these were a 10BASE2 Ethernet controller, a SCSI-SNS host adapter, a parallel port, and an 8-channel serial controller. The specification was published by Edward H. Frank and James D. Lyle. A technical guide to the bus was published in 1992 in book form b ...
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Clock Rate
In computing, the clock rate or clock speed typically refers to the frequency at which the clock generator of a processor can generate pulses, which are used to synchronize the operations of its components, and is used as an indicator of the processor's speed. It is measured in the SI unit of frequency hertz (Hz). The clock rate of the first generation of computers was measured in hertz or kilohertz (kHz), the first personal computers (PCs) to arrive throughout the 1970s and 1980s had clock rates measured in megahertz (MHz), and in the 21st century the speed of modern CPUs is commonly advertised in gigahertz (GHz). This metric is most useful when comparing processors within the same family, holding constant other features that may affect performance. Determining factors Binning Manufacturers of modern processors typically charge premium prices for processors that operate at higher clock rates, a practice called binning. For a given CPU, the clock rates are determined at th ...
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SPARC Microprocessors
SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s. The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 computer workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors. SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992. SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995. Later, SPARC processors were used in sym ...
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