Xeon 3000-series (uniprocessor)

" Lynnfield" (45 nm)

* Based on

Nehalem microarchitecture Nehalem is the codename for Intel's 45 nm microarchitecture released in November 2008. It was used in the first-generation of the Intel Core i5 and i7 processors, and succeeds the older Core microarchitecture used on Core 2 processors. The ...

* Uni-processor only * All models except X3430 support

Hyper-Threading Hyper-threading (officially called Hyper-Threading Technology or HT Technology and abbreviated as HTT or HT) is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multip ...

* All models support: '' MMX,

XD bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...

, SSE,

SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier Streamin ...

SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...

SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitecture ...

SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; mor ...

SSE4.2 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core (microarchitecture), Core microarchitecture and AMD K10, AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vag ...

x64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mo ...

SpeedStep Enhanced SpeedStep is a series of dynamic frequency scaling technologies (codenamed Geyserville and including SpeedStep, SpeedStep II, and SpeedStep III) built into some Intel microprocessors that allow the clock speed of the processor to be dynami ...

Turbo Boost Intel Turbo Boost is Intel's trade name for central processing units (CPUs) dynamic frequency scaling feature that automatically raises certain versions of its operating frequency when demanding tasks are running, thus enabling a higher resulting ...

Smart Cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which ...

VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...

, EPT,

VT-d x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...

, TXT, ECC'' *

Die Die, as a verb, refers to death, the cessation of life. Die may also refer to: Games * Die, singular of dice, small throwable objects used for producing random numbers Manufacturing * Die (integrated circuit), a rectangular piece of a semicondu ...

size: 296 mm² * Steppings: B1

" Bloomfield" (45 nm)

* Based on

* Uni-processor only * Quad Core models support: ''

'' * All models support: '' MMX,

, SSE,

, EPT, ECC'' *

size: 263 mm² * Steppings: D0

" Jasper Forest" (45 nm)

* Based on

* Uni-processor only * LC3528 supports: ''

'' * All models support: '' MMX,

, SSE,

, EPT,

, ECC'' *

size: 263 mm² * Steppings: B0

" Clarkdale" ( MCP, 32 nm)

* Based on Westmere microarchitecture * Uni-processor only * L3406 supports

* All models support: '' MMX,

, SSE,

, EPT,

, TXT, ECC'' *

size: 81 mm² (CPU Component) * Steppings: C2

"
Gulftown Gulftown or Westmere-EP is the codename of an up to six-core hyperthreaded Intel processor able to run up to 12 threads in parallel. It is based on Westmere microarchitecture, the 32 nm shrink of Nehalem. Originally rumored to be called the Int ...
" (32 nm)

* Based on Westmere microarchitecture * Uniprocessor-only systems * All models support: ''

'' * All models support: '' MMX,

, SSE,

AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...

, EPT,

, TXT, ECC'' *

size: 240 mm² * Steppings: B1

Xeon 5000-series (dual-processor)

" Gainestown" (45 nm)

* Based on

* All models support: '' MMX, SSE,

, Demand-Based Switching (Intel's Server

EIST Enhanced SpeedStep is a series of dynamic frequency scaling technologies (codenamed Geyserville and including SpeedStep, SpeedStep II, and SpeedStep III) built into some Intel microprocessors that allow the clock speed of the processor to be dynami ...

Intel 64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...

(an

NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...

implementation),

Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...

, Intel EPT,

Intel VT-d x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...

Intel VT-c x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...

, Intel x8 SDDC'' * All models support: ''

'' except E5502, E5503, E5504, E5506, L5506, E5507 * All models support dual-processor configurations *

size: 263 mm² * Steppings: D0

" Jasper Forest" (45 nm)

* Based on

* All models support: '' MMX, SSE,

, Demand-Based Switching (Intel's Server

(an

implementation),

, Intel EPT,

, Intel x8 SDDC'' * EC5549, LC5528, and LC5518 support: ''

'' *

size: 263 mm² * Steppings: B0

" Westmere-EP" (32 nm) Efficient Performance

* Based on Westmere microarchitecture * All models support: '' MMX, SSE,

, Enhanced Intel

Technology (EIST),

, XD bit (an

implementation), TXT,

, Intel EPT,

, Intel x8 SDDC,

'', ''

'' except E5603, E5606, E5607, L5609 * Dual-socket configurations supported *

size: 240 mm² * Steppings: B1

Xeon 7000-series (multiprocessor)

"
Beckton Beckton is a suburb in east London, England, located east of Charing Cross and part of the London Borough of Newham. Adjacent to the River Thames, the area consisted of unpopulated marshland known as the East Ham Levels in the parishes of Bark ...
" (45 nm)

* Based on

* All models support: '' MMX, SSE,

, Enhanced Intel

Technology (EIST),

, XD bit (an

implementation), TXT,

, Intel EPT,

, Intel x8 SDDC,

'', ''

'' except X7542 * 65xx models support single- and dual-processor configurations, while 75xx models support up to 8-processor configurations * Transistors: 2.3 billion *

size: 684 mm² * Steppings: D0

Xeon E7 (multiprocessor)

"
Westmere-EX Xeon ( ) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same ar ...
" (32 nm) Expandable

* Based on Westmere microarchitecture. * All models support: '' MMX, SSE,

, Enhanced Intel

Technology (EIST),

, XD bit (an

implementation), TXT,

, Intel EPT,

, Intel DDDC,

Hyper-threading Hyper-threading (officially called Hyper-Threading Technology or HT Technology and abbreviated as HTT or HT) is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multip ...

(except E7-8837),

, Smart Cache.'' * 28xx models support single- and dual-processor configurations, 48xx models support up to four-processor configurations, 88xx models support up to eight-processor configurations. * Transistors: 2.6 billion *

size: 513 mm² * Steppings: A2

References

{{Intel processors, * Intel Xeon (Nehalem)

Xeon 3000-series (uniprocessor)

" Lynnfield" (45 nm)

" Bloomfield" (45 nm)

" Jasper Forest" (45 nm)

" Clarkdale" ( MCP, 32 nm)

"Gulftown Gulftown or Westmere-EP is the codename of an up to six-core hyperthreaded Intel processor able to run up to 12 threads in parallel. It is based on Westmere microarchitecture, the 32 nm shrink of Nehalem. Originally rumored to be called the Int ..." (32 nm)

Xeon 5000-series (dual-processor)

" Gainestown" (45 nm)

" Jasper Forest" (45 nm)

" Westmere-EP" (32 nm) Efficient Performance

Xeon 7000-series (multiprocessor)

"Beckton Beckton is a suburb in east London, England, located east of Charing Cross and part of the London Borough of Newham. Adjacent to the River Thames, the area consisted of unpopulated marshland known as the East Ham Levels in the parishes of Bark ..." (45 nm)

Xeon E7 (multiprocessor)

"Westmere-EX Xeon ( ) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same ar ..." (32 nm) Expandable

References

"
Gulftown Gulftown or Westmere-EP is the codename of an up to six-core hyperthreaded Intel processor able to run up to 12 threads in parallel. It is based on Westmere microarchitecture, the 32 nm shrink of Nehalem. Originally rumored to be called the Int ...
" (32 nm)

"
Beckton Beckton is a suburb in east London, England, located east of Charing Cross and part of the London Borough of Newham. Adjacent to the River Thames, the area consisted of unpopulated marshland known as the East Ham Levels in the parishes of Bark ...
" (45 nm)

"
Westmere-EX Xeon ( ) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same ar ...
" (32 nm) Expandable