High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it is the task to verify a model that represents hardware above
register-transfer level
In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those ...
(RTL) abstract level. For
high-level synthesis
High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that takes an abstract behavioral specification of a digital ...
(HLS or C synthesis), HLV is to HLS as
functional verification
In electronic design automation, functional verification is the task of verifying that the logic design conforms to specification. Functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a ...
is to
logic synthesis
In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a com ...
.
Electronic
digital hardware
Digital electronics is a field of electronics involving the study of digital signals and the engineering of devices that use or produce them. This is in contrast to analog electronics and analog signals.
Digital electronic circuits are usually ...
design has evolved from low level abstraction at
gate level to
register transfer level
In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those ...
(RTL), the abstraction level above RTL is commonly called high-level, ESL, or behavioral/algorithmic level.
In
high-level synthesis
High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that takes an abstract behavioral specification of a digital ...
, behavioral/algorithmic designs in ANSI C/C++/SystemC code is synthesized to RTL, which is then synthesized into gate level through
logic synthesis
In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a com ...
.
Functional verification
In electronic design automation, functional verification is the task of verifying that the logic design conforms to specification. Functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a ...
is the task to make sure a design at RTL or gate level conforms to a specification. As logic synthesis matures, most functional verification is done at the higher abstraction, i.e. at RTL level, the correctness of logic synthesis tool in the translating process from RTL description to gate netlist is of less concern today.
High-level synthesis is still an emerging technology, so High-level verification today has two important areas under development
# to validate HLS is correct in the translation process, i.e. to validate the design before and after HLS are equivalent, typically through
formal methods
In computer science, formal methods are mathematically rigorous techniques for the specification, development, and verification of software and hardware systems. The use of formal methods for software and hardware design is motivated by the exp ...
# to verify a design in ANSI C/C++/SystemC code is conforming to a specification, typically through
logic simulation
Logic simulation is the use of simulation software to predict the behavior of digital circuits and hardware description languages. Simulation can be performed at varying degrees of physical abstraction, such as at the transistor level, gate le ...
.
Terminology
History
Product areas
* Formal Solution: Verify high level models against RTL designs
* Simulation Solution: Intelligent stimulus generation, code and functional coverage, temporal assertion checker
See also
*
Accellera
Accellera Systems Initiative (Accellera) is a standards organization that supports a mix of user and vendor standards and open interfaces development in the area of electronic design automation (EDA) and integrated circuit (IC) design and manufactu ...
*
Electronic system-level Electronic system level (ESL) design and verification is an electronic design methodology, focused on higher abstraction level concerns. The term ''Electronic System Level'' or ''ESL Design'' was first defined by Gartner Dataquest, an EDA-industry ...
(ESL)
*
Formal verification
In the context of hardware and software systems, formal verification is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal met ...
*
Property Specification Language Property Specification Language (PSL) is a temporal logic extending linear temporal logic with a range of operators for both ease of expression and enhancement of expressive power. PSL makes an extensive use of regular expressions and syntactic su ...
(PSL)
*
SystemC
*
SystemVerilog
SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since ...
*
Transaction-level modeling (TLM)
References
* {{Cite book, title = 1800-2005 — IEEE Standard for System Verilog—Unified Hardware Design, Specification, and Verification Language, doi = 10.1109/IEEESTD.2005.97972, year = 2005, isbn = 0-7381-4810-5
* Accellera PSL v1.1 LRM, Accellera
"Native SystemC Assertion for OCP property checking" www.nascug.org
"Checking for TLM2.0 Compliance, Why bother?" www.nascug.org
External links
Accellera(formerly OSCI; Open SystemC Initiative)
Electronic design automation