BACPAC, or the Berkeley Advanced Chip Performance Calculator, is a software program to explore the effect of changes in IC technology. The use enters a set of fairly fundamental properties of the technology (such as interconnect layer thickness, and logic depth) and the program estimates the system level performance of an IC built with these assumptions. Previous work in this area can be found in and, but these do not consider many of the effects of deep-sub-micrometre interconnect. BACPAC is based on the work in.
[D. Sylvester and K. Keutzer, “Getting to the bottom of deep submicron,” Proc. of International Conference on CAD, pp. 203–211, 1998.]
BACPAC uses analytical approximations for system properties such as delay and interconnect requirements. The intent is not absolute accuracy for a given design, but to show trends and effects of technology changes.
Inputs to BACPAC
Interconnect
*Number of routing layers
*Pitches (center to center distance of each layer)
*
Resistivity
Electrical resistivity (also called specific electrical resistance or volume resistivity) is a fundamental property of a material that measures how strongly it resists electric current. A low resistivity indicates a material that readily allows ...
of the wires
*
Dielectric constant
The relative permittivity (in older texts, dielectric constant) is the permittivity of a material expressed as a ratio with the electric permittivity of a vacuum. A dielectric is an insulating material, and the dielectric constant of an insulat ...
of the insulators between the layers
Device
*V
dd, also called supply voltage
*V
t, also called
threshold voltage
The threshold voltage, commonly abbreviated as Vth or VGS(th), of a field-effect transistor (FET) is the minimum gate-to-source voltage (VGS) that is needed to create a conducting path between the source and drain terminals. It is an important s ...
*
Gate oxide
The gate oxide is the dielectric layer that separates the gate terminal of a MOSFET (metal-oxide-semiconductor field-effect transistor) from the underlying source and drain terminals as well as the conductive channel that connects source and drain ...
thickness of the MOS transistors
*Drain current
*
Fan-in
Fan-in is the number of inputs a logic gate can handle. For instance the fan-in for the AND gate shown in the figure is 3. Physical logic gates with a large fan-in tend to be slower than those with a small fan-in. This is because the complexity o ...
(number of inputs for each gate, on the average)
System-level
*Block design size (number of gates in each block)
*Silicon efficiency (depends on design style - custom, ASIC,
gate array
A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICs) using a prefabricated chip with components that are later interconnected into logic devices (e.g. NAND gates, flip-flops, etc.) according ...
, and so on)
*logic depth (number of gates between state elements)
*Rent's exponent (how the number of connections varies with block size - see
Rent's rule Rent's rule pertains to the organization of computing logic, specifically the relationship between the number of external signal connections to a logic block (i.e., the number of "pins") with the number of logic gates in the logic block, and has bee ...
.)
BACPAC outputs
Delay analysis
*Chip area
*Maximum
clock frequency
In computing, the clock rate or clock speed typically refers to the frequency at which the clock generator of a processor can generate pulses, which are used to synchronize the operations of its components, and is used as an indicator of the pr ...
- how fast the chip can run
*Optimized device sizes - estimated devices sizes to make it run this fast
*Interconnect RC
*Average wirelength (local & global)
*Ratio of wire delay to gate delay
Noise analysis
*Clock frequency with noise
*Newly optimized device sizes for the clock distribution network
*Ratio of wire delay to gate delay
Wirability analysis
*Wiring capacity
*Wiring requirements (global & local),
*Wiring needs for clock distribution
*Wiring needs for the power distribution network
Power analysis
*Total power consumption, divided into sub-categories:
**Clock (power needed to distribute the clock across the chip)
**I/O (power needed to get needed signals on and off the chip)
**memory (power needed to retain and access data in the internal memories)
**global wiring (power dissipated in the global wiring)
**logic (power dissipated in the logic gates themselves)
**short-circuit (power wasted inside the gates from pull-up and pull down transistors fighting each other during switching)
**leakage (power that flows through the gate even when it is not switching)
Yield analysis
*Projected yields for excellent, average, and poor process control using a negative binomial yield mode
References
{{reflist
External links
Main BACPAC web site
Electronic design automation software